{"block":{"name":"xbar_main","variant":null,"commit":"a0994129303fcb17a56df9a84a3babc5b4069141","commit_short":"a099412","branch":"master","url":"https://github.com/lowRISC/opentitan/tree/a0994129303fcb17a56df9a84a3babc5b4069141","revision_info":"GitHub Revision: [`a099412`](https://github.com/lowrisc/opentitan/tree/a0994129303fcb17a56df9a84a3babc5b4069141)"},"tool":{"name":"vcs","version":"unknown"},"timestamp":"2026-08-28T21:54:34Z","build_seed":null,"testplan_ref":"https://opentitan.org/book/hw/ip/tlul/data/tlul_testplan.html","stages":{"V1":{"testpoints":{"xbar_smoke":{"tests":{"xbar_smoke":{"max_time":1.5788820711895823,"sim_time":0.0,"passed":0,"total":20,"percent":0.0}},"passed":0,"total":20,"percent":0.0}},"passed":0,"total":20,"percent":0.0},"V2":{"testpoints":{"xbar_base_random_sequence":{"tests":{"xbar_random":{"max_time":1.3940942184999585,"sim_time":0.0,"passed":0,"total":20,"percent":0.0}},"passed":0,"total":20,"percent":0.0},"xbar_random_delay":{"tests":{"xbar_smoke_zero_delays":{"max_time":1.5473264455795288,"sim_time":0.0,"passed":0,"total":20,"percent":0.0},"xbar_smoke_large_delays":{"max_time":0.8847133880481124,"sim_time":0.0,"passed":0,"total":20,"percent":0.0},"xbar_smoke_slow_rsp":{"max_time":2.027143836952746,"sim_time":0.0,"passed":0,"total":20,"percent":0.0},"xbar_random_zero_delays":{"max_time":1.60352239664644,"sim_time":0.0,"passed":0,"total":20,"percent":0.0},"xbar_random_large_delays":{"max_time":1.5387659184634686,"sim_time":0.0,"passed":0,"total":20,"percent":0.0},"xbar_random_slow_rsp":{"max_time":1.5615521930158138,"sim_time":0.0,"passed":0,"total":20,"percent":0.0}},"passed":0,"total":120,"percent":0.0},"xbar_unmapped_address":{"tests":{"xbar_unmapped_addr":{"max_time":1.5909609757363796,"sim_time":0.0,"passed":0,"total":20,"percent":0.0},"xbar_error_and_unmapped_addr":{"max_time":1.544412692077458,"sim_time":0.0,"passed":0,"total":20,"percent":0.0}},"passed":0,"total":40,"percent":0.0},"xbar_error_cases":{"tests":{"xbar_error_random":{"max_time":1.597241261973977,"sim_time":0.0,"passed":0,"total":20,"percent":0.0},"xbar_error_and_unmapped_addr":{"max_time":1.544412692077458,"sim_time":0.0,"passed":0,"total":20,"percent":0.0}},"passed":0,"total":40,"percent":0.0},"xbar_all_access_same_device":{"tests":{"xbar_access_same_device":{"max_time":0.8971843495965004,"sim_time":0.0,"passed":0,"total":20,"percent":0.0},"xbar_access_same_device_slow_rsp":{"max_time":1.5572067722678185,"sim_time":0.0,"passed":0,"total":50,"percent":0.0}},"passed":0,"total":70,"percent":0.0},"xbar_all_hosts_use_same_source_id":{"tests":{"xbar_same_source":{"max_time":0.8952981643378735,"sim_time":0.0,"passed":0,"total":20,"percent":0.0}},"passed":0,"total":20,"percent":0.0},"xbar_stress_all":{"tests":{"xbar_stress_all":{"max_time":1.5673590023070574,"sim_time":0.0,"passed":0,"total":20,"percent":0.0},"xbar_stress_all_with_error":{"max_time":1.6401221239939332,"sim_time":0.0,"passed":0,"total":50,"percent":0.0}},"passed":0,"total":70,"percent":0.0},"xbar_stress_with_reset":{"tests":{"xbar_stress_all_with_rand_reset":{"max_time":1.54383360221982,"sim_time":0.0,"passed":0,"total":20,"percent":0.0},"xbar_stress_all_with_reset_error":{"max_time":1.5469003869220614,"sim_time":0.0,"passed":0,"total":50,"percent":0.0}},"passed":0,"total":70,"percent":0.0}},"passed":0,"total":430,"percent":0.0}},"coverage":{"code":{"block":null,"line_statement":null,"branch":null,"condition_expression":null,"toggle":null,"fsm":null},"assertion":null,"functional":null},"cov_report_page":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/cov_report/dashboard.html","vplan_report_page":null,"vplan_coverage":null,"failed_jobs":{"buckets":{"Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$']":[{"name":"xbar_smoke","qual_name":"0.xbar_smoke.46877292718367765813435572576902053484534980158151732601985030131572338222088","seed":46877292718367765813435572576902053484534980158151732601985030131572338222088,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/0.xbar_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/0.xbar_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3408028680 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke.3408028680' seed=46877292718367765813435572576902053484534980158151732601985030131572338222088 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=46877292718367765813435572576902053484534980158151732601985030131572338222088 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/0.xbar_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_zero_delays","qual_name":"0.xbar_smoke_zero_delays.90155909735281546791933274399573017085089657058538977262657837699090709614709","seed":90155909735281546791933274399573017085089657058538977262657837699090709614709,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/0.xbar_smoke_zero_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/0.xbar_smoke_zero_delays/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1791889525 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_zero_delays.1791889525' seed=90155909735281546791933274399573017085089657058538977262657837699090709614709 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=90155909735281546791933274399573017085089657058538977262657837699090709614709 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/0.xbar_smoke_zero_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_large_delays","qual_name":"0.xbar_smoke_large_delays.103229655045180352935367835826128022595491559598887173444349331312280901371394","seed":103229655045180352935367835826128022595491559598887173444349331312280901371394,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/0.xbar_smoke_large_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/0.xbar_smoke_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=313378306 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_large_delays.313378306' seed=103229655045180352935367835826128022595491559598887173444349331312280901371394 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=103229655045180352935367835826128022595491559598887173444349331312280901371394 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/0.xbar_smoke_large_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_slow_rsp","qual_name":"0.xbar_smoke_slow_rsp.79033384450215604300198464213352101719486381015950484371763814451012635834887","seed":79033384450215604300198464213352101719486381015950484371763814451012635834887,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/0.xbar_smoke_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/0.xbar_smoke_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=470399495 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_slow_rsp.470399495' seed=79033384450215604300198464213352101719486381015950484371763814451012635834887 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=79033384450215604300198464213352101719486381015950484371763814451012635834887 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/0.xbar_smoke_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random","qual_name":"0.xbar_random.60680248140537671421517572655735077451902134014281383619037968021462580503389","seed":60680248140537671421517572655735077451902134014281383619037968021462580503389,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/0.xbar_random/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/0.xbar_random/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3110380381 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random.3110380381' seed=60680248140537671421517572655735077451902134014281383619037968021462580503389 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=60680248140537671421517572655735077451902134014281383619037968021462580503389 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/0.xbar_random/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_zero_delays","qual_name":"0.xbar_random_zero_delays.36104830096883102448982762385923781958043496607667028972290795804490964122434","seed":36104830096883102448982762385923781958043496607667028972290795804490964122434,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/0.xbar_random_zero_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/0.xbar_random_zero_delays/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2505816898 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_zero_delays.2505816898' seed=36104830096883102448982762385923781958043496607667028972290795804490964122434 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=36104830096883102448982762385923781958043496607667028972290795804490964122434 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/0.xbar_random_zero_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_large_delays","qual_name":"0.xbar_random_large_delays.42319503365673598569403970165012598006737379515739245325789071032939706764729","seed":42319503365673598569403970165012598006737379515739245325789071032939706764729,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/0.xbar_random_large_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/0.xbar_random_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=669437369 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_large_delays.669437369' seed=42319503365673598569403970165012598006737379515739245325789071032939706764729 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=42319503365673598569403970165012598006737379515739245325789071032939706764729 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/0.xbar_random_large_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_slow_rsp","qual_name":"0.xbar_random_slow_rsp.81927731961142576668422708738410862386271448553810519252728323822243787055639","seed":81927731961142576668422708738410862386271448553810519252728323822243787055639,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/0.xbar_random_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/0.xbar_random_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1412178455 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_slow_rsp.1412178455' seed=81927731961142576668422708738410862386271448553810519252728323822243787055639 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=81927731961142576668422708738410862386271448553810519252728323822243787055639 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/0.xbar_random_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device","qual_name":"0.xbar_access_same_device.27273893293955082982514668556051181109009240114694952759215834532310197251656","seed":27273893293955082982514668556051181109009240114694952759215834532310197251656,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/0.xbar_access_same_device/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/0.xbar_access_same_device/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3091246664 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device.3091246664' seed=27273893293955082982514668556051181109009240114694952759215834532310197251656 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=27273893293955082982514668556051181109009240114694952759215834532310197251656 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/0.xbar_access_same_device/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"0.xbar_access_same_device_slow_rsp.70881916968941025485016826012005959651592383057785922926703555856885100378838","seed":70881916968941025485016826012005959651592383057785922926703555856885100378838,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/0.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/0.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3401120470 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device_slow_rsp.3401120470' seed=70881916968941025485016826012005959651592383057785922926703555856885100378838 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=70881916968941025485016826012005959651592383057785922926703555856885100378838 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/0.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_same_source","qual_name":"0.xbar_same_source.35162299640078745778277815318363821516525821818506945071417508420034115801778","seed":35162299640078745778277815318363821516525821818506945071417508420034115801778,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/0.xbar_same_source/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/0.xbar_same_source/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2473464498 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_same_source.2473464498' seed=35162299640078745778277815318363821516525821818506945071417508420034115801778 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=35162299640078745778277815318363821516525821818506945071417508420034115801778 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/0.xbar_same_source/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_same_source_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_random","qual_name":"0.xbar_error_random.104656827964038294059657624990707371097143473289856123950321285467073869221228","seed":104656827964038294059657624990707371097143473289856123950321285467073869221228,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/0.xbar_error_random/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/0.xbar_error_random/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4063202668 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_error_random.4063202668' seed=104656827964038294059657624990707371097143473289856123950321285467073869221228 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=104656827964038294059657624990707371097143473289856123950321285467073869221228 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/0.xbar_error_random/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_unmapped_addr","qual_name":"0.xbar_unmapped_addr.35366880317852827979021769329901801795806357248219320849036817784036566764252","seed":35366880317852827979021769329901801795806357248219320849036817784036566764252,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/0.xbar_unmapped_addr/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/0.xbar_unmapped_addr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=758909660 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_unmapped_addr.758909660' seed=35366880317852827979021769329901801795806357248219320849036817784036566764252 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=35366880317852827979021769329901801795806357248219320849036817784036566764252 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/0.xbar_unmapped_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_and_unmapped_addr","qual_name":"0.xbar_error_and_unmapped_addr.113107004587573065089485935051786459450318608144075536259213833399693987867353","seed":113107004587573065089485935051786459450318608144075536259213833399693987867353,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/0.xbar_error_and_unmapped_addr/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/0.xbar_error_and_unmapped_addr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3190090457 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_error_and_unmapped_addr.3190090457' seed=113107004587573065089485935051786459450318608144075536259213833399693987867353 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=113107004587573065089485935051786459450318608144075536259213833399693987867353 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/0.xbar_error_and_unmapped_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all","qual_name":"0.xbar_stress_all.22743468408015201117707451406331927153681908080885807728584099904317477292893","seed":22743468408015201117707451406331927153681908080885807728584099904317477292893,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/0.xbar_stress_all/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/0.xbar_stress_all/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=216206173 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all.216206173' seed=22743468408015201117707451406331927153681908080885807728584099904317477292893 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=22743468408015201117707451406331927153681908080885807728584099904317477292893 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/0.xbar_stress_all/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_rand_reset","qual_name":"0.xbar_stress_all_with_rand_reset.112978540479970112480870287324755104833498548276258163983031742956918748575765","seed":112978540479970112480870287324755104833498548276258163983031742956918748575765,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/0.xbar_stress_all_with_rand_reset/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/0.xbar_stress_all_with_rand_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=166295573 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_rand_reset.166295573' seed=112978540479970112480870287324755104833498548276258163983031742956918748575765 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=112978540479970112480870287324755104833498548276258163983031742956918748575765 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/0.xbar_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"0.xbar_stress_all_with_error.28094546606982793874886039890916802048228978466289285534565025736505262387131","seed":28094546606982793874886039890916802048228978466289285534565025736505262387131,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/0.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/0.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2355146683 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_error.2355146683' seed=28094546606982793874886039890916802048228978466289285534565025736505262387131 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=28094546606982793874886039890916802048228978466289285534565025736505262387131 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/0.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"0.xbar_stress_all_with_reset_error.89198567831334918525355658480783618420390376287543845626503422617498290797393","seed":89198567831334918525355658480783618420390376287543845626503422617498290797393,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/0.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/0.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3006839633 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_reset_error.3006839633' seed=89198567831334918525355658480783618420390376287543845626503422617498290797393 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=89198567831334918525355658480783618420390376287543845626503422617498290797393 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/0.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke","qual_name":"1.xbar_smoke.9109164270558230289415863747650371240715806148028832004407043791761136410456","seed":9109164270558230289415863747650371240715806148028832004407043791761136410456,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/1.xbar_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/1.xbar_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=689692504 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke.689692504' seed=9109164270558230289415863747650371240715806148028832004407043791761136410456 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=9109164270558230289415863747650371240715806148028832004407043791761136410456 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/1.xbar_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_zero_delays","qual_name":"1.xbar_smoke_zero_delays.99414904296306776618702542540695299082620187953012535230183660664778412830432","seed":99414904296306776618702542540695299082620187953012535230183660664778412830432,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/1.xbar_smoke_zero_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/1.xbar_smoke_zero_delays/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3693391584 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_zero_delays.3693391584' seed=99414904296306776618702542540695299082620187953012535230183660664778412830432 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=99414904296306776618702542540695299082620187953012535230183660664778412830432 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/1.xbar_smoke_zero_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_large_delays","qual_name":"1.xbar_smoke_large_delays.2552046009024332067821831083215168540216544134875364078268470665692318849597","seed":2552046009024332067821831083215168540216544134875364078268470665692318849597,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/1.xbar_smoke_large_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/1.xbar_smoke_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2349914685 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_large_delays.2349914685' seed=2552046009024332067821831083215168540216544134875364078268470665692318849597 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=2552046009024332067821831083215168540216544134875364078268470665692318849597 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/1.xbar_smoke_large_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_slow_rsp","qual_name":"1.xbar_smoke_slow_rsp.4211123051577844168384420933432614315570619722508722535424786735850605165750","seed":4211123051577844168384420933432614315570619722508722535424786735850605165750,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/1.xbar_smoke_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/1.xbar_smoke_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3949116598 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_slow_rsp.3949116598' seed=4211123051577844168384420933432614315570619722508722535424786735850605165750 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=4211123051577844168384420933432614315570619722508722535424786735850605165750 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/1.xbar_smoke_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random","qual_name":"1.xbar_random.44636882517568368805747899678572186166605127884334164227583992933866827790750","seed":44636882517568368805747899678572186166605127884334164227583992933866827790750,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/1.xbar_random/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/1.xbar_random/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3260397982 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random.3260397982' seed=44636882517568368805747899678572186166605127884334164227583992933866827790750 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=44636882517568368805747899678572186166605127884334164227583992933866827790750 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/1.xbar_random/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_zero_delays","qual_name":"1.xbar_random_zero_delays.47361194261229267717548798200509641538950224006734212541126322032792006907298","seed":47361194261229267717548798200509641538950224006734212541126322032792006907298,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/1.xbar_random_zero_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/1.xbar_random_zero_delays/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=485578146 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_zero_delays.485578146' seed=47361194261229267717548798200509641538950224006734212541126322032792006907298 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=47361194261229267717548798200509641538950224006734212541126322032792006907298 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/1.xbar_random_zero_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_large_delays","qual_name":"1.xbar_random_large_delays.25505921101547983563396141576513020437421509192071187950539053346078964759820","seed":25505921101547983563396141576513020437421509192071187950539053346078964759820,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/1.xbar_random_large_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/1.xbar_random_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1864809740 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_large_delays.1864809740' seed=25505921101547983563396141576513020437421509192071187950539053346078964759820 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=25505921101547983563396141576513020437421509192071187950539053346078964759820 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/1.xbar_random_large_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_slow_rsp","qual_name":"1.xbar_random_slow_rsp.37507419139749291017347753055623740802965660971004144729466030247398049462820","seed":37507419139749291017347753055623740802965660971004144729466030247398049462820,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/1.xbar_random_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/1.xbar_random_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3250993700 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_slow_rsp.3250993700' seed=37507419139749291017347753055623740802965660971004144729466030247398049462820 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=37507419139749291017347753055623740802965660971004144729466030247398049462820 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/1.xbar_random_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device","qual_name":"1.xbar_access_same_device.29504348411880102362042915814147067039846247108780155428788813132169294287875","seed":29504348411880102362042915814147067039846247108780155428788813132169294287875,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/1.xbar_access_same_device/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/1.xbar_access_same_device/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=680170499 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device.680170499' seed=29504348411880102362042915814147067039846247108780155428788813132169294287875 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=29504348411880102362042915814147067039846247108780155428788813132169294287875 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/1.xbar_access_same_device/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"1.xbar_access_same_device_slow_rsp.51855057481460384784496572840458670578799153958620613659450311821124051969316","seed":51855057481460384784496572840458670578799153958620613659450311821124051969316,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/1.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/1.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1027384612 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device_slow_rsp.1027384612' seed=51855057481460384784496572840458670578799153958620613659450311821124051969316 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=51855057481460384784496572840458670578799153958620613659450311821124051969316 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/1.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_same_source","qual_name":"1.xbar_same_source.95660269444734011945527382406094551117081354298032854820289802566606459814176","seed":95660269444734011945527382406094551117081354298032854820289802566606459814176,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/1.xbar_same_source/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/1.xbar_same_source/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=889504032 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_same_source.889504032' seed=95660269444734011945527382406094551117081354298032854820289802566606459814176 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=95660269444734011945527382406094551117081354298032854820289802566606459814176 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/1.xbar_same_source/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_same_source_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_random","qual_name":"1.xbar_error_random.45583470239885251669285757575357886394212507827381871698379585540835777620445","seed":45583470239885251669285757575357886394212507827381871698379585540835777620445,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/1.xbar_error_random/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/1.xbar_error_random/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1313778141 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_error_random.1313778141' seed=45583470239885251669285757575357886394212507827381871698379585540835777620445 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=45583470239885251669285757575357886394212507827381871698379585540835777620445 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/1.xbar_error_random/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_unmapped_addr","qual_name":"1.xbar_unmapped_addr.108235344106138967714487252122460561887707114661843136440635170792214695366011","seed":108235344106138967714487252122460561887707114661843136440635170792214695366011,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/1.xbar_unmapped_addr/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/1.xbar_unmapped_addr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3747466619 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_unmapped_addr.3747466619' seed=108235344106138967714487252122460561887707114661843136440635170792214695366011 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=108235344106138967714487252122460561887707114661843136440635170792214695366011 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/1.xbar_unmapped_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_and_unmapped_addr","qual_name":"1.xbar_error_and_unmapped_addr.43730869721184399590306819292511541402002246367257074377131163653205923049276","seed":43730869721184399590306819292511541402002246367257074377131163653205923049276,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/1.xbar_error_and_unmapped_addr/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/1.xbar_error_and_unmapped_addr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4180782908 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_error_and_unmapped_addr.4180782908' seed=43730869721184399590306819292511541402002246367257074377131163653205923049276 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=43730869721184399590306819292511541402002246367257074377131163653205923049276 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/1.xbar_error_and_unmapped_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all","qual_name":"1.xbar_stress_all.32181969135343323556056428241382501369142278269780657427101733692059053339644","seed":32181969135343323556056428241382501369142278269780657427101733692059053339644,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/1.xbar_stress_all/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/1.xbar_stress_all/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=179975164 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all.179975164' seed=32181969135343323556056428241382501369142278269780657427101733692059053339644 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=32181969135343323556056428241382501369142278269780657427101733692059053339644 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/1.xbar_stress_all/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_rand_reset","qual_name":"1.xbar_stress_all_with_rand_reset.70484476752910821546315398641363898529659494014366660639880001677353285385286","seed":70484476752910821546315398641363898529659494014366660639880001677353285385286,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/1.xbar_stress_all_with_rand_reset/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/1.xbar_stress_all_with_rand_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2614950982 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_rand_reset.2614950982' seed=70484476752910821546315398641363898529659494014366660639880001677353285385286 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=70484476752910821546315398641363898529659494014366660639880001677353285385286 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/1.xbar_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"1.xbar_stress_all_with_error.98252715397607832032079575496617693021836164265657019326487140052855006604438","seed":98252715397607832032079575496617693021836164265657019326487140052855006604438,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/1.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/1.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3933121686 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_error.3933121686' seed=98252715397607832032079575496617693021836164265657019326487140052855006604438 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=98252715397607832032079575496617693021836164265657019326487140052855006604438 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/1.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"1.xbar_stress_all_with_reset_error.95389320445371119090136992471273691487680329700260432237186351930907260851374","seed":95389320445371119090136992471273691487680329700260432237186351930907260851374,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/1.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/1.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2978714798 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_reset_error.2978714798' seed=95389320445371119090136992471273691487680329700260432237186351930907260851374 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=95389320445371119090136992471273691487680329700260432237186351930907260851374 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/1.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke","qual_name":"2.xbar_smoke.86051885174988140545459291897958271640567826563900478728858744707860265579668","seed":86051885174988140545459291897958271640567826563900478728858744707860265579668,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/2.xbar_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/2.xbar_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2327458964 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke.2327458964' seed=86051885174988140545459291897958271640567826563900478728858744707860265579668 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=86051885174988140545459291897958271640567826563900478728858744707860265579668 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/2.xbar_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_zero_delays","qual_name":"2.xbar_smoke_zero_delays.113893299047034475793195097849070661986901643014360464525089163657147398621187","seed":113893299047034475793195097849070661986901643014360464525089163657147398621187,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/2.xbar_smoke_zero_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/2.xbar_smoke_zero_delays/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1200228355 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_zero_delays.1200228355' seed=113893299047034475793195097849070661986901643014360464525089163657147398621187 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=113893299047034475793195097849070661986901643014360464525089163657147398621187 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/2.xbar_smoke_zero_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_large_delays","qual_name":"2.xbar_smoke_large_delays.112242107046254761826494139115490028740373702844022591796105328060279714387840","seed":112242107046254761826494139115490028740373702844022591796105328060279714387840,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/2.xbar_smoke_large_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/2.xbar_smoke_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2513344384 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_large_delays.2513344384' seed=112242107046254761826494139115490028740373702844022591796105328060279714387840 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=112242107046254761826494139115490028740373702844022591796105328060279714387840 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/2.xbar_smoke_large_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_slow_rsp","qual_name":"2.xbar_smoke_slow_rsp.63762034566540400706920327070519570348872061241195271451289867181778633356447","seed":63762034566540400706920327070519570348872061241195271451289867181778633356447,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/2.xbar_smoke_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/2.xbar_smoke_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1105589407 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_slow_rsp.1105589407' seed=63762034566540400706920327070519570348872061241195271451289867181778633356447 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=63762034566540400706920327070519570348872061241195271451289867181778633356447 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/2.xbar_smoke_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random","qual_name":"2.xbar_random.92937075981109301564047511820610796623719179145199691805459161915066123941842","seed":92937075981109301564047511820610796623719179145199691805459161915066123941842,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/2.xbar_random/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/2.xbar_random/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1753610194 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random.1753610194' seed=92937075981109301564047511820610796623719179145199691805459161915066123941842 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=92937075981109301564047511820610796623719179145199691805459161915066123941842 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/2.xbar_random/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_zero_delays","qual_name":"2.xbar_random_zero_delays.97147170991348748608061841173516236521794627342773555473966512210245618490138","seed":97147170991348748608061841173516236521794627342773555473966512210245618490138,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/2.xbar_random_zero_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/2.xbar_random_zero_delays/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=945806106 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_zero_delays.945806106' seed=97147170991348748608061841173516236521794627342773555473966512210245618490138 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=97147170991348748608061841173516236521794627342773555473966512210245618490138 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/2.xbar_random_zero_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_large_delays","qual_name":"2.xbar_random_large_delays.26999854651055754893079151401067741663093806006599105377057148052023080001049","seed":26999854651055754893079151401067741663093806006599105377057148052023080001049,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/2.xbar_random_large_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/2.xbar_random_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1406803481 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_large_delays.1406803481' seed=26999854651055754893079151401067741663093806006599105377057148052023080001049 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=26999854651055754893079151401067741663093806006599105377057148052023080001049 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/2.xbar_random_large_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_slow_rsp","qual_name":"2.xbar_random_slow_rsp.104925614203755104820528237478052119995867598263970177745064676868078408005123","seed":104925614203755104820528237478052119995867598263970177745064676868078408005123,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/2.xbar_random_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/2.xbar_random_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=921662979 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_slow_rsp.921662979' seed=104925614203755104820528237478052119995867598263970177745064676868078408005123 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=104925614203755104820528237478052119995867598263970177745064676868078408005123 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/2.xbar_random_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device","qual_name":"2.xbar_access_same_device.44960498809573677804011521697473486386780507457931178551625431999491542106350","seed":44960498809573677804011521697473486386780507457931178551625431999491542106350,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/2.xbar_access_same_device/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/2.xbar_access_same_device/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1812480238 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device.1812480238' seed=44960498809573677804011521697473486386780507457931178551625431999491542106350 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=44960498809573677804011521697473486386780507457931178551625431999491542106350 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/2.xbar_access_same_device/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"2.xbar_access_same_device_slow_rsp.23710893148287566121516868995766768166134316604009233281354554249489899338522","seed":23710893148287566121516868995766768166134316604009233281354554249489899338522,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/2.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/2.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=21773082 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device_slow_rsp.21773082' seed=23710893148287566121516868995766768166134316604009233281354554249489899338522 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=23710893148287566121516868995766768166134316604009233281354554249489899338522 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/2.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_same_source","qual_name":"2.xbar_same_source.66209592783329161638508458871732918376841002490893467182972957250099513851106","seed":66209592783329161638508458871732918376841002490893467182972957250099513851106,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/2.xbar_same_source/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/2.xbar_same_source/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=522910946 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_same_source.522910946' seed=66209592783329161638508458871732918376841002490893467182972957250099513851106 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=66209592783329161638508458871732918376841002490893467182972957250099513851106 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/2.xbar_same_source/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_same_source_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_random","qual_name":"2.xbar_error_random.99605819122206147922706853661832000928537537590829464890130208428480878514879","seed":99605819122206147922706853661832000928537537590829464890130208428480878514879,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/2.xbar_error_random/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/2.xbar_error_random/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3974009535 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_error_random.3974009535' seed=99605819122206147922706853661832000928537537590829464890130208428480878514879 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=99605819122206147922706853661832000928537537590829464890130208428480878514879 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/2.xbar_error_random/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_unmapped_addr","qual_name":"2.xbar_unmapped_addr.82113300259831056843266610785794650843775233549003233280661171742434459178547","seed":82113300259831056843266610785794650843775233549003233280661171742434459178547,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/2.xbar_unmapped_addr/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/2.xbar_unmapped_addr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3288389171 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_unmapped_addr.3288389171' seed=82113300259831056843266610785794650843775233549003233280661171742434459178547 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=82113300259831056843266610785794650843775233549003233280661171742434459178547 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/2.xbar_unmapped_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_and_unmapped_addr","qual_name":"2.xbar_error_and_unmapped_addr.9195279926082894949739228765249907162628903283526215538232532649183871705250","seed":9195279926082894949739228765249907162628903283526215538232532649183871705250,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/2.xbar_error_and_unmapped_addr/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/2.xbar_error_and_unmapped_addr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2289246370 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_error_and_unmapped_addr.2289246370' seed=9195279926082894949739228765249907162628903283526215538232532649183871705250 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=9195279926082894949739228765249907162628903283526215538232532649183871705250 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/2.xbar_error_and_unmapped_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all","qual_name":"2.xbar_stress_all.16723505287039491883442317753316419903660673740699495731709601343292650656048","seed":16723505287039491883442317753316419903660673740699495731709601343292650656048,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/2.xbar_stress_all/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/2.xbar_stress_all/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4099248432 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all.4099248432' seed=16723505287039491883442317753316419903660673740699495731709601343292650656048 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=16723505287039491883442317753316419903660673740699495731709601343292650656048 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/2.xbar_stress_all/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_rand_reset","qual_name":"2.xbar_stress_all_with_rand_reset.102044470052640907442119307892888076140324332924815044797070733350610895188978","seed":102044470052640907442119307892888076140324332924815044797070733350610895188978,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/2.xbar_stress_all_with_rand_reset/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/2.xbar_stress_all_with_rand_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3820041202 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_rand_reset.3820041202' seed=102044470052640907442119307892888076140324332924815044797070733350610895188978 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=102044470052640907442119307892888076140324332924815044797070733350610895188978 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/2.xbar_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"2.xbar_stress_all_with_error.92265604827145591853935561814739252372695776618315780768994451458534310393902","seed":92265604827145591853935561814739252372695776618315780768994451458534310393902,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/2.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/2.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1990965294 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_error.1990965294' seed=92265604827145591853935561814739252372695776618315780768994451458534310393902 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=92265604827145591853935561814739252372695776618315780768994451458534310393902 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/2.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"2.xbar_stress_all_with_reset_error.47909607041771661545738388813831848468902611377963220598717618063945465837359","seed":47909607041771661545738388813831848468902611377963220598717618063945465837359,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/2.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/2.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1858844463 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_reset_error.1858844463' seed=47909607041771661545738388813831848468902611377963220598717618063945465837359 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=47909607041771661545738388813831848468902611377963220598717618063945465837359 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/2.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke","qual_name":"3.xbar_smoke.99751745388728287327212098698517003287881571665424363458296612878141440519108","seed":99751745388728287327212098698517003287881571665424363458296612878141440519108,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/3.xbar_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/3.xbar_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3356093380 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke.3356093380' seed=99751745388728287327212098698517003287881571665424363458296612878141440519108 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=99751745388728287327212098698517003287881571665424363458296612878141440519108 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/3.xbar_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_zero_delays","qual_name":"3.xbar_smoke_zero_delays.53911249102930231123154482594504459950329848425279761801313217349466691567792","seed":53911249102930231123154482594504459950329848425279761801313217349466691567792,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/3.xbar_smoke_zero_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/3.xbar_smoke_zero_delays/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=657031344 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_zero_delays.657031344' seed=53911249102930231123154482594504459950329848425279761801313217349466691567792 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=53911249102930231123154482594504459950329848425279761801313217349466691567792 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/3.xbar_smoke_zero_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_large_delays","qual_name":"3.xbar_smoke_large_delays.18736182040939716558302781787316755505797531500614959973909221878925232717391","seed":18736182040939716558302781787316755505797531500614959973909221878925232717391,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/3.xbar_smoke_large_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/3.xbar_smoke_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=215498319 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_large_delays.215498319' seed=18736182040939716558302781787316755505797531500614959973909221878925232717391 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=18736182040939716558302781787316755505797531500614959973909221878925232717391 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/3.xbar_smoke_large_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_slow_rsp","qual_name":"3.xbar_smoke_slow_rsp.59458876699599742239371920430782634197300262718768892326791943501189273651594","seed":59458876699599742239371920430782634197300262718768892326791943501189273651594,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/3.xbar_smoke_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/3.xbar_smoke_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1636600202 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_slow_rsp.1636600202' seed=59458876699599742239371920430782634197300262718768892326791943501189273651594 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=59458876699599742239371920430782634197300262718768892326791943501189273651594 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/3.xbar_smoke_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random","qual_name":"3.xbar_random.23703600835406466039931979385812998615923472872851826826774972160853113344330","seed":23703600835406466039931979385812998615923472872851826826774972160853113344330,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/3.xbar_random/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/3.xbar_random/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1156878666 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random.1156878666' seed=23703600835406466039931979385812998615923472872851826826774972160853113344330 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=23703600835406466039931979385812998615923472872851826826774972160853113344330 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/3.xbar_random/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_zero_delays","qual_name":"3.xbar_random_zero_delays.61144241264094619931506889405462287144275284272973531932143058862595339159874","seed":61144241264094619931506889405462287144275284272973531932143058862595339159874,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/3.xbar_random_zero_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/3.xbar_random_zero_delays/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2954594626 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_zero_delays.2954594626' seed=61144241264094619931506889405462287144275284272973531932143058862595339159874 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=61144241264094619931506889405462287144275284272973531932143058862595339159874 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/3.xbar_random_zero_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_large_delays","qual_name":"3.xbar_random_large_delays.73384937929474530204728942065832922193464533140462038757035462676129374731278","seed":73384937929474530204728942065832922193464533140462038757035462676129374731278,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/3.xbar_random_large_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/3.xbar_random_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3376086030 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_large_delays.3376086030' seed=73384937929474530204728942065832922193464533140462038757035462676129374731278 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=73384937929474530204728942065832922193464533140462038757035462676129374731278 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/3.xbar_random_large_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_slow_rsp","qual_name":"3.xbar_random_slow_rsp.64404413608704797591914940813204016254964501205889185975025585759525751724265","seed":64404413608704797591914940813204016254964501205889185975025585759525751724265,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/3.xbar_random_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/3.xbar_random_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3848247529 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_slow_rsp.3848247529' seed=64404413608704797591914940813204016254964501205889185975025585759525751724265 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=64404413608704797591914940813204016254964501205889185975025585759525751724265 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/3.xbar_random_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device","qual_name":"3.xbar_access_same_device.16350046764964895836001055278590307805239618810172808529936736472616059984185","seed":16350046764964895836001055278590307805239618810172808529936736472616059984185,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/3.xbar_access_same_device/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/3.xbar_access_same_device/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3511605561 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device.3511605561' seed=16350046764964895836001055278590307805239618810172808529936736472616059984185 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=16350046764964895836001055278590307805239618810172808529936736472616059984185 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/3.xbar_access_same_device/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"3.xbar_access_same_device_slow_rsp.105792229604592424385510812713056646387641130394629209624391264830546586750836","seed":105792229604592424385510812713056646387641130394629209624391264830546586750836,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/3.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/3.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3887452020 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device_slow_rsp.3887452020' seed=105792229604592424385510812713056646387641130394629209624391264830546586750836 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=105792229604592424385510812713056646387641130394629209624391264830546586750836 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/3.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_same_source","qual_name":"3.xbar_same_source.57866877174320228206804651723196567400628119844421757044472251668836376747438","seed":57866877174320228206804651723196567400628119844421757044472251668836376747438,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/3.xbar_same_source/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/3.xbar_same_source/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2854591918 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_same_source.2854591918' seed=57866877174320228206804651723196567400628119844421757044472251668836376747438 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=57866877174320228206804651723196567400628119844421757044472251668836376747438 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/3.xbar_same_source/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_same_source_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_random","qual_name":"3.xbar_error_random.108073918371690705654282583647996364004135822033257577244683896242595179968455","seed":108073918371690705654282583647996364004135822033257577244683896242595179968455,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/3.xbar_error_random/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/3.xbar_error_random/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=529708999 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_error_random.529708999' seed=108073918371690705654282583647996364004135822033257577244683896242595179968455 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=108073918371690705654282583647996364004135822033257577244683896242595179968455 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/3.xbar_error_random/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_unmapped_addr","qual_name":"3.xbar_unmapped_addr.52284636582412223880239415323138713997408033990182096373372921583974300399832","seed":52284636582412223880239415323138713997408033990182096373372921583974300399832,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/3.xbar_unmapped_addr/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/3.xbar_unmapped_addr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1464744152 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_unmapped_addr.1464744152' seed=52284636582412223880239415323138713997408033990182096373372921583974300399832 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=52284636582412223880239415323138713997408033990182096373372921583974300399832 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/3.xbar_unmapped_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_and_unmapped_addr","qual_name":"3.xbar_error_and_unmapped_addr.1562104737846613181224104442058930190155964001819110924684920269110284813","seed":1562104737846613181224104442058930190155964001819110924684920269110284813,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/3.xbar_error_and_unmapped_addr/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/3.xbar_error_and_unmapped_addr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3967324685 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_error_and_unmapped_addr.3967324685' seed=1562104737846613181224104442058930190155964001819110924684920269110284813 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=1562104737846613181224104442058930190155964001819110924684920269110284813 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/3.xbar_error_and_unmapped_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all","qual_name":"3.xbar_stress_all.65036224682079603751023644808216982438054386598901938031701064396867268226621","seed":65036224682079603751023644808216982438054386598901938031701064396867268226621,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/3.xbar_stress_all/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/3.xbar_stress_all/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1382002237 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all.1382002237' seed=65036224682079603751023644808216982438054386598901938031701064396867268226621 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=65036224682079603751023644808216982438054386598901938031701064396867268226621 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/3.xbar_stress_all/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_rand_reset","qual_name":"3.xbar_stress_all_with_rand_reset.108465009715129784768769214360865785327758166200503582522685426205429403739071","seed":108465009715129784768769214360865785327758166200503582522685426205429403739071,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/3.xbar_stress_all_with_rand_reset/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/3.xbar_stress_all_with_rand_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=734520255 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_rand_reset.734520255' seed=108465009715129784768769214360865785327758166200503582522685426205429403739071 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=108465009715129784768769214360865785327758166200503582522685426205429403739071 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/3.xbar_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"3.xbar_stress_all_with_error.67292441034935255545424864435978255714804501158662825122818307980332093575464","seed":67292441034935255545424864435978255714804501158662825122818307980332093575464,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/3.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/3.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=856068392 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_error.856068392' seed=67292441034935255545424864435978255714804501158662825122818307980332093575464 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=67292441034935255545424864435978255714804501158662825122818307980332093575464 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/3.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"3.xbar_stress_all_with_reset_error.98997602579902035517238584053190605786285923922079506248594145804074454421108","seed":98997602579902035517238584053190605786285923922079506248594145804074454421108,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/3.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/3.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3820031604 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_reset_error.3820031604' seed=98997602579902035517238584053190605786285923922079506248594145804074454421108 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=98997602579902035517238584053190605786285923922079506248594145804074454421108 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/3.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke","qual_name":"4.xbar_smoke.20274255862623044348339688413886549511010248736666710574727818331862387187081","seed":20274255862623044348339688413886549511010248736666710574727818331862387187081,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/4.xbar_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/4.xbar_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3686063497 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke.3686063497' seed=20274255862623044348339688413886549511010248736666710574727818331862387187081 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=20274255862623044348339688413886549511010248736666710574727818331862387187081 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/4.xbar_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_zero_delays","qual_name":"4.xbar_smoke_zero_delays.36750490234477608221048294642433438236458362245975972279673339538042648802428","seed":36750490234477608221048294642433438236458362245975972279673339538042648802428,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/4.xbar_smoke_zero_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/4.xbar_smoke_zero_delays/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3591648380 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_zero_delays.3591648380' seed=36750490234477608221048294642433438236458362245975972279673339538042648802428 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=36750490234477608221048294642433438236458362245975972279673339538042648802428 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/4.xbar_smoke_zero_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_large_delays","qual_name":"4.xbar_smoke_large_delays.65994802394950022158643407269630902320953089435468783369853481737969291567134","seed":65994802394950022158643407269630902320953089435468783369853481737969291567134,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/4.xbar_smoke_large_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/4.xbar_smoke_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1782915102 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_large_delays.1782915102' seed=65994802394950022158643407269630902320953089435468783369853481737969291567134 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=65994802394950022158643407269630902320953089435468783369853481737969291567134 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/4.xbar_smoke_large_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_slow_rsp","qual_name":"4.xbar_smoke_slow_rsp.73154729333258100307615770363720879285186825304397412139378214333251046638956","seed":73154729333258100307615770363720879285186825304397412139378214333251046638956,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/4.xbar_smoke_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/4.xbar_smoke_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3132654956 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_slow_rsp.3132654956' seed=73154729333258100307615770363720879285186825304397412139378214333251046638956 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=73154729333258100307615770363720879285186825304397412139378214333251046638956 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/4.xbar_smoke_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random","qual_name":"4.xbar_random.104633835341200163995527330180923939211511397821109706137686899339882535428682","seed":104633835341200163995527330180923939211511397821109706137686899339882535428682,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/4.xbar_random/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/4.xbar_random/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1920311882 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random.1920311882' seed=104633835341200163995527330180923939211511397821109706137686899339882535428682 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=104633835341200163995527330180923939211511397821109706137686899339882535428682 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/4.xbar_random/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_zero_delays","qual_name":"4.xbar_random_zero_delays.67147789607705889768269063656541911011613537247807146889257174822609995615394","seed":67147789607705889768269063656541911011613537247807146889257174822609995615394,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/4.xbar_random_zero_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/4.xbar_random_zero_delays/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3733114018 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_zero_delays.3733114018' seed=67147789607705889768269063656541911011613537247807146889257174822609995615394 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=67147789607705889768269063656541911011613537247807146889257174822609995615394 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/4.xbar_random_zero_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_large_delays","qual_name":"4.xbar_random_large_delays.54327341755825190048410987513321565875719337782660826611915191404225964645367","seed":54327341755825190048410987513321565875719337782660826611915191404225964645367,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/4.xbar_random_large_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/4.xbar_random_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3714948087 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_large_delays.3714948087' seed=54327341755825190048410987513321565875719337782660826611915191404225964645367 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=54327341755825190048410987513321565875719337782660826611915191404225964645367 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/4.xbar_random_large_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_slow_rsp","qual_name":"4.xbar_random_slow_rsp.82915815247477270125168968347183632816368133667482176739696839336766480553857","seed":82915815247477270125168968347183632816368133667482176739696839336766480553857,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/4.xbar_random_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/4.xbar_random_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2495584129 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_slow_rsp.2495584129' seed=82915815247477270125168968347183632816368133667482176739696839336766480553857 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=82915815247477270125168968347183632816368133667482176739696839336766480553857 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/4.xbar_random_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device","qual_name":"4.xbar_access_same_device.112823829744387722595873141673402958142762893515124703882561174859746016015597","seed":112823829744387722595873141673402958142762893515124703882561174859746016015597,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/4.xbar_access_same_device/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/4.xbar_access_same_device/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1261483245 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device.1261483245' seed=112823829744387722595873141673402958142762893515124703882561174859746016015597 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=112823829744387722595873141673402958142762893515124703882561174859746016015597 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/4.xbar_access_same_device/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"4.xbar_access_same_device_slow_rsp.21160558982654943509098032980422307927804852278232589839723556687025132380740","seed":21160558982654943509098032980422307927804852278232589839723556687025132380740,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/4.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/4.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3940655684 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device_slow_rsp.3940655684' seed=21160558982654943509098032980422307927804852278232589839723556687025132380740 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=21160558982654943509098032980422307927804852278232589839723556687025132380740 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/4.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_same_source","qual_name":"4.xbar_same_source.53358298575179473216055657547456757775828970974175454344548307611535420468670","seed":53358298575179473216055657547456757775828970974175454344548307611535420468670,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/4.xbar_same_source/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/4.xbar_same_source/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3768364478 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_same_source.3768364478' seed=53358298575179473216055657547456757775828970974175454344548307611535420468670 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=53358298575179473216055657547456757775828970974175454344548307611535420468670 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/4.xbar_same_source/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_same_source_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_random","qual_name":"4.xbar_error_random.54386277613685857505466213664376877468448104413839993819817296384824790703435","seed":54386277613685857505466213664376877468448104413839993819817296384824790703435,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/4.xbar_error_random/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/4.xbar_error_random/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=259743051 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_error_random.259743051' seed=54386277613685857505466213664376877468448104413839993819817296384824790703435 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=54386277613685857505466213664376877468448104413839993819817296384824790703435 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/4.xbar_error_random/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_unmapped_addr","qual_name":"4.xbar_unmapped_addr.31729791328103623280541512037939906352457259582399396681080091982082212186364","seed":31729791328103623280541512037939906352457259582399396681080091982082212186364,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/4.xbar_unmapped_addr/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/4.xbar_unmapped_addr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=315967740 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_unmapped_addr.315967740' seed=31729791328103623280541512037939906352457259582399396681080091982082212186364 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=31729791328103623280541512037939906352457259582399396681080091982082212186364 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/4.xbar_unmapped_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_and_unmapped_addr","qual_name":"4.xbar_error_and_unmapped_addr.49167692158818122972825632574812630807496762654561858404522784230085825775964","seed":49167692158818122972825632574812630807496762654561858404522784230085825775964,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/4.xbar_error_and_unmapped_addr/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/4.xbar_error_and_unmapped_addr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3493448028 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_error_and_unmapped_addr.3493448028' seed=49167692158818122972825632574812630807496762654561858404522784230085825775964 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=49167692158818122972825632574812630807496762654561858404522784230085825775964 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/4.xbar_error_and_unmapped_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all","qual_name":"4.xbar_stress_all.22879628379494843829407107501062280667255680404393928319044692508651372221615","seed":22879628379494843829407107501062280667255680404393928319044692508651372221615,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/4.xbar_stress_all/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/4.xbar_stress_all/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4286387375 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all.4286387375' seed=22879628379494843829407107501062280667255680404393928319044692508651372221615 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=22879628379494843829407107501062280667255680404393928319044692508651372221615 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/4.xbar_stress_all/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_rand_reset","qual_name":"4.xbar_stress_all_with_rand_reset.84331380270337546561746344370545029344484888731003689251817434293633383259730","seed":84331380270337546561746344370545029344484888731003689251817434293633383259730,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/4.xbar_stress_all_with_rand_reset/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/4.xbar_stress_all_with_rand_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2013912658 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_rand_reset.2013912658' seed=84331380270337546561746344370545029344484888731003689251817434293633383259730 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=84331380270337546561746344370545029344484888731003689251817434293633383259730 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/4.xbar_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"4.xbar_stress_all_with_error.110136382238378950375418265135641926294713069382550820251513793077820503484748","seed":110136382238378950375418265135641926294713069382550820251513793077820503484748,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/4.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/4.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3298683212 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_error.3298683212' seed=110136382238378950375418265135641926294713069382550820251513793077820503484748 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=110136382238378950375418265135641926294713069382550820251513793077820503484748 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/4.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"4.xbar_stress_all_with_reset_error.56288018875579189815531971536560247664833338859027508616870336905676211326190","seed":56288018875579189815531971536560247664833338859027508616870336905676211326190,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/4.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/4.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3023801582 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_reset_error.3023801582' seed=56288018875579189815531971536560247664833338859027508616870336905676211326190 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=56288018875579189815531971536560247664833338859027508616870336905676211326190 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/4.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke","qual_name":"5.xbar_smoke.64162430725380609151830663017222998449375918329611883980714616863959296329110","seed":64162430725380609151830663017222998449375918329611883980714616863959296329110,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/5.xbar_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/5.xbar_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=352404886 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke.352404886' seed=64162430725380609151830663017222998449375918329611883980714616863959296329110 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=64162430725380609151830663017222998449375918329611883980714616863959296329110 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/5.xbar_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_zero_delays","qual_name":"5.xbar_smoke_zero_delays.82896369364960518283168732413012035817686416450086609005437973450712678926788","seed":82896369364960518283168732413012035817686416450086609005437973450712678926788,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/5.xbar_smoke_zero_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/5.xbar_smoke_zero_delays/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2271742404 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_zero_delays.2271742404' seed=82896369364960518283168732413012035817686416450086609005437973450712678926788 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=82896369364960518283168732413012035817686416450086609005437973450712678926788 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/5.xbar_smoke_zero_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_large_delays","qual_name":"5.xbar_smoke_large_delays.67395201456010664592487932964362958318555258833028828802175443521076424965095","seed":67395201456010664592487932964362958318555258833028828802175443521076424965095,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/5.xbar_smoke_large_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/5.xbar_smoke_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3981540327 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_large_delays.3981540327' seed=67395201456010664592487932964362958318555258833028828802175443521076424965095 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=67395201456010664592487932964362958318555258833028828802175443521076424965095 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/5.xbar_smoke_large_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_slow_rsp","qual_name":"5.xbar_smoke_slow_rsp.60296099475256312843634633519595050840327884123153926573069035787019416910293","seed":60296099475256312843634633519595050840327884123153926573069035787019416910293,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/5.xbar_smoke_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/5.xbar_smoke_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4093524437 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_slow_rsp.4093524437' seed=60296099475256312843634633519595050840327884123153926573069035787019416910293 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=60296099475256312843634633519595050840327884123153926573069035787019416910293 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/5.xbar_smoke_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random","qual_name":"5.xbar_random.75899883748375949939890846909723860340159390574377140275004370751037589345870","seed":75899883748375949939890846909723860340159390574377140275004370751037589345870,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/5.xbar_random/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/5.xbar_random/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2936985166 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random.2936985166' seed=75899883748375949939890846909723860340159390574377140275004370751037589345870 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=75899883748375949939890846909723860340159390574377140275004370751037589345870 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/5.xbar_random/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_zero_delays","qual_name":"5.xbar_random_zero_delays.44013096047495486889356048794646820102807508006224433733897915817139072783886","seed":44013096047495486889356048794646820102807508006224433733897915817139072783886,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/5.xbar_random_zero_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/5.xbar_random_zero_delays/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3156858382 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_zero_delays.3156858382' seed=44013096047495486889356048794646820102807508006224433733897915817139072783886 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=44013096047495486889356048794646820102807508006224433733897915817139072783886 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/5.xbar_random_zero_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_large_delays","qual_name":"5.xbar_random_large_delays.65623613808869752543700309752488594630904036000595351384615427295247382174455","seed":65623613808869752543700309752488594630904036000595351384615427295247382174455,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/5.xbar_random_large_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/5.xbar_random_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2192136951 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_large_delays.2192136951' seed=65623613808869752543700309752488594630904036000595351384615427295247382174455 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=65623613808869752543700309752488594630904036000595351384615427295247382174455 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/5.xbar_random_large_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_slow_rsp","qual_name":"5.xbar_random_slow_rsp.33774305708461427232016094266522630376295604191237985293615876175514481961633","seed":33774305708461427232016094266522630376295604191237985293615876175514481961633,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/5.xbar_random_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/5.xbar_random_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3975391905 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_slow_rsp.3975391905' seed=33774305708461427232016094266522630376295604191237985293615876175514481961633 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=33774305708461427232016094266522630376295604191237985293615876175514481961633 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/5.xbar_random_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device","qual_name":"5.xbar_access_same_device.86968074780769147584064028764363361772848957690268151735217189058365704159316","seed":86968074780769147584064028764363361772848957690268151735217189058365704159316,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/5.xbar_access_same_device/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/5.xbar_access_same_device/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1640022100 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device.1640022100' seed=86968074780769147584064028764363361772848957690268151735217189058365704159316 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=86968074780769147584064028764363361772848957690268151735217189058365704159316 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/5.xbar_access_same_device/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"5.xbar_access_same_device_slow_rsp.39472231702375063810948823400453264839881584042385646454455777684128466208490","seed":39472231702375063810948823400453264839881584042385646454455777684128466208490,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/5.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/5.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=824968938 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device_slow_rsp.824968938' seed=39472231702375063810948823400453264839881584042385646454455777684128466208490 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=39472231702375063810948823400453264839881584042385646454455777684128466208490 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/5.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_same_source","qual_name":"5.xbar_same_source.68015440046671767626173424310769986785421163998535332636512924855069751946351","seed":68015440046671767626173424310769986785421163998535332636512924855069751946351,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/5.xbar_same_source/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/5.xbar_same_source/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=784903279 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_same_source.784903279' seed=68015440046671767626173424310769986785421163998535332636512924855069751946351 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=68015440046671767626173424310769986785421163998535332636512924855069751946351 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/5.xbar_same_source/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_same_source_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_random","qual_name":"5.xbar_error_random.14265449571977807112350291519691117729437908533902246324957631443630117149906","seed":14265449571977807112350291519691117729437908533902246324957631443630117149906,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/5.xbar_error_random/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/5.xbar_error_random/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3190086866 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_error_random.3190086866' seed=14265449571977807112350291519691117729437908533902246324957631443630117149906 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=14265449571977807112350291519691117729437908533902246324957631443630117149906 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/5.xbar_error_random/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_unmapped_addr","qual_name":"5.xbar_unmapped_addr.7617047354671987828608462502493205338803261253461524938939127201348924178134","seed":7617047354671987828608462502493205338803261253461524938939127201348924178134,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/5.xbar_unmapped_addr/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/5.xbar_unmapped_addr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=933199574 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_unmapped_addr.933199574' seed=7617047354671987828608462502493205338803261253461524938939127201348924178134 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=7617047354671987828608462502493205338803261253461524938939127201348924178134 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/5.xbar_unmapped_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_and_unmapped_addr","qual_name":"5.xbar_error_and_unmapped_addr.101367090180790394850257478702053033190678531448054536802089224226424162245863","seed":101367090180790394850257478702053033190678531448054536802089224226424162245863,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/5.xbar_error_and_unmapped_addr/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/5.xbar_error_and_unmapped_addr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1417043175 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_error_and_unmapped_addr.1417043175' seed=101367090180790394850257478702053033190678531448054536802089224226424162245863 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=101367090180790394850257478702053033190678531448054536802089224226424162245863 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/5.xbar_error_and_unmapped_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all","qual_name":"5.xbar_stress_all.37159213012243400936759789322734654776604388866433897899948295933936075798959","seed":37159213012243400936759789322734654776604388866433897899948295933936075798959,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/5.xbar_stress_all/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/5.xbar_stress_all/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2214066607 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all.2214066607' seed=37159213012243400936759789322734654776604388866433897899948295933936075798959 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=37159213012243400936759789322734654776604388866433897899948295933936075798959 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/5.xbar_stress_all/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_rand_reset","qual_name":"5.xbar_stress_all_with_rand_reset.23754406839160766104585021719789681215589802417459261030949293896881569817804","seed":23754406839160766104585021719789681215589802417459261030949293896881569817804,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/5.xbar_stress_all_with_rand_reset/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/5.xbar_stress_all_with_rand_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=335832268 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_rand_reset.335832268' seed=23754406839160766104585021719789681215589802417459261030949293896881569817804 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=23754406839160766104585021719789681215589802417459261030949293896881569817804 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/5.xbar_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"5.xbar_stress_all_with_error.92699230772146853687580346140578707257566077213898667493098686213118983189970","seed":92699230772146853687580346140578707257566077213898667493098686213118983189970,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/5.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/5.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2258417106 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_error.2258417106' seed=92699230772146853687580346140578707257566077213898667493098686213118983189970 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=92699230772146853687580346140578707257566077213898667493098686213118983189970 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/5.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"5.xbar_stress_all_with_reset_error.110143763326300898285675223464246518497262800424468285313381816704508484488462","seed":110143763326300898285675223464246518497262800424468285313381816704508484488462,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/5.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/5.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=287411470 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_reset_error.287411470' seed=110143763326300898285675223464246518497262800424468285313381816704508484488462 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=110143763326300898285675223464246518497262800424468285313381816704508484488462 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/5.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke","qual_name":"6.xbar_smoke.19761594329578728175558938846283872043945966753649492174374893010111381022476","seed":19761594329578728175558938846283872043945966753649492174374893010111381022476,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/6.xbar_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/6.xbar_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3062540044 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke.3062540044' seed=19761594329578728175558938846283872043945966753649492174374893010111381022476 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=19761594329578728175558938846283872043945966753649492174374893010111381022476 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/6.xbar_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_zero_delays","qual_name":"6.xbar_smoke_zero_delays.69879858155910173195937336977492577036442373080242822580648438767491198350317","seed":69879858155910173195937336977492577036442373080242822580648438767491198350317,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/6.xbar_smoke_zero_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/6.xbar_smoke_zero_delays/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3246257133 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_zero_delays.3246257133' seed=69879858155910173195937336977492577036442373080242822580648438767491198350317 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=69879858155910173195937336977492577036442373080242822580648438767491198350317 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/6.xbar_smoke_zero_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_large_delays","qual_name":"6.xbar_smoke_large_delays.33092815853164203578845593367479949025925406512570181032917402167736615496006","seed":33092815853164203578845593367479949025925406512570181032917402167736615496006,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/6.xbar_smoke_large_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/6.xbar_smoke_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3410684230 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_large_delays.3410684230' seed=33092815853164203578845593367479949025925406512570181032917402167736615496006 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=33092815853164203578845593367479949025925406512570181032917402167736615496006 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/6.xbar_smoke_large_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_slow_rsp","qual_name":"6.xbar_smoke_slow_rsp.51857999355797242893760347591598166584298978957505995545756756320480351900828","seed":51857999355797242893760347591598166584298978957505995545756756320480351900828,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/6.xbar_smoke_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/6.xbar_smoke_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=816469148 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_slow_rsp.816469148' seed=51857999355797242893760347591598166584298978957505995545756756320480351900828 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=51857999355797242893760347591598166584298978957505995545756756320480351900828 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/6.xbar_smoke_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random","qual_name":"6.xbar_random.18644734959173282852243499763681862006365921523040756885205302947395186077060","seed":18644734959173282852243499763681862006365921523040756885205302947395186077060,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/6.xbar_random/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/6.xbar_random/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=568733060 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random.568733060' seed=18644734959173282852243499763681862006365921523040756885205302947395186077060 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=18644734959173282852243499763681862006365921523040756885205302947395186077060 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/6.xbar_random/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_zero_delays","qual_name":"6.xbar_random_zero_delays.8545413017155432916565960652026823590973773029802390373312932680948863889058","seed":8545413017155432916565960652026823590973773029802390373312932680948863889058,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/6.xbar_random_zero_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/6.xbar_random_zero_delays/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1557032610 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_zero_delays.1557032610' seed=8545413017155432916565960652026823590973773029802390373312932680948863889058 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=8545413017155432916565960652026823590973773029802390373312932680948863889058 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/6.xbar_random_zero_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_large_delays","qual_name":"6.xbar_random_large_delays.36626611339696220014338575636952849976604551767181344244755161151927918925225","seed":36626611339696220014338575636952849976604551767181344244755161151927918925225,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/6.xbar_random_large_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/6.xbar_random_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=384177577 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_large_delays.384177577' seed=36626611339696220014338575636952849976604551767181344244755161151927918925225 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=36626611339696220014338575636952849976604551767181344244755161151927918925225 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/6.xbar_random_large_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_slow_rsp","qual_name":"6.xbar_random_slow_rsp.15707572726934551216989184727429726038776096863098344427321473378387321061916","seed":15707572726934551216989184727429726038776096863098344427321473378387321061916,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/6.xbar_random_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/6.xbar_random_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3185738268 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_slow_rsp.3185738268' seed=15707572726934551216989184727429726038776096863098344427321473378387321061916 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=15707572726934551216989184727429726038776096863098344427321473378387321061916 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/6.xbar_random_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device","qual_name":"6.xbar_access_same_device.21402567085326715275862038543215767850825319612478113045394206562431192976254","seed":21402567085326715275862038543215767850825319612478113045394206562431192976254,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/6.xbar_access_same_device/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/6.xbar_access_same_device/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3527068542 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device.3527068542' seed=21402567085326715275862038543215767850825319612478113045394206562431192976254 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=21402567085326715275862038543215767850825319612478113045394206562431192976254 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/6.xbar_access_same_device/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"6.xbar_access_same_device_slow_rsp.30906322026932429884755095022426595090253921593158608059796841766999232105598","seed":30906322026932429884755095022426595090253921593158608059796841766999232105598,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/6.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/6.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3601878142 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device_slow_rsp.3601878142' seed=30906322026932429884755095022426595090253921593158608059796841766999232105598 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=30906322026932429884755095022426595090253921593158608059796841766999232105598 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/6.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_same_source","qual_name":"6.xbar_same_source.89137440428438560119750515508977854712885417389252068162334433195679726965744","seed":89137440428438560119750515508977854712885417389252068162334433195679726965744,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/6.xbar_same_source/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/6.xbar_same_source/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2585007088 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_same_source.2585007088' seed=89137440428438560119750515508977854712885417389252068162334433195679726965744 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=89137440428438560119750515508977854712885417389252068162334433195679726965744 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/6.xbar_same_source/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_same_source_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_random","qual_name":"6.xbar_error_random.102975732307494135797550507660454474220863102281231165912619967623161471230154","seed":102975732307494135797550507660454474220863102281231165912619967623161471230154,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/6.xbar_error_random/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/6.xbar_error_random/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3048923338 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_error_random.3048923338' seed=102975732307494135797550507660454474220863102281231165912619967623161471230154 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=102975732307494135797550507660454474220863102281231165912619967623161471230154 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/6.xbar_error_random/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_unmapped_addr","qual_name":"6.xbar_unmapped_addr.39527785229345858058097422816505398847888451461819831793902731445362764297927","seed":39527785229345858058097422816505398847888451461819831793902731445362764297927,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/6.xbar_unmapped_addr/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/6.xbar_unmapped_addr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=455358151 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_unmapped_addr.455358151' seed=39527785229345858058097422816505398847888451461819831793902731445362764297927 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=39527785229345858058097422816505398847888451461819831793902731445362764297927 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/6.xbar_unmapped_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_and_unmapped_addr","qual_name":"6.xbar_error_and_unmapped_addr.2496309572526498062733020845362007759968421700287187858656419462133287685865","seed":2496309572526498062733020845362007759968421700287187858656419462133287685865,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/6.xbar_error_and_unmapped_addr/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/6.xbar_error_and_unmapped_addr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1121390313 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_error_and_unmapped_addr.1121390313' seed=2496309572526498062733020845362007759968421700287187858656419462133287685865 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=2496309572526498062733020845362007759968421700287187858656419462133287685865 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/6.xbar_error_and_unmapped_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all","qual_name":"6.xbar_stress_all.103349046750901134021181392753485146796198115209833580783557264819541416971282","seed":103349046750901134021181392753485146796198115209833580783557264819541416971282,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/6.xbar_stress_all/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/6.xbar_stress_all/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1404144658 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all.1404144658' seed=103349046750901134021181392753485146796198115209833580783557264819541416971282 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=103349046750901134021181392753485146796198115209833580783557264819541416971282 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/6.xbar_stress_all/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_rand_reset","qual_name":"6.xbar_stress_all_with_rand_reset.64430237621210080733169604363977840497030424303014903174307615878680930918609","seed":64430237621210080733169604363977840497030424303014903174307615878680930918609,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/6.xbar_stress_all_with_rand_reset/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/6.xbar_stress_all_with_rand_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=374055121 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_rand_reset.374055121' seed=64430237621210080733169604363977840497030424303014903174307615878680930918609 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=64430237621210080733169604363977840497030424303014903174307615878680930918609 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/6.xbar_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"6.xbar_stress_all_with_error.73720392253820702763402495227599261955309617324295466402119295927014902986402","seed":73720392253820702763402495227599261955309617324295466402119295927014902986402,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/6.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/6.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=729282210 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_error.729282210' seed=73720392253820702763402495227599261955309617324295466402119295927014902986402 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=73720392253820702763402495227599261955309617324295466402119295927014902986402 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/6.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"6.xbar_stress_all_with_reset_error.61169639866436313941139265489991156097827820786418790897076508729147865029611","seed":61169639866436313941139265489991156097827820786418790897076508729147865029611,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/6.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/6.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3618757611 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_reset_error.3618757611' seed=61169639866436313941139265489991156097827820786418790897076508729147865029611 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=61169639866436313941139265489991156097827820786418790897076508729147865029611 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/6.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke","qual_name":"7.xbar_smoke.3152420750708045016684796140340068999920190173145034154610013123732737171223","seed":3152420750708045016684796140340068999920190173145034154610013123732737171223,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/7.xbar_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/7.xbar_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4134870807 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke.4134870807' seed=3152420750708045016684796140340068999920190173145034154610013123732737171223 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=3152420750708045016684796140340068999920190173145034154610013123732737171223 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/7.xbar_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_zero_delays","qual_name":"7.xbar_smoke_zero_delays.68742511185926377753529052117629257122206579107091878489176011351064683366395","seed":68742511185926377753529052117629257122206579107091878489176011351064683366395,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/7.xbar_smoke_zero_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/7.xbar_smoke_zero_delays/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1822836731 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_zero_delays.1822836731' seed=68742511185926377753529052117629257122206579107091878489176011351064683366395 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=68742511185926377753529052117629257122206579107091878489176011351064683366395 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/7.xbar_smoke_zero_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_large_delays","qual_name":"7.xbar_smoke_large_delays.104367483324873405289611428590576281509165869571478743783003272888089484733059","seed":104367483324873405289611428590576281509165869571478743783003272888089484733059,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/7.xbar_smoke_large_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/7.xbar_smoke_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2646092419 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_large_delays.2646092419' seed=104367483324873405289611428590576281509165869571478743783003272888089484733059 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=104367483324873405289611428590576281509165869571478743783003272888089484733059 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/7.xbar_smoke_large_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_slow_rsp","qual_name":"7.xbar_smoke_slow_rsp.19644341970857156725311113582439798263272639290592997758580374031034614337452","seed":19644341970857156725311113582439798263272639290592997758580374031034614337452,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/7.xbar_smoke_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/7.xbar_smoke_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4202221484 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_slow_rsp.4202221484' seed=19644341970857156725311113582439798263272639290592997758580374031034614337452 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=19644341970857156725311113582439798263272639290592997758580374031034614337452 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/7.xbar_smoke_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random","qual_name":"7.xbar_random.49606006965599539671966780165224832551338255721865194284007368377531830691908","seed":49606006965599539671966780165224832551338255721865194284007368377531830691908,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/7.xbar_random/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/7.xbar_random/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2403133508 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random.2403133508' seed=49606006965599539671966780165224832551338255721865194284007368377531830691908 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=49606006965599539671966780165224832551338255721865194284007368377531830691908 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/7.xbar_random/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_zero_delays","qual_name":"7.xbar_random_zero_delays.113682898461428894251336127410662347373534575511217108076334080034576684591958","seed":113682898461428894251336127410662347373534575511217108076334080034576684591958,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/7.xbar_random_zero_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/7.xbar_random_zero_delays/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3506482006 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_zero_delays.3506482006' seed=113682898461428894251336127410662347373534575511217108076334080034576684591958 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=113682898461428894251336127410662347373534575511217108076334080034576684591958 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/7.xbar_random_zero_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_large_delays","qual_name":"7.xbar_random_large_delays.44665440970636025075729105992584036577286812100543996052251733141272897439243","seed":44665440970636025075729105992584036577286812100543996052251733141272897439243,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/7.xbar_random_large_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/7.xbar_random_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1220986379 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_large_delays.1220986379' seed=44665440970636025075729105992584036577286812100543996052251733141272897439243 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=44665440970636025075729105992584036577286812100543996052251733141272897439243 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/7.xbar_random_large_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_slow_rsp","qual_name":"7.xbar_random_slow_rsp.19341751010749781972633326904145048071265956692208977791967931940857491091590","seed":19341751010749781972633326904145048071265956692208977791967931940857491091590,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/7.xbar_random_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/7.xbar_random_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3465146502 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_slow_rsp.3465146502' seed=19341751010749781972633326904145048071265956692208977791967931940857491091590 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=19341751010749781972633326904145048071265956692208977791967931940857491091590 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/7.xbar_random_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device","qual_name":"7.xbar_access_same_device.48763913656027798232778546891741719853561693202315917473374672695686659263187","seed":48763913656027798232778546891741719853561693202315917473374672695686659263187,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/7.xbar_access_same_device/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/7.xbar_access_same_device/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1140542163 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device.1140542163' seed=48763913656027798232778546891741719853561693202315917473374672695686659263187 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=48763913656027798232778546891741719853561693202315917473374672695686659263187 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/7.xbar_access_same_device/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"7.xbar_access_same_device_slow_rsp.44291486909195484438107350625736971495814223772359941627517975899521971015267","seed":44291486909195484438107350625736971495814223772359941627517975899521971015267,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/7.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/7.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1264733795 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device_slow_rsp.1264733795' seed=44291486909195484438107350625736971495814223772359941627517975899521971015267 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=44291486909195484438107350625736971495814223772359941627517975899521971015267 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/7.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_same_source","qual_name":"7.xbar_same_source.25336909922934649723780207043758188167338639968822863977692492072827806662136","seed":25336909922934649723780207043758188167338639968822863977692492072827806662136,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/7.xbar_same_source/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/7.xbar_same_source/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=49921528 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_same_source.49921528' seed=25336909922934649723780207043758188167338639968822863977692492072827806662136 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=25336909922934649723780207043758188167338639968822863977692492072827806662136 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/7.xbar_same_source/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_same_source_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_random","qual_name":"7.xbar_error_random.101172259790134872449956026049244948223180136894024779097240707137048610680187","seed":101172259790134872449956026049244948223180136894024779097240707137048610680187,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/7.xbar_error_random/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/7.xbar_error_random/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2706713979 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_error_random.2706713979' seed=101172259790134872449956026049244948223180136894024779097240707137048610680187 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=101172259790134872449956026049244948223180136894024779097240707137048610680187 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/7.xbar_error_random/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_unmapped_addr","qual_name":"7.xbar_unmapped_addr.23734498274876191220410219040855876157545856905368442277749659828052290916125","seed":23734498274876191220410219040855876157545856905368442277749659828052290916125,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/7.xbar_unmapped_addr/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/7.xbar_unmapped_addr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2052542237 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_unmapped_addr.2052542237' seed=23734498274876191220410219040855876157545856905368442277749659828052290916125 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=23734498274876191220410219040855876157545856905368442277749659828052290916125 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/7.xbar_unmapped_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_and_unmapped_addr","qual_name":"7.xbar_error_and_unmapped_addr.14441149059051642720185105944491157800196154865515183438557968277852331669208","seed":14441149059051642720185105944491157800196154865515183438557968277852331669208,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/7.xbar_error_and_unmapped_addr/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/7.xbar_error_and_unmapped_addr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3245307608 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_error_and_unmapped_addr.3245307608' seed=14441149059051642720185105944491157800196154865515183438557968277852331669208 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=14441149059051642720185105944491157800196154865515183438557968277852331669208 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/7.xbar_error_and_unmapped_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all","qual_name":"7.xbar_stress_all.48468696770046047914183097137784403594250934173692174433349298008707136149409","seed":48468696770046047914183097137784403594250934173692174433349298008707136149409,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/7.xbar_stress_all/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/7.xbar_stress_all/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2798049185 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all.2798049185' seed=48468696770046047914183097137784403594250934173692174433349298008707136149409 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=48468696770046047914183097137784403594250934173692174433349298008707136149409 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/7.xbar_stress_all/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_rand_reset","qual_name":"7.xbar_stress_all_with_rand_reset.73766743442532923491168530186189666308207310809401375148425677849811679685197","seed":73766743442532923491168530186189666308207310809401375148425677849811679685197,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/7.xbar_stress_all_with_rand_reset/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/7.xbar_stress_all_with_rand_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=213887565 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_rand_reset.213887565' seed=73766743442532923491168530186189666308207310809401375148425677849811679685197 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=73766743442532923491168530186189666308207310809401375148425677849811679685197 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/7.xbar_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"7.xbar_stress_all_with_error.7734141662637602690239876891934696973183344196889625883573091505634634821501","seed":7734141662637602690239876891934696973183344196889625883573091505634634821501,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/7.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/7.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=353300349 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_error.353300349' seed=7734141662637602690239876891934696973183344196889625883573091505634634821501 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=7734141662637602690239876891934696973183344196889625883573091505634634821501 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/7.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"7.xbar_stress_all_with_reset_error.55714745464176240125474985165816155294435275122208971632678724916251367584440","seed":55714745464176240125474985165816155294435275122208971632678724916251367584440,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/7.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/7.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4286853816 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_reset_error.4286853816' seed=55714745464176240125474985165816155294435275122208971632678724916251367584440 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=55714745464176240125474985165816155294435275122208971632678724916251367584440 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/7.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke","qual_name":"8.xbar_smoke.73642513450592214555759071787583055246691899733398403461066479002819028222045","seed":73642513450592214555759071787583055246691899733398403461066479002819028222045,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/8.xbar_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/8.xbar_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=461275229 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke.461275229' seed=73642513450592214555759071787583055246691899733398403461066479002819028222045 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=73642513450592214555759071787583055246691899733398403461066479002819028222045 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/8.xbar_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_zero_delays","qual_name":"8.xbar_smoke_zero_delays.88025194215168263418752447279640425081710736304198479865000866186083307266232","seed":88025194215168263418752447279640425081710736304198479865000866186083307266232,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/8.xbar_smoke_zero_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/8.xbar_smoke_zero_delays/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=915054776 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_zero_delays.915054776' seed=88025194215168263418752447279640425081710736304198479865000866186083307266232 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=88025194215168263418752447279640425081710736304198479865000866186083307266232 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/8.xbar_smoke_zero_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_large_delays","qual_name":"8.xbar_smoke_large_delays.10188656413762722108193316741212202543371471029862661339427223225698343937530","seed":10188656413762722108193316741212202543371471029862661339427223225698343937530,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/8.xbar_smoke_large_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/8.xbar_smoke_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=758343162 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_large_delays.758343162' seed=10188656413762722108193316741212202543371471029862661339427223225698343937530 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=10188656413762722108193316741212202543371471029862661339427223225698343937530 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/8.xbar_smoke_large_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_slow_rsp","qual_name":"8.xbar_smoke_slow_rsp.93267869223717901940042554850632099623916463982531598458809830567109040554926","seed":93267869223717901940042554850632099623916463982531598458809830567109040554926,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/8.xbar_smoke_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/8.xbar_smoke_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2881504174 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_slow_rsp.2881504174' seed=93267869223717901940042554850632099623916463982531598458809830567109040554926 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=93267869223717901940042554850632099623916463982531598458809830567109040554926 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/8.xbar_smoke_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random","qual_name":"8.xbar_random.108225397452823303978258977851623612174711782091002381318738413865068137120281","seed":108225397452823303978258977851623612174711782091002381318738413865068137120281,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/8.xbar_random/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/8.xbar_random/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2034860569 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random.2034860569' seed=108225397452823303978258977851623612174711782091002381318738413865068137120281 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=108225397452823303978258977851623612174711782091002381318738413865068137120281 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/8.xbar_random/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_zero_delays","qual_name":"8.xbar_random_zero_delays.6991402351679008423668102237581709239752793678722279573695818303279689446813","seed":6991402351679008423668102237581709239752793678722279573695818303279689446813,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/8.xbar_random_zero_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/8.xbar_random_zero_delays/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1409889693 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_zero_delays.1409889693' seed=6991402351679008423668102237581709239752793678722279573695818303279689446813 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=6991402351679008423668102237581709239752793678722279573695818303279689446813 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/8.xbar_random_zero_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_large_delays","qual_name":"8.xbar_random_large_delays.54491753479183104995052696621648996364226785481942478631496186390369700318199","seed":54491753479183104995052696621648996364226785481942478631496186390369700318199,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/8.xbar_random_large_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/8.xbar_random_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1537903607 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_large_delays.1537903607' seed=54491753479183104995052696621648996364226785481942478631496186390369700318199 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=54491753479183104995052696621648996364226785481942478631496186390369700318199 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/8.xbar_random_large_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_slow_rsp","qual_name":"8.xbar_random_slow_rsp.86417983631971454419406013090795100812257358337674990927939393239536571528023","seed":86417983631971454419406013090795100812257358337674990927939393239536571528023,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/8.xbar_random_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/8.xbar_random_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=942158679 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_slow_rsp.942158679' seed=86417983631971454419406013090795100812257358337674990927939393239536571528023 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=86417983631971454419406013090795100812257358337674990927939393239536571528023 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/8.xbar_random_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device","qual_name":"8.xbar_access_same_device.13843024830349094092634021862653614793180255060291402983974577465559946721258","seed":13843024830349094092634021862653614793180255060291402983974577465559946721258,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/8.xbar_access_same_device/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/8.xbar_access_same_device/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1132296170 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device.1132296170' seed=13843024830349094092634021862653614793180255060291402983974577465559946721258 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=13843024830349094092634021862653614793180255060291402983974577465559946721258 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/8.xbar_access_same_device/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"8.xbar_access_same_device_slow_rsp.86166036883711561565690720622792888747617021116034358365616073160701429854302","seed":86166036883711561565690720622792888747617021116034358365616073160701429854302,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/8.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/8.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1560195166 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device_slow_rsp.1560195166' seed=86166036883711561565690720622792888747617021116034358365616073160701429854302 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=86166036883711561565690720622792888747617021116034358365616073160701429854302 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/8.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_same_source","qual_name":"8.xbar_same_source.106423877991385905351404226929391292960845447307499325976135568946523395154535","seed":106423877991385905351404226929391292960845447307499325976135568946523395154535,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/8.xbar_same_source/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/8.xbar_same_source/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2749719143 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_same_source.2749719143' seed=106423877991385905351404226929391292960845447307499325976135568946523395154535 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=106423877991385905351404226929391292960845447307499325976135568946523395154535 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/8.xbar_same_source/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_same_source_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_random","qual_name":"8.xbar_error_random.30768114870320051083060608300062326516920559823106500878689769375682871207593","seed":30768114870320051083060608300062326516920559823106500878689769375682871207593,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/8.xbar_error_random/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/8.xbar_error_random/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3309348521 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_error_random.3309348521' seed=30768114870320051083060608300062326516920559823106500878689769375682871207593 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=30768114870320051083060608300062326516920559823106500878689769375682871207593 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/8.xbar_error_random/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_unmapped_addr","qual_name":"8.xbar_unmapped_addr.86364983571845276141273332195239354313155560497857119667696580404014451473489","seed":86364983571845276141273332195239354313155560497857119667696580404014451473489,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/8.xbar_unmapped_addr/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/8.xbar_unmapped_addr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=626474065 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_unmapped_addr.626474065' seed=86364983571845276141273332195239354313155560497857119667696580404014451473489 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=86364983571845276141273332195239354313155560497857119667696580404014451473489 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/8.xbar_unmapped_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_and_unmapped_addr","qual_name":"8.xbar_error_and_unmapped_addr.83994466452565119714539628048400820972438883704655512109418711906649523161405","seed":83994466452565119714539628048400820972438883704655512109418711906649523161405,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/8.xbar_error_and_unmapped_addr/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/8.xbar_error_and_unmapped_addr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=561580349 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_error_and_unmapped_addr.561580349' seed=83994466452565119714539628048400820972438883704655512109418711906649523161405 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=83994466452565119714539628048400820972438883704655512109418711906649523161405 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/8.xbar_error_and_unmapped_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all","qual_name":"8.xbar_stress_all.29506629870202851570769462429781248328080737147858594536742312926939834572005","seed":29506629870202851570769462429781248328080737147858594536742312926939834572005,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/8.xbar_stress_all/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/8.xbar_stress_all/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4267007205 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all.4267007205' seed=29506629870202851570769462429781248328080737147858594536742312926939834572005 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=29506629870202851570769462429781248328080737147858594536742312926939834572005 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/8.xbar_stress_all/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_rand_reset","qual_name":"8.xbar_stress_all_with_rand_reset.46734844329143845163664675505042929743634231741947762189736620437134037270149","seed":46734844329143845163664675505042929743634231741947762189736620437134037270149,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/8.xbar_stress_all_with_rand_reset/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/8.xbar_stress_all_with_rand_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2439036549 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_rand_reset.2439036549' seed=46734844329143845163664675505042929743634231741947762189736620437134037270149 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=46734844329143845163664675505042929743634231741947762189736620437134037270149 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/8.xbar_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"8.xbar_stress_all_with_error.90424419026352892867283075122916316307417558514168839155434187533819875379794","seed":90424419026352892867283075122916316307417558514168839155434187533819875379794,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/8.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/8.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4134750802 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_error.4134750802' seed=90424419026352892867283075122916316307417558514168839155434187533819875379794 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=90424419026352892867283075122916316307417558514168839155434187533819875379794 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/8.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"8.xbar_stress_all_with_reset_error.93003624317127965392469026664687011661080983833791713449900858427158380135676","seed":93003624317127965392469026664687011661080983833791713449900858427158380135676,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/8.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/8.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1140573436 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_reset_error.1140573436' seed=93003624317127965392469026664687011661080983833791713449900858427158380135676 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=93003624317127965392469026664687011661080983833791713449900858427158380135676 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/8.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke","qual_name":"9.xbar_smoke.56524764829182348289855488225632844512473604824684867271762015957276689390910","seed":56524764829182348289855488225632844512473604824684867271762015957276689390910,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/9.xbar_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/9.xbar_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=246373694 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke.246373694' seed=56524764829182348289855488225632844512473604824684867271762015957276689390910 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=56524764829182348289855488225632844512473604824684867271762015957276689390910 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/9.xbar_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_zero_delays","qual_name":"9.xbar_smoke_zero_delays.75672122427354642262754857125940777311797077188619155240755566775128039809896","seed":75672122427354642262754857125940777311797077188619155240755566775128039809896,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/9.xbar_smoke_zero_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/9.xbar_smoke_zero_delays/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3007505256 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_zero_delays.3007505256' seed=75672122427354642262754857125940777311797077188619155240755566775128039809896 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=75672122427354642262754857125940777311797077188619155240755566775128039809896 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/9.xbar_smoke_zero_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_large_delays","qual_name":"9.xbar_smoke_large_delays.100969387297523157681349132287758626247865684146343584512049310889334829081120","seed":100969387297523157681349132287758626247865684146343584512049310889334829081120,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/9.xbar_smoke_large_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/9.xbar_smoke_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3642090016 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_large_delays.3642090016' seed=100969387297523157681349132287758626247865684146343584512049310889334829081120 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=100969387297523157681349132287758626247865684146343584512049310889334829081120 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/9.xbar_smoke_large_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_slow_rsp","qual_name":"9.xbar_smoke_slow_rsp.11800317375796389335161017839096755834957431993289610093641403877528911917592","seed":11800317375796389335161017839096755834957431993289610093641403877528911917592,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/9.xbar_smoke_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/9.xbar_smoke_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3474108952 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_slow_rsp.3474108952' seed=11800317375796389335161017839096755834957431993289610093641403877528911917592 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=11800317375796389335161017839096755834957431993289610093641403877528911917592 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/9.xbar_smoke_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random","qual_name":"9.xbar_random.76022155708980789207975187814915576011469252905817377951127406486871493879919","seed":76022155708980789207975187814915576011469252905817377951127406486871493879919,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/9.xbar_random/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/9.xbar_random/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3174869103 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random.3174869103' seed=76022155708980789207975187814915576011469252905817377951127406486871493879919 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=76022155708980789207975187814915576011469252905817377951127406486871493879919 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/9.xbar_random/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_zero_delays","qual_name":"9.xbar_random_zero_delays.30654429663193216370991546663234666332678263918087799320030224059518263025284","seed":30654429663193216370991546663234666332678263918087799320030224059518263025284,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/9.xbar_random_zero_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/9.xbar_random_zero_delays/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2538921604 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_zero_delays.2538921604' seed=30654429663193216370991546663234666332678263918087799320030224059518263025284 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=30654429663193216370991546663234666332678263918087799320030224059518263025284 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/9.xbar_random_zero_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_large_delays","qual_name":"9.xbar_random_large_delays.12400061140107200720256223368019732216590589083551383550245431526735401257998","seed":12400061140107200720256223368019732216590589083551383550245431526735401257998,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/9.xbar_random_large_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/9.xbar_random_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=69274638 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_large_delays.69274638' seed=12400061140107200720256223368019732216590589083551383550245431526735401257998 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=12400061140107200720256223368019732216590589083551383550245431526735401257998 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/9.xbar_random_large_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_slow_rsp","qual_name":"9.xbar_random_slow_rsp.85842564535392186066182178262352177752783213743637532391492781287897751076451","seed":85842564535392186066182178262352177752783213743637532391492781287897751076451,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/9.xbar_random_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/9.xbar_random_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1934868067 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_slow_rsp.1934868067' seed=85842564535392186066182178262352177752783213743637532391492781287897751076451 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=85842564535392186066182178262352177752783213743637532391492781287897751076451 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/9.xbar_random_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device","qual_name":"9.xbar_access_same_device.34162032508384448685421583292112735595558186264932133297934606588062900969420","seed":34162032508384448685421583292112735595558186264932133297934606588062900969420,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/9.xbar_access_same_device/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/9.xbar_access_same_device/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1638686668 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device.1638686668' seed=34162032508384448685421583292112735595558186264932133297934606588062900969420 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=34162032508384448685421583292112735595558186264932133297934606588062900969420 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/9.xbar_access_same_device/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"9.xbar_access_same_device_slow_rsp.56138212566643219519685307094279618018601769812802079270012557943026938607919","seed":56138212566643219519685307094279618018601769812802079270012557943026938607919,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/9.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/9.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=973404463 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device_slow_rsp.973404463' seed=56138212566643219519685307094279618018601769812802079270012557943026938607919 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=56138212566643219519685307094279618018601769812802079270012557943026938607919 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/9.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_same_source","qual_name":"9.xbar_same_source.84150914130346112773376021721659419707774820617821049610057582198752565150764","seed":84150914130346112773376021721659419707774820617821049610057582198752565150764,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/9.xbar_same_source/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/9.xbar_same_source/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=584467500 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_same_source.584467500' seed=84150914130346112773376021721659419707774820617821049610057582198752565150764 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=84150914130346112773376021721659419707774820617821049610057582198752565150764 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/9.xbar_same_source/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_same_source_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_random","qual_name":"9.xbar_error_random.26927324371801091486872138581611960251920581495054905013430682473519709885574","seed":26927324371801091486872138581611960251920581495054905013430682473519709885574,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/9.xbar_error_random/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/9.xbar_error_random/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=805508230 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_error_random.805508230' seed=26927324371801091486872138581611960251920581495054905013430682473519709885574 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=26927324371801091486872138581611960251920581495054905013430682473519709885574 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/9.xbar_error_random/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_unmapped_addr","qual_name":"9.xbar_unmapped_addr.39171669030663799833350859074074032767761622089222227166306306105769714064094","seed":39171669030663799833350859074074032767761622089222227166306306105769714064094,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/9.xbar_unmapped_addr/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/9.xbar_unmapped_addr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=130620126 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_unmapped_addr.130620126' seed=39171669030663799833350859074074032767761622089222227166306306105769714064094 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=39171669030663799833350859074074032767761622089222227166306306105769714064094 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/9.xbar_unmapped_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_and_unmapped_addr","qual_name":"9.xbar_error_and_unmapped_addr.86385221492993947264076456861245115631446026261401340310773538850669989283604","seed":86385221492993947264076456861245115631446026261401340310773538850669989283604,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/9.xbar_error_and_unmapped_addr/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/9.xbar_error_and_unmapped_addr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3596961556 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_error_and_unmapped_addr.3596961556' seed=86385221492993947264076456861245115631446026261401340310773538850669989283604 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=86385221492993947264076456861245115631446026261401340310773538850669989283604 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/9.xbar_error_and_unmapped_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all","qual_name":"9.xbar_stress_all.21351795440744691488559465853446856263089030153980053405845321837790284272023","seed":21351795440744691488559465853446856263089030153980053405845321837790284272023,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/9.xbar_stress_all/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/9.xbar_stress_all/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1248121239 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all.1248121239' seed=21351795440744691488559465853446856263089030153980053405845321837790284272023 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=21351795440744691488559465853446856263089030153980053405845321837790284272023 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/9.xbar_stress_all/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_rand_reset","qual_name":"9.xbar_stress_all_with_rand_reset.3156395581554457350725486980850159880691365565539204974255740182366100001494","seed":3156395581554457350725486980850159880691365565539204974255740182366100001494,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/9.xbar_stress_all_with_rand_reset/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/9.xbar_stress_all_with_rand_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2109870806 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_rand_reset.2109870806' seed=3156395581554457350725486980850159880691365565539204974255740182366100001494 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=3156395581554457350725486980850159880691365565539204974255740182366100001494 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/9.xbar_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"9.xbar_stress_all_with_error.31050722441783575364325479600074436051555113875292881709575823454322748487821","seed":31050722441783575364325479600074436051555113875292881709575823454322748487821,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/9.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/9.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4159371405 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_error.4159371405' seed=31050722441783575364325479600074436051555113875292881709575823454322748487821 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=31050722441783575364325479600074436051555113875292881709575823454322748487821 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/9.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"9.xbar_stress_all_with_reset_error.101447163090128845189434489522692539154531113072158165540177898516557919385840","seed":101447163090128845189434489522692539154531113072158165540177898516557919385840,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/9.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/9.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3460004080 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_reset_error.3460004080' seed=101447163090128845189434489522692539154531113072158165540177898516557919385840 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=101447163090128845189434489522692539154531113072158165540177898516557919385840 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/9.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke","qual_name":"10.xbar_smoke.23691354889395180930711143292952310368396345717718000589236107718247106222319","seed":23691354889395180930711143292952310368396345717718000589236107718247106222319,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/10.xbar_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/10.xbar_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1156061423 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke.1156061423' seed=23691354889395180930711143292952310368396345717718000589236107718247106222319 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=23691354889395180930711143292952310368396345717718000589236107718247106222319 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/10.xbar_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_zero_delays","qual_name":"10.xbar_smoke_zero_delays.29610514219806626140831057381761828170083175683504085576304620986455796934128","seed":29610514219806626140831057381761828170083175683504085576304620986455796934128,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/10.xbar_smoke_zero_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/10.xbar_smoke_zero_delays/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3621447152 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_zero_delays.3621447152' seed=29610514219806626140831057381761828170083175683504085576304620986455796934128 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=29610514219806626140831057381761828170083175683504085576304620986455796934128 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/10.xbar_smoke_zero_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_large_delays","qual_name":"10.xbar_smoke_large_delays.75038644680966295804288962136399186863460860156705580836702349117206656341636","seed":75038644680966295804288962136399186863460860156705580836702349117206656341636,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/10.xbar_smoke_large_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/10.xbar_smoke_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2725402244 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_large_delays.2725402244' seed=75038644680966295804288962136399186863460860156705580836702349117206656341636 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=75038644680966295804288962136399186863460860156705580836702349117206656341636 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/10.xbar_smoke_large_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_slow_rsp","qual_name":"10.xbar_smoke_slow_rsp.27747677516964100896951548227199695032985202161683654957545931491397262362367","seed":27747677516964100896951548227199695032985202161683654957545931491397262362367,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/10.xbar_smoke_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/10.xbar_smoke_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3005990655 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_slow_rsp.3005990655' seed=27747677516964100896951548227199695032985202161683654957545931491397262362367 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=27747677516964100896951548227199695032985202161683654957545931491397262362367 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/10.xbar_smoke_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random","qual_name":"10.xbar_random.103405716141593164316169346777606948580620671484178717862178300612017618330628","seed":103405716141593164316169346777606948580620671484178717862178300612017618330628,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/10.xbar_random/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/10.xbar_random/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3433210884 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random.3433210884' seed=103405716141593164316169346777606948580620671484178717862178300612017618330628 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=103405716141593164316169346777606948580620671484178717862178300612017618330628 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/10.xbar_random/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_zero_delays","qual_name":"10.xbar_random_zero_delays.83276244970858513328426113697754334709620345834724338069185221709483269363570","seed":83276244970858513328426113697754334709620345834724338069185221709483269363570,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/10.xbar_random_zero_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/10.xbar_random_zero_delays/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3690927986 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_zero_delays.3690927986' seed=83276244970858513328426113697754334709620345834724338069185221709483269363570 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=83276244970858513328426113697754334709620345834724338069185221709483269363570 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/10.xbar_random_zero_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_large_delays","qual_name":"10.xbar_random_large_delays.108925808695720537948072370378046019502258373886825778155268350325160180211728","seed":108925808695720537948072370378046019502258373886825778155268350325160180211728,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/10.xbar_random_large_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/10.xbar_random_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=33316880 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_large_delays.33316880' seed=108925808695720537948072370378046019502258373886825778155268350325160180211728 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=108925808695720537948072370378046019502258373886825778155268350325160180211728 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/10.xbar_random_large_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_slow_rsp","qual_name":"10.xbar_random_slow_rsp.105955135881305090952080019991642535802732429793484380279677561648990532276160","seed":105955135881305090952080019991642535802732429793484380279677561648990532276160,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/10.xbar_random_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/10.xbar_random_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=552996800 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_slow_rsp.552996800' seed=105955135881305090952080019991642535802732429793484380279677561648990532276160 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=105955135881305090952080019991642535802732429793484380279677561648990532276160 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/10.xbar_random_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device","qual_name":"10.xbar_access_same_device.82238349267619246025043071484472871913806891515955682653777655951265753187269","seed":82238349267619246025043071484472871913806891515955682653777655951265753187269,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/10.xbar_access_same_device/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/10.xbar_access_same_device/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2010366917 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device.2010366917' seed=82238349267619246025043071484472871913806891515955682653777655951265753187269 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=82238349267619246025043071484472871913806891515955682653777655951265753187269 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/10.xbar_access_same_device/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"10.xbar_access_same_device_slow_rsp.91445336980981944563734184715851147792932996878196189106958620367980830782047","seed":91445336980981944563734184715851147792932996878196189106958620367980830782047,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/10.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/10.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3672765023 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device_slow_rsp.3672765023' seed=91445336980981944563734184715851147792932996878196189106958620367980830782047 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=91445336980981944563734184715851147792932996878196189106958620367980830782047 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/10.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_same_source","qual_name":"10.xbar_same_source.22028197598644141474431842821573243419614270736318998937453278376086255565860","seed":22028197598644141474431842821573243419614270736318998937453278376086255565860,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/10.xbar_same_source/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/10.xbar_same_source/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=953023524 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_same_source.953023524' seed=22028197598644141474431842821573243419614270736318998937453278376086255565860 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=22028197598644141474431842821573243419614270736318998937453278376086255565860 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/10.xbar_same_source/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_same_source_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_random","qual_name":"10.xbar_error_random.21519814239965358573382192138343941091557394582239872714728501625797924154719","seed":21519814239965358573382192138343941091557394582239872714728501625797924154719,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/10.xbar_error_random/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/10.xbar_error_random/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3591433567 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_error_random.3591433567' seed=21519814239965358573382192138343941091557394582239872714728501625797924154719 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=21519814239965358573382192138343941091557394582239872714728501625797924154719 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/10.xbar_error_random/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_unmapped_addr","qual_name":"10.xbar_unmapped_addr.101338094171333374453328058317325576235836916604643209383572154953787231915886","seed":101338094171333374453328058317325576235836916604643209383572154953787231915886,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/10.xbar_unmapped_addr/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/10.xbar_unmapped_addr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1113542510 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_unmapped_addr.1113542510' seed=101338094171333374453328058317325576235836916604643209383572154953787231915886 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=101338094171333374453328058317325576235836916604643209383572154953787231915886 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/10.xbar_unmapped_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_and_unmapped_addr","qual_name":"10.xbar_error_and_unmapped_addr.114139696495244043127964319071832878753892369910103227024724450300809338201777","seed":114139696495244043127964319071832878753892369910103227024724450300809338201777,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/10.xbar_error_and_unmapped_addr/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/10.xbar_error_and_unmapped_addr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=662480561 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_error_and_unmapped_addr.662480561' seed=114139696495244043127964319071832878753892369910103227024724450300809338201777 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=114139696495244043127964319071832878753892369910103227024724450300809338201777 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/10.xbar_error_and_unmapped_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all","qual_name":"10.xbar_stress_all.17036192253390608930538349308211151144781794318410166652642900644531961338358","seed":17036192253390608930538349308211151144781794318410166652642900644531961338358,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/10.xbar_stress_all/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/10.xbar_stress_all/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1388059126 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all.1388059126' seed=17036192253390608930538349308211151144781794318410166652642900644531961338358 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=17036192253390608930538349308211151144781794318410166652642900644531961338358 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/10.xbar_stress_all/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_rand_reset","qual_name":"10.xbar_stress_all_with_rand_reset.74735631883457159127535073349238333783373978901435681494306149447804113854421","seed":74735631883457159127535073349238333783373978901435681494306149447804113854421,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/10.xbar_stress_all_with_rand_reset/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/10.xbar_stress_all_with_rand_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3690143701 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_rand_reset.3690143701' seed=74735631883457159127535073349238333783373978901435681494306149447804113854421 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=74735631883457159127535073349238333783373978901435681494306149447804113854421 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/10.xbar_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"10.xbar_stress_all_with_error.106801709950584030789381075117138643028941158513748328064772540265586153338716","seed":106801709950584030789381075117138643028941158513748328064772540265586153338716,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/10.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/10.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=77182812 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_error.77182812' seed=106801709950584030789381075117138643028941158513748328064772540265586153338716 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=106801709950584030789381075117138643028941158513748328064772540265586153338716 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/10.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"10.xbar_stress_all_with_reset_error.89149013261827435700788218496837434700407183838587343878615766960389203798074","seed":89149013261827435700788218496837434700407183838587343878615766960389203798074,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/10.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/10.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3963988026 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_reset_error.3963988026' seed=89149013261827435700788218496837434700407183838587343878615766960389203798074 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=89149013261827435700788218496837434700407183838587343878615766960389203798074 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/10.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke","qual_name":"11.xbar_smoke.50368149722443740418599531954055351180277394324711026526772773255166228627105","seed":50368149722443740418599531954055351180277394324711026526772773255166228627105,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/11.xbar_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/11.xbar_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4162518689 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke.4162518689' seed=50368149722443740418599531954055351180277394324711026526772773255166228627105 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=50368149722443740418599531954055351180277394324711026526772773255166228627105 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/11.xbar_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_zero_delays","qual_name":"11.xbar_smoke_zero_delays.30401669474384702810630413494041075339052468125186305106813590530140557567971","seed":30401669474384702810630413494041075339052468125186305106813590530140557567971,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/11.xbar_smoke_zero_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/11.xbar_smoke_zero_delays/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=552364003 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_zero_delays.552364003' seed=30401669474384702810630413494041075339052468125186305106813590530140557567971 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=30401669474384702810630413494041075339052468125186305106813590530140557567971 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/11.xbar_smoke_zero_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_large_delays","qual_name":"11.xbar_smoke_large_delays.4724099459582855400913467903568920075388274869860717701256045541380351234641","seed":4724099459582855400913467903568920075388274869860717701256045541380351234641,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/11.xbar_smoke_large_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/11.xbar_smoke_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1938461265 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_large_delays.1938461265' seed=4724099459582855400913467903568920075388274869860717701256045541380351234641 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=4724099459582855400913467903568920075388274869860717701256045541380351234641 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/11.xbar_smoke_large_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_slow_rsp","qual_name":"11.xbar_smoke_slow_rsp.91813537868617190031631688134709962512866523212034148106475550180802420973936","seed":91813537868617190031631688134709962512866523212034148106475550180802420973936,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/11.xbar_smoke_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/11.xbar_smoke_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=56009072 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_slow_rsp.56009072' seed=91813537868617190031631688134709962512866523212034148106475550180802420973936 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=91813537868617190031631688134709962512866523212034148106475550180802420973936 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/11.xbar_smoke_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random","qual_name":"11.xbar_random.80255448588068514458243936511877445936839901616433248933555051140621719969992","seed":80255448588068514458243936511877445936839901616433248933555051140621719969992,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/11.xbar_random/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/11.xbar_random/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2183274696 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random.2183274696' seed=80255448588068514458243936511877445936839901616433248933555051140621719969992 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=80255448588068514458243936511877445936839901616433248933555051140621719969992 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/11.xbar_random/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_zero_delays","qual_name":"11.xbar_random_zero_delays.70059229883432384443187551804656556755780938124104874053446670454654659041322","seed":70059229883432384443187551804656556755780938124104874053446670454654659041322,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/11.xbar_random_zero_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/11.xbar_random_zero_delays/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1783470122 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_zero_delays.1783470122' seed=70059229883432384443187551804656556755780938124104874053446670454654659041322 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=70059229883432384443187551804656556755780938124104874053446670454654659041322 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/11.xbar_random_zero_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_large_delays","qual_name":"11.xbar_random_large_delays.64798332520885265702051993632424943590675587402126496627383964917077653016200","seed":64798332520885265702051993632424943590675587402126496627383964917077653016200,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/11.xbar_random_large_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/11.xbar_random_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2478001800 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_large_delays.2478001800' seed=64798332520885265702051993632424943590675587402126496627383964917077653016200 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=64798332520885265702051993632424943590675587402126496627383964917077653016200 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/11.xbar_random_large_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_slow_rsp","qual_name":"11.xbar_random_slow_rsp.61953356161923732388249241050724304446845871766968993829278106428080400202702","seed":61953356161923732388249241050724304446845871766968993829278106428080400202702,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/11.xbar_random_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/11.xbar_random_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1780054990 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_slow_rsp.1780054990' seed=61953356161923732388249241050724304446845871766968993829278106428080400202702 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=61953356161923732388249241050724304446845871766968993829278106428080400202702 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/11.xbar_random_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device","qual_name":"11.xbar_access_same_device.81976892881378038003872062066370775705162751707994266740756335967512393579844","seed":81976892881378038003872062066370775705162751707994266740756335967512393579844,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/11.xbar_access_same_device/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/11.xbar_access_same_device/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3692723524 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device.3692723524' seed=81976892881378038003872062066370775705162751707994266740756335967512393579844 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=81976892881378038003872062066370775705162751707994266740756335967512393579844 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/11.xbar_access_same_device/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"11.xbar_access_same_device_slow_rsp.41999650251551818593843017187892962873458139961299238528233659982910869739926","seed":41999650251551818593843017187892962873458139961299238528233659982910869739926,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/11.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/11.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1513888150 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device_slow_rsp.1513888150' seed=41999650251551818593843017187892962873458139961299238528233659982910869739926 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=41999650251551818593843017187892962873458139961299238528233659982910869739926 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/11.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_same_source","qual_name":"11.xbar_same_source.74654516141552518337252667758667223473339609577555436459044021337995025767902","seed":74654516141552518337252667758667223473339609577555436459044021337995025767902,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/11.xbar_same_source/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/11.xbar_same_source/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2009783774 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_same_source.2009783774' seed=74654516141552518337252667758667223473339609577555436459044021337995025767902 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=74654516141552518337252667758667223473339609577555436459044021337995025767902 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/11.xbar_same_source/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_same_source_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_random","qual_name":"11.xbar_error_random.18094173047301186791490372302339028883488838782326543960092049993859808632114","seed":18094173047301186791490372302339028883488838782326543960092049993859808632114,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/11.xbar_error_random/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/11.xbar_error_random/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4257750322 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_error_random.4257750322' seed=18094173047301186791490372302339028883488838782326543960092049993859808632114 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=18094173047301186791490372302339028883488838782326543960092049993859808632114 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/11.xbar_error_random/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_unmapped_addr","qual_name":"11.xbar_unmapped_addr.87060944958123213308231867031102098356914306035029732379577270534059797923038","seed":87060944958123213308231867031102098356914306035029732379577270534059797923038,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/11.xbar_unmapped_addr/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/11.xbar_unmapped_addr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2301248734 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_unmapped_addr.2301248734' seed=87060944958123213308231867031102098356914306035029732379577270534059797923038 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=87060944958123213308231867031102098356914306035029732379577270534059797923038 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/11.xbar_unmapped_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_and_unmapped_addr","qual_name":"11.xbar_error_and_unmapped_addr.77495829389625541279399524357827962414933432938527757431868183345055072817706","seed":77495829389625541279399524357827962414933432938527757431868183345055072817706,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/11.xbar_error_and_unmapped_addr/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/11.xbar_error_and_unmapped_addr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3126891050 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_error_and_unmapped_addr.3126891050' seed=77495829389625541279399524357827962414933432938527757431868183345055072817706 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=77495829389625541279399524357827962414933432938527757431868183345055072817706 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/11.xbar_error_and_unmapped_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all","qual_name":"11.xbar_stress_all.75708974005989799965234793895045078670119896540269737991303591624655004294861","seed":75708974005989799965234793895045078670119896540269737991303591624655004294861,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/11.xbar_stress_all/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/11.xbar_stress_all/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1872813773 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all.1872813773' seed=75708974005989799965234793895045078670119896540269737991303591624655004294861 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=75708974005989799965234793895045078670119896540269737991303591624655004294861 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/11.xbar_stress_all/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_rand_reset","qual_name":"11.xbar_stress_all_with_rand_reset.15313068592516354623784362915060212512880134679383037025470890682867921824466","seed":15313068592516354623784362915060212512880134679383037025470890682867921824466,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/11.xbar_stress_all_with_rand_reset/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/11.xbar_stress_all_with_rand_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2587470546 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_rand_reset.2587470546' seed=15313068592516354623784362915060212512880134679383037025470890682867921824466 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=15313068592516354623784362915060212512880134679383037025470890682867921824466 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/11.xbar_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"11.xbar_stress_all_with_error.45264524989859550441036814160325688802941577795798032885017270373300052649540","seed":45264524989859550441036814160325688802941577795798032885017270373300052649540,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/11.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/11.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1193764420 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_error.1193764420' seed=45264524989859550441036814160325688802941577795798032885017270373300052649540 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=45264524989859550441036814160325688802941577795798032885017270373300052649540 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/11.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"11.xbar_stress_all_with_reset_error.83122352958811474925289213959153650123123440179473102760816698315102645004731","seed":83122352958811474925289213959153650123123440179473102760816698315102645004731,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/11.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/11.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3660720571 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_reset_error.3660720571' seed=83122352958811474925289213959153650123123440179473102760816698315102645004731 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=83122352958811474925289213959153650123123440179473102760816698315102645004731 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/11.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke","qual_name":"12.xbar_smoke.109312608127409530044184185781283462987196305476908946571656188620853344078468","seed":109312608127409530044184185781283462987196305476908946571656188620853344078468,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/12.xbar_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/12.xbar_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=32377476 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke.32377476' seed=109312608127409530044184185781283462987196305476908946571656188620853344078468 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=109312608127409530044184185781283462987196305476908946571656188620853344078468 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/12.xbar_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_zero_delays","qual_name":"12.xbar_smoke_zero_delays.33145633385578296277153702004981399541293281614378731380999025905983283458194","seed":33145633385578296277153702004981399541293281614378731380999025905983283458194,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/12.xbar_smoke_zero_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/12.xbar_smoke_zero_delays/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=988213394 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_zero_delays.988213394' seed=33145633385578296277153702004981399541293281614378731380999025905983283458194 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=33145633385578296277153702004981399541293281614378731380999025905983283458194 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/12.xbar_smoke_zero_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_large_delays","qual_name":"12.xbar_smoke_large_delays.107456206037226729089966906191691494475650113431864552290442181511832395612211","seed":107456206037226729089966906191691494475650113431864552290442181511832395612211,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/12.xbar_smoke_large_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/12.xbar_smoke_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3764420659 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_large_delays.3764420659' seed=107456206037226729089966906191691494475650113431864552290442181511832395612211 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=107456206037226729089966906191691494475650113431864552290442181511832395612211 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/12.xbar_smoke_large_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_slow_rsp","qual_name":"12.xbar_smoke_slow_rsp.56398687928768627742560803851521928256552185559952752063546662414632679350702","seed":56398687928768627742560803851521928256552185559952752063546662414632679350702,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/12.xbar_smoke_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/12.xbar_smoke_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2273812910 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_slow_rsp.2273812910' seed=56398687928768627742560803851521928256552185559952752063546662414632679350702 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=56398687928768627742560803851521928256552185559952752063546662414632679350702 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/12.xbar_smoke_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random","qual_name":"12.xbar_random.63926940732310276389528370776076259050144736194758677581427813867272350826426","seed":63926940732310276389528370776076259050144736194758677581427813867272350826426,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/12.xbar_random/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/12.xbar_random/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2293596090 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random.2293596090' seed=63926940732310276389528370776076259050144736194758677581427813867272350826426 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=63926940732310276389528370776076259050144736194758677581427813867272350826426 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/12.xbar_random/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_zero_delays","qual_name":"12.xbar_random_zero_delays.4562350900790250314190057190934084493791542219781915531429159851866287439738","seed":4562350900790250314190057190934084493791542219781915531429159851866287439738,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/12.xbar_random_zero_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/12.xbar_random_zero_delays/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=775094138 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_zero_delays.775094138' seed=4562350900790250314190057190934084493791542219781915531429159851866287439738 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=4562350900790250314190057190934084493791542219781915531429159851866287439738 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/12.xbar_random_zero_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_large_delays","qual_name":"12.xbar_random_large_delays.61668801942970048548255468471122338205760768510738961372489832833657499835963","seed":61668801942970048548255468471122338205760768510738961372489832833657499835963,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/12.xbar_random_large_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/12.xbar_random_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2009620027 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_large_delays.2009620027' seed=61668801942970048548255468471122338205760768510738961372489832833657499835963 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=61668801942970048548255468471122338205760768510738961372489832833657499835963 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/12.xbar_random_large_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_slow_rsp","qual_name":"12.xbar_random_slow_rsp.72047511650497886049114539589367403154576574313077322958894885833403071233449","seed":72047511650497886049114539589367403154576574313077322958894885833403071233449,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/12.xbar_random_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/12.xbar_random_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2620685737 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_slow_rsp.2620685737' seed=72047511650497886049114539589367403154576574313077322958894885833403071233449 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=72047511650497886049114539589367403154576574313077322958894885833403071233449 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/12.xbar_random_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device","qual_name":"12.xbar_access_same_device.45380338502662979568246557268597870993435212549756448926212178938052492980309","seed":45380338502662979568246557268597870993435212549756448926212178938052492980309,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/12.xbar_access_same_device/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/12.xbar_access_same_device/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4113887317 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device.4113887317' seed=45380338502662979568246557268597870993435212549756448926212178938052492980309 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=45380338502662979568246557268597870993435212549756448926212178938052492980309 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/12.xbar_access_same_device/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"12.xbar_access_same_device_slow_rsp.58271259127853215741470425552750172401056704409137249507014629379834962035090","seed":58271259127853215741470425552750172401056704409137249507014629379834962035090,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/12.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/12.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=588038546 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device_slow_rsp.588038546' seed=58271259127853215741470425552750172401056704409137249507014629379834962035090 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=58271259127853215741470425552750172401056704409137249507014629379834962035090 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/12.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_same_source","qual_name":"12.xbar_same_source.40747824614648382859326523483805058087580141037484934539573041046624849761366","seed":40747824614648382859326523483805058087580141037484934539573041046624849761366,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/12.xbar_same_source/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/12.xbar_same_source/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3239711830 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_same_source.3239711830' seed=40747824614648382859326523483805058087580141037484934539573041046624849761366 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=40747824614648382859326523483805058087580141037484934539573041046624849761366 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/12.xbar_same_source/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_same_source_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_random","qual_name":"12.xbar_error_random.80303950427336257001291149529796420464430174494191255036466085149500098770349","seed":80303950427336257001291149529796420464430174494191255036466085149500098770349,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/12.xbar_error_random/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/12.xbar_error_random/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3820516781 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_error_random.3820516781' seed=80303950427336257001291149529796420464430174494191255036466085149500098770349 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=80303950427336257001291149529796420464430174494191255036466085149500098770349 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/12.xbar_error_random/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_unmapped_addr","qual_name":"12.xbar_unmapped_addr.24898193772255177997984498893956704859058981390463290764765631542661301166022","seed":24898193772255177997984498893956704859058981390463290764765631542661301166022,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/12.xbar_unmapped_addr/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/12.xbar_unmapped_addr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1756389318 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_unmapped_addr.1756389318' seed=24898193772255177997984498893956704859058981390463290764765631542661301166022 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=24898193772255177997984498893956704859058981390463290764765631542661301166022 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/12.xbar_unmapped_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_and_unmapped_addr","qual_name":"12.xbar_error_and_unmapped_addr.92766371288821988804616296335006607968234688950641467849213253071236294301626","seed":92766371288821988804616296335006607968234688950641467849213253071236294301626,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/12.xbar_error_and_unmapped_addr/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/12.xbar_error_and_unmapped_addr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2282018746 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_error_and_unmapped_addr.2282018746' seed=92766371288821988804616296335006607968234688950641467849213253071236294301626 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=92766371288821988804616296335006607968234688950641467849213253071236294301626 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/12.xbar_error_and_unmapped_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all","qual_name":"12.xbar_stress_all.14716562556110761091989361869202610673296373898472911499790072102011777248306","seed":14716562556110761091989361869202610673296373898472911499790072102011777248306,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/12.xbar_stress_all/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/12.xbar_stress_all/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2131422258 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all.2131422258' seed=14716562556110761091989361869202610673296373898472911499790072102011777248306 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=14716562556110761091989361869202610673296373898472911499790072102011777248306 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/12.xbar_stress_all/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_rand_reset","qual_name":"12.xbar_stress_all_with_rand_reset.50214286520013059311814260027717994245851724977577751285559485275679150775293","seed":50214286520013059311814260027717994245851724977577751285559485275679150775293,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/12.xbar_stress_all_with_rand_reset/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/12.xbar_stress_all_with_rand_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2355567613 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_rand_reset.2355567613' seed=50214286520013059311814260027717994245851724977577751285559485275679150775293 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=50214286520013059311814260027717994245851724977577751285559485275679150775293 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/12.xbar_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"12.xbar_stress_all_with_error.62286786909702159507374973262486091695956828546350010780891184819856988366765","seed":62286786909702159507374973262486091695956828546350010780891184819856988366765,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/12.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/12.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=633792429 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_error.633792429' seed=62286786909702159507374973262486091695956828546350010780891184819856988366765 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=62286786909702159507374973262486091695956828546350010780891184819856988366765 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/12.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"12.xbar_stress_all_with_reset_error.6054889192878087904023645156014518818213585854151955602966335791569681914511","seed":6054889192878087904023645156014518818213585854151955602966335791569681914511,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/12.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/12.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1745754767 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_reset_error.1745754767' seed=6054889192878087904023645156014518818213585854151955602966335791569681914511 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=6054889192878087904023645156014518818213585854151955602966335791569681914511 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/12.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke","qual_name":"13.xbar_smoke.61155922902699995030904347217551022029354984382487116354555399097629211289790","seed":61155922902699995030904347217551022029354984382487116354555399097629211289790,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/13.xbar_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/13.xbar_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1860364478 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke.1860364478' seed=61155922902699995030904347217551022029354984382487116354555399097629211289790 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=61155922902699995030904347217551022029354984382487116354555399097629211289790 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/13.xbar_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_zero_delays","qual_name":"13.xbar_smoke_zero_delays.15349155642561032715298337158424657337207320097236917236567702799587441081986","seed":15349155642561032715298337158424657337207320097236917236567702799587441081986,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/13.xbar_smoke_zero_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/13.xbar_smoke_zero_delays/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=481525378 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_zero_delays.481525378' seed=15349155642561032715298337158424657337207320097236917236567702799587441081986 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=15349155642561032715298337158424657337207320097236917236567702799587441081986 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/13.xbar_smoke_zero_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_large_delays","qual_name":"13.xbar_smoke_large_delays.41748818082802117308453625657282552802243353333948200085974566474396196048565","seed":41748818082802117308453625657282552802243353333948200085974566474396196048565,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/13.xbar_smoke_large_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/13.xbar_smoke_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=959876789 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_large_delays.959876789' seed=41748818082802117308453625657282552802243353333948200085974566474396196048565 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=41748818082802117308453625657282552802243353333948200085974566474396196048565 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/13.xbar_smoke_large_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_slow_rsp","qual_name":"13.xbar_smoke_slow_rsp.7731207681594427913637574230726913047442445082373993833264209317343935540762","seed":7731207681594427913637574230726913047442445082373993833264209317343935540762,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/13.xbar_smoke_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/13.xbar_smoke_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4183502362 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_slow_rsp.4183502362' seed=7731207681594427913637574230726913047442445082373993833264209317343935540762 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=7731207681594427913637574230726913047442445082373993833264209317343935540762 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/13.xbar_smoke_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random","qual_name":"13.xbar_random.23681461953172315824793155775123478616428182110424207884662075523260021102666","seed":23681461953172315824793155775123478616428182110424207884662075523260021102666,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/13.xbar_random/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/13.xbar_random/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3387840586 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random.3387840586' seed=23681461953172315824793155775123478616428182110424207884662075523260021102666 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=23681461953172315824793155775123478616428182110424207884662075523260021102666 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/13.xbar_random/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_zero_delays","qual_name":"13.xbar_random_zero_delays.34891665857430548465820537391097283637637874374268876298667171799186274047970","seed":34891665857430548465820537391097283637637874374268876298667171799186274047970,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/13.xbar_random_zero_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/13.xbar_random_zero_delays/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2992429026 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_zero_delays.2992429026' seed=34891665857430548465820537391097283637637874374268876298667171799186274047970 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=34891665857430548465820537391097283637637874374268876298667171799186274047970 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/13.xbar_random_zero_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_large_delays","qual_name":"13.xbar_random_large_delays.84419314615114185264461177860698073366325904137105259915254581209762307860382","seed":84419314615114185264461177860698073366325904137105259915254581209762307860382,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/13.xbar_random_large_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/13.xbar_random_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=611411870 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_large_delays.611411870' seed=84419314615114185264461177860698073366325904137105259915254581209762307860382 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=84419314615114185264461177860698073366325904137105259915254581209762307860382 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/13.xbar_random_large_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_slow_rsp","qual_name":"13.xbar_random_slow_rsp.46777914027934833896442221070555204520566149389753876217296605217512444430575","seed":46777914027934833896442221070555204520566149389753876217296605217512444430575,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/13.xbar_random_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/13.xbar_random_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3461908719 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_slow_rsp.3461908719' seed=46777914027934833896442221070555204520566149389753876217296605217512444430575 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=46777914027934833896442221070555204520566149389753876217296605217512444430575 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/13.xbar_random_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device","qual_name":"13.xbar_access_same_device.10969490443091827589691524879762168788080800090498328458148030939746581349513","seed":10969490443091827589691524879762168788080800090498328458148030939746581349513,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/13.xbar_access_same_device/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/13.xbar_access_same_device/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1148978313 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device.1148978313' seed=10969490443091827589691524879762168788080800090498328458148030939746581349513 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=10969490443091827589691524879762168788080800090498328458148030939746581349513 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/13.xbar_access_same_device/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"13.xbar_access_same_device_slow_rsp.99265693769385607368135140394246116054375696290427866496179312042660659148528","seed":99265693769385607368135140394246116054375696290427866496179312042660659148528,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/13.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/13.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=38221552 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device_slow_rsp.38221552' seed=99265693769385607368135140394246116054375696290427866496179312042660659148528 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=99265693769385607368135140394246116054375696290427866496179312042660659148528 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/13.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_same_source","qual_name":"13.xbar_same_source.41717419249607867635405331418421307653416390788027142802135266528285349530063","seed":41717419249607867635405331418421307653416390788027142802135266528285349530063,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/13.xbar_same_source/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/13.xbar_same_source/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3084274127 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_same_source.3084274127' seed=41717419249607867635405331418421307653416390788027142802135266528285349530063 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=41717419249607867635405331418421307653416390788027142802135266528285349530063 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/13.xbar_same_source/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_same_source_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_random","qual_name":"13.xbar_error_random.5247782223397953641269424876094103961720537739094626970353638478022348092282","seed":5247782223397953641269424876094103961720537739094626970353638478022348092282,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/13.xbar_error_random/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/13.xbar_error_random/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3826758522 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_error_random.3826758522' seed=5247782223397953641269424876094103961720537739094626970353638478022348092282 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=5247782223397953641269424876094103961720537739094626970353638478022348092282 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/13.xbar_error_random/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_unmapped_addr","qual_name":"13.xbar_unmapped_addr.714373805127512366103139257623085387880706697238784380274576178254405965649","seed":714373805127512366103139257623085387880706697238784380274576178254405965649,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/13.xbar_unmapped_addr/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/13.xbar_unmapped_addr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1941182289 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_unmapped_addr.1941182289' seed=714373805127512366103139257623085387880706697238784380274576178254405965649 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=714373805127512366103139257623085387880706697238784380274576178254405965649 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/13.xbar_unmapped_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_and_unmapped_addr","qual_name":"13.xbar_error_and_unmapped_addr.16317582731210676979985083007992061991918464896418144991997316108548933903089","seed":16317582731210676979985083007992061991918464896418144991997316108548933903089,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/13.xbar_error_and_unmapped_addr/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/13.xbar_error_and_unmapped_addr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4286538481 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_error_and_unmapped_addr.4286538481' seed=16317582731210676979985083007992061991918464896418144991997316108548933903089 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=16317582731210676979985083007992061991918464896418144991997316108548933903089 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/13.xbar_error_and_unmapped_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all","qual_name":"13.xbar_stress_all.23474225557956669580695870764089859192682307612609848041116437374592954131040","seed":23474225557956669580695870764089859192682307612609848041116437374592954131040,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/13.xbar_stress_all/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/13.xbar_stress_all/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3082805856 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all.3082805856' seed=23474225557956669580695870764089859192682307612609848041116437374592954131040 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=23474225557956669580695870764089859192682307612609848041116437374592954131040 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/13.xbar_stress_all/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_rand_reset","qual_name":"13.xbar_stress_all_with_rand_reset.103482843338770921871938400263103134434225008892526937348292700836288026163409","seed":103482843338770921871938400263103134434225008892526937348292700836288026163409,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/13.xbar_stress_all_with_rand_reset/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/13.xbar_stress_all_with_rand_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2450569425 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_rand_reset.2450569425' seed=103482843338770921871938400263103134434225008892526937348292700836288026163409 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=103482843338770921871938400263103134434225008892526937348292700836288026163409 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/13.xbar_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"13.xbar_stress_all_with_error.22329483369565075194369765143525929624399477516832359874512230521804320427127","seed":22329483369565075194369765143525929624399477516832359874512230521804320427127,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/13.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/13.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2965392503 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_error.2965392503' seed=22329483369565075194369765143525929624399477516832359874512230521804320427127 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=22329483369565075194369765143525929624399477516832359874512230521804320427127 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/13.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"13.xbar_stress_all_with_reset_error.16901455625724955435970191158146476968547907171880029547003867886680183848594","seed":16901455625724955435970191158146476968547907171880029547003867886680183848594,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/13.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/13.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2159197842 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_reset_error.2159197842' seed=16901455625724955435970191158146476968547907171880029547003867886680183848594 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=16901455625724955435970191158146476968547907171880029547003867886680183848594 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/13.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke","qual_name":"14.xbar_smoke.10877560453355150982600531475115808707756467603492184222048229030213410938677","seed":10877560453355150982600531475115808707756467603492184222048229030213410938677,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/14.xbar_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/14.xbar_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3400589109 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke.3400589109' seed=10877560453355150982600531475115808707756467603492184222048229030213410938677 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=10877560453355150982600531475115808707756467603492184222048229030213410938677 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/14.xbar_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_zero_delays","qual_name":"14.xbar_smoke_zero_delays.62076212412177092710813833563181138692139856622200095993185646744063140311212","seed":62076212412177092710813833563181138692139856622200095993185646744063140311212,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/14.xbar_smoke_zero_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/14.xbar_smoke_zero_delays/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2163617964 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_zero_delays.2163617964' seed=62076212412177092710813833563181138692139856622200095993185646744063140311212 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=62076212412177092710813833563181138692139856622200095993185646744063140311212 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/14.xbar_smoke_zero_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_large_delays","qual_name":"14.xbar_smoke_large_delays.13447318943998438832844780846352910089038390693890312546991498198337906898990","seed":13447318943998438832844780846352910089038390693890312546991498198337906898990,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/14.xbar_smoke_large_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/14.xbar_smoke_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2214426670 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_large_delays.2214426670' seed=13447318943998438832844780846352910089038390693890312546991498198337906898990 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=13447318943998438832844780846352910089038390693890312546991498198337906898990 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/14.xbar_smoke_large_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_slow_rsp","qual_name":"14.xbar_smoke_slow_rsp.103386843257634595693893290685541043121882888274778917928567106747190024421947","seed":103386843257634595693893290685541043121882888274778917928567106747190024421947,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/14.xbar_smoke_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/14.xbar_smoke_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4255728187 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_slow_rsp.4255728187' seed=103386843257634595693893290685541043121882888274778917928567106747190024421947 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=103386843257634595693893290685541043121882888274778917928567106747190024421947 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/14.xbar_smoke_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random","qual_name":"14.xbar_random.1431209430311941255229262837848567779186901441681920786369945567353530577158","seed":1431209430311941255229262837848567779186901441681920786369945567353530577158,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/14.xbar_random/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/14.xbar_random/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1489596678 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random.1489596678' seed=1431209430311941255229262837848567779186901441681920786369945567353530577158 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=1431209430311941255229262837848567779186901441681920786369945567353530577158 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/14.xbar_random/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_zero_delays","qual_name":"14.xbar_random_zero_delays.62544633800663338817873549402249748662944983770339518254701367053215511179479","seed":62544633800663338817873549402249748662944983770339518254701367053215511179479,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/14.xbar_random_zero_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/14.xbar_random_zero_delays/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=701067479 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_zero_delays.701067479' seed=62544633800663338817873549402249748662944983770339518254701367053215511179479 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=62544633800663338817873549402249748662944983770339518254701367053215511179479 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/14.xbar_random_zero_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_large_delays","qual_name":"14.xbar_random_large_delays.65363522784368786304879814157622821316667197204514415084320501132583802983550","seed":65363522784368786304879814157622821316667197204514415084320501132583802983550,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/14.xbar_random_large_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/14.xbar_random_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=594760830 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_large_delays.594760830' seed=65363522784368786304879814157622821316667197204514415084320501132583802983550 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=65363522784368786304879814157622821316667197204514415084320501132583802983550 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/14.xbar_random_large_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_slow_rsp","qual_name":"14.xbar_random_slow_rsp.74698487242671658331442701445483136292762925047302304426786989683943175406870","seed":74698487242671658331442701445483136292762925047302304426786989683943175406870,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/14.xbar_random_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/14.xbar_random_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2284373270 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_slow_rsp.2284373270' seed=74698487242671658331442701445483136292762925047302304426786989683943175406870 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=74698487242671658331442701445483136292762925047302304426786989683943175406870 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/14.xbar_random_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device","qual_name":"14.xbar_access_same_device.65484720210243905349265336622565549158185678378517284086389705260835479050232","seed":65484720210243905349265336622565549158185678378517284086389705260835479050232,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/14.xbar_access_same_device/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/14.xbar_access_same_device/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=225269752 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device.225269752' seed=65484720210243905349265336622565549158185678378517284086389705260835479050232 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=65484720210243905349265336622565549158185678378517284086389705260835479050232 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/14.xbar_access_same_device/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"14.xbar_access_same_device_slow_rsp.42684358773316130107918336643759322042309417853527892498255665805367357056497","seed":42684358773316130107918336643759322042309417853527892498255665805367357056497,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/14.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/14.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3736708593 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device_slow_rsp.3736708593' seed=42684358773316130107918336643759322042309417853527892498255665805367357056497 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=42684358773316130107918336643759322042309417853527892498255665805367357056497 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/14.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_same_source","qual_name":"14.xbar_same_source.19997444795060964177035329250737735009511251703489796739911078867890501581521","seed":19997444795060964177035329250737735009511251703489796739911078867890501581521,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/14.xbar_same_source/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/14.xbar_same_source/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2386819793 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_same_source.2386819793' seed=19997444795060964177035329250737735009511251703489796739911078867890501581521 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=19997444795060964177035329250737735009511251703489796739911078867890501581521 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/14.xbar_same_source/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_same_source_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_random","qual_name":"14.xbar_error_random.38908623692448509958143465255256623172992826002591972618711368718447955268587","seed":38908623692448509958143465255256623172992826002591972618711368718447955268587,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/14.xbar_error_random/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/14.xbar_error_random/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1232983019 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_error_random.1232983019' seed=38908623692448509958143465255256623172992826002591972618711368718447955268587 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=38908623692448509958143465255256623172992826002591972618711368718447955268587 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/14.xbar_error_random/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_unmapped_addr","qual_name":"14.xbar_unmapped_addr.87164154492739690103539640415048795688840165283249404257403726805013945606000","seed":87164154492739690103539640415048795688840165283249404257403726805013945606000,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/14.xbar_unmapped_addr/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/14.xbar_unmapped_addr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2990497648 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_unmapped_addr.2990497648' seed=87164154492739690103539640415048795688840165283249404257403726805013945606000 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=87164154492739690103539640415048795688840165283249404257403726805013945606000 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/14.xbar_unmapped_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_and_unmapped_addr","qual_name":"14.xbar_error_and_unmapped_addr.36864222198553869549360191942818791693925794115231297956237633123578459782777","seed":36864222198553869549360191942818791693925794115231297956237633123578459782777,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/14.xbar_error_and_unmapped_addr/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/14.xbar_error_and_unmapped_addr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2132344441 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_error_and_unmapped_addr.2132344441' seed=36864222198553869549360191942818791693925794115231297956237633123578459782777 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=36864222198553869549360191942818791693925794115231297956237633123578459782777 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/14.xbar_error_and_unmapped_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all","qual_name":"14.xbar_stress_all.89465559738949613381056920701486105904178585815982476054974460533462169386748","seed":89465559738949613381056920701486105904178585815982476054974460533462169386748,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/14.xbar_stress_all/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/14.xbar_stress_all/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1275166460 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all.1275166460' seed=89465559738949613381056920701486105904178585815982476054974460533462169386748 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=89465559738949613381056920701486105904178585815982476054974460533462169386748 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/14.xbar_stress_all/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_rand_reset","qual_name":"14.xbar_stress_all_with_rand_reset.2021414604561866022424383632578109274766119179943967740620662139704372695849","seed":2021414604561866022424383632578109274766119179943967740620662139704372695849,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/14.xbar_stress_all_with_rand_reset/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/14.xbar_stress_all_with_rand_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4202763049 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_rand_reset.4202763049' seed=2021414604561866022424383632578109274766119179943967740620662139704372695849 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=2021414604561866022424383632578109274766119179943967740620662139704372695849 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/14.xbar_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"14.xbar_stress_all_with_error.19073414812108104365144829949847576226037809897423852731216552660923427240208","seed":19073414812108104365144829949847576226037809897423852731216552660923427240208,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/14.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/14.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3781081360 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_error.3781081360' seed=19073414812108104365144829949847576226037809897423852731216552660923427240208 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=19073414812108104365144829949847576226037809897423852731216552660923427240208 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/14.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"14.xbar_stress_all_with_reset_error.69192188461578569502854309017226672438641069321915480238204020057431828590094","seed":69192188461578569502854309017226672438641069321915480238204020057431828590094,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/14.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/14.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2008018446 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_reset_error.2008018446' seed=69192188461578569502854309017226672438641069321915480238204020057431828590094 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=69192188461578569502854309017226672438641069321915480238204020057431828590094 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/14.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke","qual_name":"15.xbar_smoke.5483060548357429319711505248635329932370078417751220493740919735164498026085","seed":5483060548357429319711505248635329932370078417751220493740919735164498026085,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/15.xbar_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/15.xbar_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=579280485 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke.579280485' seed=5483060548357429319711505248635329932370078417751220493740919735164498026085 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=5483060548357429319711505248635329932370078417751220493740919735164498026085 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/15.xbar_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_zero_delays","qual_name":"15.xbar_smoke_zero_delays.10948676271067250331810399036965813259568976510717468843625193542345878472155","seed":10948676271067250331810399036965813259568976510717468843625193542345878472155,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/15.xbar_smoke_zero_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/15.xbar_smoke_zero_delays/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1461257691 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_zero_delays.1461257691' seed=10948676271067250331810399036965813259568976510717468843625193542345878472155 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=10948676271067250331810399036965813259568976510717468843625193542345878472155 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/15.xbar_smoke_zero_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_large_delays","qual_name":"15.xbar_smoke_large_delays.55398856723274429158141977606827125928440818852812941154153413299099976822150","seed":55398856723274429158141977606827125928440818852812941154153413299099976822150,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/15.xbar_smoke_large_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/15.xbar_smoke_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=471821702 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_large_delays.471821702' seed=55398856723274429158141977606827125928440818852812941154153413299099976822150 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=55398856723274429158141977606827125928440818852812941154153413299099976822150 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/15.xbar_smoke_large_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_slow_rsp","qual_name":"15.xbar_smoke_slow_rsp.102142535860662450206259146895897739999479630382484240545037316558514825732762","seed":102142535860662450206259146895897739999479630382484240545037316558514825732762,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/15.xbar_smoke_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/15.xbar_smoke_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4142146202 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_slow_rsp.4142146202' seed=102142535860662450206259146895897739999479630382484240545037316558514825732762 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=102142535860662450206259146895897739999479630382484240545037316558514825732762 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/15.xbar_smoke_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random","qual_name":"15.xbar_random.92185092709199990141194291861857886486591711185821544824439759799415481257027","seed":92185092709199990141194291861857886486591711185821544824439759799415481257027,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/15.xbar_random/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/15.xbar_random/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4224404547 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random.4224404547' seed=92185092709199990141194291861857886486591711185821544824439759799415481257027 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=92185092709199990141194291861857886486591711185821544824439759799415481257027 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/15.xbar_random/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_zero_delays","qual_name":"15.xbar_random_zero_delays.87563404998580965129671471987618896497413278821915620042425832958491045022784","seed":87563404998580965129671471987618896497413278821915620042425832958491045022784,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/15.xbar_random_zero_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/15.xbar_random_zero_delays/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1789283392 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_zero_delays.1789283392' seed=87563404998580965129671471987618896497413278821915620042425832958491045022784 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=87563404998580965129671471987618896497413278821915620042425832958491045022784 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/15.xbar_random_zero_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_large_delays","qual_name":"15.xbar_random_large_delays.12771490186019960520750362391601184808945593998849180004911744337580488125195","seed":12771490186019960520750362391601184808945593998849180004911744337580488125195,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/15.xbar_random_large_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/15.xbar_random_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=961800971 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_large_delays.961800971' seed=12771490186019960520750362391601184808945593998849180004911744337580488125195 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=12771490186019960520750362391601184808945593998849180004911744337580488125195 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/15.xbar_random_large_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_slow_rsp","qual_name":"15.xbar_random_slow_rsp.48807091901069891330681887176058079621836035815310948022642517123934061195773","seed":48807091901069891330681887176058079621836035815310948022642517123934061195773,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/15.xbar_random_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/15.xbar_random_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=958001661 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_slow_rsp.958001661' seed=48807091901069891330681887176058079621836035815310948022642517123934061195773 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=48807091901069891330681887176058079621836035815310948022642517123934061195773 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/15.xbar_random_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device","qual_name":"15.xbar_access_same_device.79615195317041715813599730276730106518494105749190912948614578961437742124297","seed":79615195317041715813599730276730106518494105749190912948614578961437742124297,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/15.xbar_access_same_device/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/15.xbar_access_same_device/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=362597641 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device.362597641' seed=79615195317041715813599730276730106518494105749190912948614578961437742124297 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=79615195317041715813599730276730106518494105749190912948614578961437742124297 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/15.xbar_access_same_device/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"15.xbar_access_same_device_slow_rsp.30157841832559971900702379201806804579953779523512068340405393952937418297916","seed":30157841832559971900702379201806804579953779523512068340405393952937418297916,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/15.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/15.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4273869372 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device_slow_rsp.4273869372' seed=30157841832559971900702379201806804579953779523512068340405393952937418297916 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=30157841832559971900702379201806804579953779523512068340405393952937418297916 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/15.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_same_source","qual_name":"15.xbar_same_source.35651584348990286754557245933525435700084307295978360934317201670342328238483","seed":35651584348990286754557245933525435700084307295978360934317201670342328238483,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/15.xbar_same_source/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/15.xbar_same_source/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2529739155 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_same_source.2529739155' seed=35651584348990286754557245933525435700084307295978360934317201670342328238483 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=35651584348990286754557245933525435700084307295978360934317201670342328238483 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/15.xbar_same_source/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_same_source_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_random","qual_name":"15.xbar_error_random.44497234754310151100746549805128906040178328796617637949528975236555999420692","seed":44497234754310151100746549805128906040178328796617637949528975236555999420692,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/15.xbar_error_random/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/15.xbar_error_random/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1454514452 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_error_random.1454514452' seed=44497234754310151100746549805128906040178328796617637949528975236555999420692 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=44497234754310151100746549805128906040178328796617637949528975236555999420692 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/15.xbar_error_random/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_unmapped_addr","qual_name":"15.xbar_unmapped_addr.71658233490725366501049603996403124714285914643495066512634827946509125919657","seed":71658233490725366501049603996403124714285914643495066512634827946509125919657,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/15.xbar_unmapped_addr/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/15.xbar_unmapped_addr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1226941353 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_unmapped_addr.1226941353' seed=71658233490725366501049603996403124714285914643495066512634827946509125919657 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=71658233490725366501049603996403124714285914643495066512634827946509125919657 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/15.xbar_unmapped_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_and_unmapped_addr","qual_name":"15.xbar_error_and_unmapped_addr.25858934527410164499088641439180791479451424356434886101766921097975311629306","seed":25858934527410164499088641439180791479451424356434886101766921097975311629306,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/15.xbar_error_and_unmapped_addr/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/15.xbar_error_and_unmapped_addr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2921331706 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_error_and_unmapped_addr.2921331706' seed=25858934527410164499088641439180791479451424356434886101766921097975311629306 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=25858934527410164499088641439180791479451424356434886101766921097975311629306 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/15.xbar_error_and_unmapped_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all","qual_name":"15.xbar_stress_all.13264894170772669290753782372388738719232858405160972492169066129511074280197","seed":13264894170772669290753782372388738719232858405160972492169066129511074280197,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/15.xbar_stress_all/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/15.xbar_stress_all/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2302980869 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all.2302980869' seed=13264894170772669290753782372388738719232858405160972492169066129511074280197 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=13264894170772669290753782372388738719232858405160972492169066129511074280197 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/15.xbar_stress_all/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_rand_reset","qual_name":"15.xbar_stress_all_with_rand_reset.70499151907739078770422102098048274291534017513355733183657828574614855029125","seed":70499151907739078770422102098048274291534017513355733183657828574614855029125,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/15.xbar_stress_all_with_rand_reset/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/15.xbar_stress_all_with_rand_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2505773445 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_rand_reset.2505773445' seed=70499151907739078770422102098048274291534017513355733183657828574614855029125 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=70499151907739078770422102098048274291534017513355733183657828574614855029125 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/15.xbar_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"15.xbar_stress_all_with_error.83660966735871014377364403211561489919856394645824525551309420338739153591059","seed":83660966735871014377364403211561489919856394645824525551309420338739153591059,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/15.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/15.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2477382419 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_error.2477382419' seed=83660966735871014377364403211561489919856394645824525551309420338739153591059 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=83660966735871014377364403211561489919856394645824525551309420338739153591059 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/15.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"15.xbar_stress_all_with_reset_error.28366880496512901350326584022045795841282285978498834426733805907571420535733","seed":28366880496512901350326584022045795841282285978498834426733805907571420535733,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/15.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/15.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2783288245 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_reset_error.2783288245' seed=28366880496512901350326584022045795841282285978498834426733805907571420535733 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=28366880496512901350326584022045795841282285978498834426733805907571420535733 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/15.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke","qual_name":"16.xbar_smoke.32492001899983533256789958224824963201756685242732368715897510906863381280810","seed":32492001899983533256789958224824963201756685242732368715897510906863381280810,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/16.xbar_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/16.xbar_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2003466282 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke.2003466282' seed=32492001899983533256789958224824963201756685242732368715897510906863381280810 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=32492001899983533256789958224824963201756685242732368715897510906863381280810 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/16.xbar_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_zero_delays","qual_name":"16.xbar_smoke_zero_delays.44615224262818340053503731777633326736758918290068375131300598523795742616876","seed":44615224262818340053503731777633326736758918290068375131300598523795742616876,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/16.xbar_smoke_zero_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/16.xbar_smoke_zero_delays/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2800446764 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_zero_delays.2800446764' seed=44615224262818340053503731777633326736758918290068375131300598523795742616876 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=44615224262818340053503731777633326736758918290068375131300598523795742616876 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/16.xbar_smoke_zero_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_large_delays","qual_name":"16.xbar_smoke_large_delays.29920758386851080217011134598492081349508280735099554412144995562374005672840","seed":29920758386851080217011134598492081349508280735099554412144995562374005672840,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/16.xbar_smoke_large_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/16.xbar_smoke_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2853849992 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_large_delays.2853849992' seed=29920758386851080217011134598492081349508280735099554412144995562374005672840 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=29920758386851080217011134598492081349508280735099554412144995562374005672840 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/16.xbar_smoke_large_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_slow_rsp","qual_name":"16.xbar_smoke_slow_rsp.73149922351774452654482884930830017699405875448888168992828065507371013138967","seed":73149922351774452654482884930830017699405875448888168992828065507371013138967,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/16.xbar_smoke_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/16.xbar_smoke_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3604507159 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_slow_rsp.3604507159' seed=73149922351774452654482884930830017699405875448888168992828065507371013138967 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=73149922351774452654482884930830017699405875448888168992828065507371013138967 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/16.xbar_smoke_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random","qual_name":"16.xbar_random.17344513184665222386269143611678346914424404339954674709074365660544666621668","seed":17344513184665222386269143611678346914424404339954674709074365660544666621668,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/16.xbar_random/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/16.xbar_random/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=524474084 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random.524474084' seed=17344513184665222386269143611678346914424404339954674709074365660544666621668 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=17344513184665222386269143611678346914424404339954674709074365660544666621668 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/16.xbar_random/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_zero_delays","qual_name":"16.xbar_random_zero_delays.97816566101750544205684949246246801752376509678444417116170600284312423257210","seed":97816566101750544205684949246246801752376509678444417116170600284312423257210,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/16.xbar_random_zero_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/16.xbar_random_zero_delays/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2249850 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_zero_delays.2249850' seed=97816566101750544205684949246246801752376509678444417116170600284312423257210 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=97816566101750544205684949246246801752376509678444417116170600284312423257210 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/16.xbar_random_zero_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_large_delays","qual_name":"16.xbar_random_large_delays.26559440418958571573323454745840070763922227132510094815792310425130990105373","seed":26559440418958571573323454745840070763922227132510094815792310425130990105373,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/16.xbar_random_large_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/16.xbar_random_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4173656861 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_large_delays.4173656861' seed=26559440418958571573323454745840070763922227132510094815792310425130990105373 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=26559440418958571573323454745840070763922227132510094815792310425130990105373 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/16.xbar_random_large_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_slow_rsp","qual_name":"16.xbar_random_slow_rsp.15298247814503948983067152644936327154135400220271831291628344736479632214785","seed":15298247814503948983067152644936327154135400220271831291628344736479632214785,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/16.xbar_random_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/16.xbar_random_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1506331393 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_slow_rsp.1506331393' seed=15298247814503948983067152644936327154135400220271831291628344736479632214785 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=15298247814503948983067152644936327154135400220271831291628344736479632214785 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/16.xbar_random_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device","qual_name":"16.xbar_access_same_device.113888783357542396152978701897197815772630135873545125490900955569081585516970","seed":113888783357542396152978701897197815772630135873545125490900955569081585516970,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/16.xbar_access_same_device/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/16.xbar_access_same_device/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2970632618 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device.2970632618' seed=113888783357542396152978701897197815772630135873545125490900955569081585516970 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=113888783357542396152978701897197815772630135873545125490900955569081585516970 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/16.xbar_access_same_device/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"16.xbar_access_same_device_slow_rsp.53491746402727436786659561589037565595098050606641230283835226682434991550517","seed":53491746402727436786659561589037565595098050606641230283835226682434991550517,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/16.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/16.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1653207093 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device_slow_rsp.1653207093' seed=53491746402727436786659561589037565595098050606641230283835226682434991550517 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=53491746402727436786659561589037565595098050606641230283835226682434991550517 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/16.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_same_source","qual_name":"16.xbar_same_source.54361687462941029610168185077725742226879260093598691976223479121900292789101","seed":54361687462941029610168185077725742226879260093598691976223479121900292789101,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/16.xbar_same_source/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/16.xbar_same_source/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3291206509 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_same_source.3291206509' seed=54361687462941029610168185077725742226879260093598691976223479121900292789101 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=54361687462941029610168185077725742226879260093598691976223479121900292789101 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/16.xbar_same_source/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_same_source_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_random","qual_name":"16.xbar_error_random.60895015918529254623926656191770954625818421343595100090828707435877777473420","seed":60895015918529254623926656191770954625818421343595100090828707435877777473420,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/16.xbar_error_random/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/16.xbar_error_random/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1274740620 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_error_random.1274740620' seed=60895015918529254623926656191770954625818421343595100090828707435877777473420 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=60895015918529254623926656191770954625818421343595100090828707435877777473420 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/16.xbar_error_random/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_unmapped_addr","qual_name":"16.xbar_unmapped_addr.1759306829261726814414466733959652648261000195492960431613709163779899768369","seed":1759306829261726814414466733959652648261000195492960431613709163779899768369,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/16.xbar_unmapped_addr/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/16.xbar_unmapped_addr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1448328753 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_unmapped_addr.1448328753' seed=1759306829261726814414466733959652648261000195492960431613709163779899768369 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=1759306829261726814414466733959652648261000195492960431613709163779899768369 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/16.xbar_unmapped_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_and_unmapped_addr","qual_name":"16.xbar_error_and_unmapped_addr.70696337888428693797598660281599844826955965662514174789672136376849881182973","seed":70696337888428693797598660281599844826955965662514174789672136376849881182973,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/16.xbar_error_and_unmapped_addr/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/16.xbar_error_and_unmapped_addr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=73478909 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_error_and_unmapped_addr.73478909' seed=70696337888428693797598660281599844826955965662514174789672136376849881182973 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=70696337888428693797598660281599844826955965662514174789672136376849881182973 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/16.xbar_error_and_unmapped_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all","qual_name":"16.xbar_stress_all.79917927106197881003467428349227569504989120875898132925562916248273199068122","seed":79917927106197881003467428349227569504989120875898132925562916248273199068122,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/16.xbar_stress_all/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/16.xbar_stress_all/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2814407642 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all.2814407642' seed=79917927106197881003467428349227569504989120875898132925562916248273199068122 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=79917927106197881003467428349227569504989120875898132925562916248273199068122 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/16.xbar_stress_all/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_rand_reset","qual_name":"16.xbar_stress_all_with_rand_reset.46857948302067012977362014589645302364578794885076039664714168805889495403059","seed":46857948302067012977362014589645302364578794885076039664714168805889495403059,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/16.xbar_stress_all_with_rand_reset/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/16.xbar_stress_all_with_rand_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3662023219 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_rand_reset.3662023219' seed=46857948302067012977362014589645302364578794885076039664714168805889495403059 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=46857948302067012977362014589645302364578794885076039664714168805889495403059 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/16.xbar_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"16.xbar_stress_all_with_error.23224533839585550328075392998456054380181192357251314173683875091110743450927","seed":23224533839585550328075392998456054380181192357251314173683875091110743450927,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/16.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/16.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3454215471 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_error.3454215471' seed=23224533839585550328075392998456054380181192357251314173683875091110743450927 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=23224533839585550328075392998456054380181192357251314173683875091110743450927 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/16.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"16.xbar_stress_all_with_reset_error.29014883368195189378887939052256182512209666658629497164958731266720275203740","seed":29014883368195189378887939052256182512209666658629497164958731266720275203740,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/16.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/16.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1237943964 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_reset_error.1237943964' seed=29014883368195189378887939052256182512209666658629497164958731266720275203740 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=29014883368195189378887939052256182512209666658629497164958731266720275203740 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/16.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke","qual_name":"17.xbar_smoke.62252281320882733238726035379726450369099927920562995414906284866936867053609","seed":62252281320882733238726035379726450369099927920562995414906284866936867053609,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/17.xbar_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/17.xbar_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3319717929 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke.3319717929' seed=62252281320882733238726035379726450369099927920562995414906284866936867053609 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=62252281320882733238726035379726450369099927920562995414906284866936867053609 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/17.xbar_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_zero_delays","qual_name":"17.xbar_smoke_zero_delays.73444833414080776344668122790156495576734504626251705004847914967322345665864","seed":73444833414080776344668122790156495576734504626251705004847914967322345665864,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/17.xbar_smoke_zero_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/17.xbar_smoke_zero_delays/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1021113672 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_zero_delays.1021113672' seed=73444833414080776344668122790156495576734504626251705004847914967322345665864 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=73444833414080776344668122790156495576734504626251705004847914967322345665864 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/17.xbar_smoke_zero_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_large_delays","qual_name":"17.xbar_smoke_large_delays.53569126424036519372349462575516104627433550596400086065005979427590819445061","seed":53569126424036519372349462575516104627433550596400086065005979427590819445061,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/17.xbar_smoke_large_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/17.xbar_smoke_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3281418565 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_large_delays.3281418565' seed=53569126424036519372349462575516104627433550596400086065005979427590819445061 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=53569126424036519372349462575516104627433550596400086065005979427590819445061 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/17.xbar_smoke_large_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_slow_rsp","qual_name":"17.xbar_smoke_slow_rsp.83068211352685072980698502294773409400492675604267602452141302124422265825962","seed":83068211352685072980698502294773409400492675604267602452141302124422265825962,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/17.xbar_smoke_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/17.xbar_smoke_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2310269610 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_slow_rsp.2310269610' seed=83068211352685072980698502294773409400492675604267602452141302124422265825962 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=83068211352685072980698502294773409400492675604267602452141302124422265825962 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/17.xbar_smoke_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random","qual_name":"17.xbar_random.32020297179079155180566192193104552232702755701256107399425521680801994840054","seed":32020297179079155180566192193104552232702755701256107399425521680801994840054,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/17.xbar_random/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/17.xbar_random/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1416566774 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random.1416566774' seed=32020297179079155180566192193104552232702755701256107399425521680801994840054 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=32020297179079155180566192193104552232702755701256107399425521680801994840054 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/17.xbar_random/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_zero_delays","qual_name":"17.xbar_random_zero_delays.110530446877611352021269744117502539218606147317072487706754458632776780331055","seed":110530446877611352021269744117502539218606147317072487706754458632776780331055,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/17.xbar_random_zero_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/17.xbar_random_zero_delays/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1595914287 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_zero_delays.1595914287' seed=110530446877611352021269744117502539218606147317072487706754458632776780331055 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=110530446877611352021269744117502539218606147317072487706754458632776780331055 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/17.xbar_random_zero_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_large_delays","qual_name":"17.xbar_random_large_delays.3259868454467487682593513745495806578755637848656855338699535488514634402090","seed":3259868454467487682593513745495806578755637848656855338699535488514634402090,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/17.xbar_random_large_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/17.xbar_random_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3160525098 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_large_delays.3160525098' seed=3259868454467487682593513745495806578755637848656855338699535488514634402090 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=3259868454467487682593513745495806578755637848656855338699535488514634402090 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/17.xbar_random_large_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_slow_rsp","qual_name":"17.xbar_random_slow_rsp.19217635878913237125366174911590356900395311090227334619981035045718361802746","seed":19217635878913237125366174911590356900395311090227334619981035045718361802746,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/17.xbar_random_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/17.xbar_random_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=787384314 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_slow_rsp.787384314' seed=19217635878913237125366174911590356900395311090227334619981035045718361802746 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=19217635878913237125366174911590356900395311090227334619981035045718361802746 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/17.xbar_random_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device","qual_name":"17.xbar_access_same_device.100395494942730942405536491959726508228617448941588307866428325508446224969483","seed":100395494942730942405536491959726508228617448941588307866428325508446224969483,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/17.xbar_access_same_device/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/17.xbar_access_same_device/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=873525003 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device.873525003' seed=100395494942730942405536491959726508228617448941588307866428325508446224969483 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=100395494942730942405536491959726508228617448941588307866428325508446224969483 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/17.xbar_access_same_device/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"17.xbar_access_same_device_slow_rsp.25926652369421785035674833529368789913022386327073178209132906386937491893874","seed":25926652369421785035674833529368789913022386327073178209132906386937491893874,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/17.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/17.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4168232562 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device_slow_rsp.4168232562' seed=25926652369421785035674833529368789913022386327073178209132906386937491893874 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=25926652369421785035674833529368789913022386327073178209132906386937491893874 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/17.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_same_source","qual_name":"17.xbar_same_source.105157588465642485149856594207672979030306342647464228524399837898433058488145","seed":105157588465642485149856594207672979030306342647464228524399837898433058488145,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/17.xbar_same_source/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/17.xbar_same_source/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3031088977 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_same_source.3031088977' seed=105157588465642485149856594207672979030306342647464228524399837898433058488145 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=105157588465642485149856594207672979030306342647464228524399837898433058488145 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/17.xbar_same_source/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_same_source_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_random","qual_name":"17.xbar_error_random.3872574812511132252876888516800814680721999396193729754949930455844209631967","seed":3872574812511132252876888516800814680721999396193729754949930455844209631967,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/17.xbar_error_random/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/17.xbar_error_random/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3007390431 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_error_random.3007390431' seed=3872574812511132252876888516800814680721999396193729754949930455844209631967 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=3872574812511132252876888516800814680721999396193729754949930455844209631967 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/17.xbar_error_random/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_unmapped_addr","qual_name":"17.xbar_unmapped_addr.39258362694286129543048169971177890052168649743549628268780143689970756595148","seed":39258362694286129543048169971177890052168649743549628268780143689970756595148,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/17.xbar_unmapped_addr/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/17.xbar_unmapped_addr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2968235468 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_unmapped_addr.2968235468' seed=39258362694286129543048169971177890052168649743549628268780143689970756595148 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=39258362694286129543048169971177890052168649743549628268780143689970756595148 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/17.xbar_unmapped_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_and_unmapped_addr","qual_name":"17.xbar_error_and_unmapped_addr.111097746117832638022865785007615395717683545437231901583687028988261583024928","seed":111097746117832638022865785007615395717683545437231901583687028988261583024928,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/17.xbar_error_and_unmapped_addr/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/17.xbar_error_and_unmapped_addr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=185332512 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_error_and_unmapped_addr.185332512' seed=111097746117832638022865785007615395717683545437231901583687028988261583024928 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=111097746117832638022865785007615395717683545437231901583687028988261583024928 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/17.xbar_error_and_unmapped_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all","qual_name":"17.xbar_stress_all.18188505666287074770655850760813479749824148352666567811079294681671396786857","seed":18188505666287074770655850760813479749824148352666567811079294681671396786857,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/17.xbar_stress_all/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/17.xbar_stress_all/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1294500521 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all.1294500521' seed=18188505666287074770655850760813479749824148352666567811079294681671396786857 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=18188505666287074770655850760813479749824148352666567811079294681671396786857 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/17.xbar_stress_all/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_rand_reset","qual_name":"17.xbar_stress_all_with_rand_reset.56449045621061542367918508654219570241578851320901262681148629219191736354074","seed":56449045621061542367918508654219570241578851320901262681148629219191736354074,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/17.xbar_stress_all_with_rand_reset/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/17.xbar_stress_all_with_rand_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3032335642 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_rand_reset.3032335642' seed=56449045621061542367918508654219570241578851320901262681148629219191736354074 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=56449045621061542367918508654219570241578851320901262681148629219191736354074 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/17.xbar_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"17.xbar_stress_all_with_error.15516016499795009122263573764189368645492805442725204336044353682783966027127","seed":15516016499795009122263573764189368645492805442725204336044353682783966027127,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/17.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/17.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=145186167 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_error.145186167' seed=15516016499795009122263573764189368645492805442725204336044353682783966027127 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=15516016499795009122263573764189368645492805442725204336044353682783966027127 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/17.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"17.xbar_stress_all_with_reset_error.28883639180180207646189503432666230033868961477580196550289395273720465867526","seed":28883639180180207646189503432666230033868961477580196550289395273720465867526,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/17.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/17.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=688800518 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_reset_error.688800518' seed=28883639180180207646189503432666230033868961477580196550289395273720465867526 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=28883639180180207646189503432666230033868961477580196550289395273720465867526 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/17.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke","qual_name":"18.xbar_smoke.98165918144600206154998747836552627920154953721523074304134412134726513435961","seed":98165918144600206154998747836552627920154953721523074304134412134726513435961,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/18.xbar_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/18.xbar_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1674028345 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke.1674028345' seed=98165918144600206154998747836552627920154953721523074304134412134726513435961 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=98165918144600206154998747836552627920154953721523074304134412134726513435961 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/18.xbar_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_zero_delays","qual_name":"18.xbar_smoke_zero_delays.38243332909250220896266533436211385200067340212729900464202762513600869749586","seed":38243332909250220896266533436211385200067340212729900464202762513600869749586,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/18.xbar_smoke_zero_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/18.xbar_smoke_zero_delays/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3206992722 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_zero_delays.3206992722' seed=38243332909250220896266533436211385200067340212729900464202762513600869749586 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=38243332909250220896266533436211385200067340212729900464202762513600869749586 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/18.xbar_smoke_zero_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_large_delays","qual_name":"18.xbar_smoke_large_delays.21420230191364210857857118820654196210572388322506706651367105242413249442872","seed":21420230191364210857857118820654196210572388322506706651367105242413249442872,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/18.xbar_smoke_large_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/18.xbar_smoke_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4232426552 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_large_delays.4232426552' seed=21420230191364210857857118820654196210572388322506706651367105242413249442872 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=21420230191364210857857118820654196210572388322506706651367105242413249442872 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/18.xbar_smoke_large_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_slow_rsp","qual_name":"18.xbar_smoke_slow_rsp.41958490892823183921949607194384644849204327510335991116727480929612888893956","seed":41958490892823183921949607194384644849204327510335991116727480929612888893956,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/18.xbar_smoke_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/18.xbar_smoke_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3870386692 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_slow_rsp.3870386692' seed=41958490892823183921949607194384644849204327510335991116727480929612888893956 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=41958490892823183921949607194384644849204327510335991116727480929612888893956 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/18.xbar_smoke_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random","qual_name":"18.xbar_random.104328581557853061751166344451969565473997717919088330985964051804853164229795","seed":104328581557853061751166344451969565473997717919088330985964051804853164229795,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/18.xbar_random/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/18.xbar_random/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1118749859 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random.1118749859' seed=104328581557853061751166344451969565473997717919088330985964051804853164229795 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=104328581557853061751166344451969565473997717919088330985964051804853164229795 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/18.xbar_random/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_zero_delays","qual_name":"18.xbar_random_zero_delays.97397895551243256968008000272167323719835081220242686012019888738422424759471","seed":97397895551243256968008000272167323719835081220242686012019888738422424759471,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/18.xbar_random_zero_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/18.xbar_random_zero_delays/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2294967471 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_zero_delays.2294967471' seed=97397895551243256968008000272167323719835081220242686012019888738422424759471 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=97397895551243256968008000272167323719835081220242686012019888738422424759471 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/18.xbar_random_zero_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_large_delays","qual_name":"18.xbar_random_large_delays.98254975837837047503643949433305768366450319339381431743231551702190629779109","seed":98254975837837047503643949433305768366450319339381431743231551702190629779109,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/18.xbar_random_large_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/18.xbar_random_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1793521317 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_large_delays.1793521317' seed=98254975837837047503643949433305768366450319339381431743231551702190629779109 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=98254975837837047503643949433305768366450319339381431743231551702190629779109 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/18.xbar_random_large_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_slow_rsp","qual_name":"18.xbar_random_slow_rsp.67876066750027472054945831255071183797440036296146909954649574404568994084745","seed":67876066750027472054945831255071183797440036296146909954649574404568994084745,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/18.xbar_random_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/18.xbar_random_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2114254729 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_slow_rsp.2114254729' seed=67876066750027472054945831255071183797440036296146909954649574404568994084745 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=67876066750027472054945831255071183797440036296146909954649574404568994084745 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/18.xbar_random_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device","qual_name":"18.xbar_access_same_device.46372340464538975515459221699017908849919782763542309481452556571561906618679","seed":46372340464538975515459221699017908849919782763542309481452556571561906618679,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/18.xbar_access_same_device/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/18.xbar_access_same_device/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=464994615 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device.464994615' seed=46372340464538975515459221699017908849919782763542309481452556571561906618679 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=46372340464538975515459221699017908849919782763542309481452556571561906618679 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/18.xbar_access_same_device/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"18.xbar_access_same_device_slow_rsp.109841206726239254487772422244189594874043201521506202604474787356759269581371","seed":109841206726239254487772422244189594874043201521506202604474787356759269581371,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/18.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/18.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=376185403 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device_slow_rsp.376185403' seed=109841206726239254487772422244189594874043201521506202604474787356759269581371 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=109841206726239254487772422244189594874043201521506202604474787356759269581371 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/18.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_same_source","qual_name":"18.xbar_same_source.80083304160393768848086589644671533189650241205312378953469483552459448926632","seed":80083304160393768848086589644671533189650241205312378953469483552459448926632,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/18.xbar_same_source/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/18.xbar_same_source/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2240561576 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_same_source.2240561576' seed=80083304160393768848086589644671533189650241205312378953469483552459448926632 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=80083304160393768848086589644671533189650241205312378953469483552459448926632 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/18.xbar_same_source/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_same_source_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_random","qual_name":"18.xbar_error_random.99377828878897971651838544941749705470698423419590026419340845248032812664536","seed":99377828878897971651838544941749705470698423419590026419340845248032812664536,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/18.xbar_error_random/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/18.xbar_error_random/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=26576600 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_error_random.26576600' seed=99377828878897971651838544941749705470698423419590026419340845248032812664536 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=99377828878897971651838544941749705470698423419590026419340845248032812664536 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/18.xbar_error_random/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_unmapped_addr","qual_name":"18.xbar_unmapped_addr.24206594958847934446660207308552818571789021106003406011674681852983302051850","seed":24206594958847934446660207308552818571789021106003406011674681852983302051850,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/18.xbar_unmapped_addr/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/18.xbar_unmapped_addr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3471464458 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_unmapped_addr.3471464458' seed=24206594958847934446660207308552818571789021106003406011674681852983302051850 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=24206594958847934446660207308552818571789021106003406011674681852983302051850 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/18.xbar_unmapped_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_and_unmapped_addr","qual_name":"18.xbar_error_and_unmapped_addr.29664849650595193125184949361314104823360701139555538163948459304775623473986","seed":29664849650595193125184949361314104823360701139555538163948459304775623473986,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/18.xbar_error_and_unmapped_addr/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/18.xbar_error_and_unmapped_addr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=987593538 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_error_and_unmapped_addr.987593538' seed=29664849650595193125184949361314104823360701139555538163948459304775623473986 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=29664849650595193125184949361314104823360701139555538163948459304775623473986 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/18.xbar_error_and_unmapped_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all","qual_name":"18.xbar_stress_all.98362531793006084058241409548478809833011094068956736408205551155097921287431","seed":98362531793006084058241409548478809833011094068956736408205551155097921287431,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/18.xbar_stress_all/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/18.xbar_stress_all/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1305638151 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all.1305638151' seed=98362531793006084058241409548478809833011094068956736408205551155097921287431 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=98362531793006084058241409548478809833011094068956736408205551155097921287431 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/18.xbar_stress_all/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_rand_reset","qual_name":"18.xbar_stress_all_with_rand_reset.35387654745190026323222463231155835423131944529885658646676263862087047621959","seed":35387654745190026323222463231155835423131944529885658646676263862087047621959,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/18.xbar_stress_all_with_rand_reset/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/18.xbar_stress_all_with_rand_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1979362631 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_rand_reset.1979362631' seed=35387654745190026323222463231155835423131944529885658646676263862087047621959 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=35387654745190026323222463231155835423131944529885658646676263862087047621959 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/18.xbar_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"18.xbar_stress_all_with_error.28640083245425079251010276523051192330674947927190756004600194946655312380157","seed":28640083245425079251010276523051192330674947927190756004600194946655312380157,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/18.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/18.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1827373309 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_error.1827373309' seed=28640083245425079251010276523051192330674947927190756004600194946655312380157 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=28640083245425079251010276523051192330674947927190756004600194946655312380157 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/18.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"18.xbar_stress_all_with_reset_error.62691203099176844200526994596972659828888933940269235672068454016093707330042","seed":62691203099176844200526994596972659828888933940269235672068454016093707330042,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/18.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/18.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3243008506 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_reset_error.3243008506' seed=62691203099176844200526994596972659828888933940269235672068454016093707330042 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=62691203099176844200526994596972659828888933940269235672068454016093707330042 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/18.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke","qual_name":"19.xbar_smoke.10835900508404553342853917508920656932101026230908697720107904476798281934291","seed":10835900508404553342853917508920656932101026230908697720107904476798281934291,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/19.xbar_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/19.xbar_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4009321939 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke.4009321939' seed=10835900508404553342853917508920656932101026230908697720107904476798281934291 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=10835900508404553342853917508920656932101026230908697720107904476798281934291 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/19.xbar_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_zero_delays","qual_name":"19.xbar_smoke_zero_delays.4938081903176193672695593521655502665372606154551866038983797795164132058025","seed":4938081903176193672695593521655502665372606154551866038983797795164132058025,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/19.xbar_smoke_zero_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/19.xbar_smoke_zero_delays/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3629753257 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_zero_delays.3629753257' seed=4938081903176193672695593521655502665372606154551866038983797795164132058025 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=4938081903176193672695593521655502665372606154551866038983797795164132058025 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/19.xbar_smoke_zero_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_large_delays","qual_name":"19.xbar_smoke_large_delays.76518694629048808294304316059937184013578554754132423484161527981518792093912","seed":76518694629048808294304316059937184013578554754132423484161527981518792093912,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/19.xbar_smoke_large_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/19.xbar_smoke_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=787935448 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_large_delays.787935448' seed=76518694629048808294304316059937184013578554754132423484161527981518792093912 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=76518694629048808294304316059937184013578554754132423484161527981518792093912 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/19.xbar_smoke_large_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_slow_rsp","qual_name":"19.xbar_smoke_slow_rsp.16717490342124334763602860538708432847355889344843886521839137696125754295213","seed":16717490342124334763602860538708432847355889344843886521839137696125754295213,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/19.xbar_smoke_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/19.xbar_smoke_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1894007725 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_slow_rsp.1894007725' seed=16717490342124334763602860538708432847355889344843886521839137696125754295213 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=16717490342124334763602860538708432847355889344843886521839137696125754295213 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/19.xbar_smoke_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random","qual_name":"19.xbar_random.98002625830572685832647389231039119064560559375828096472734205263439883100266","seed":98002625830572685832647389231039119064560559375828096472734205263439883100266,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/19.xbar_random/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/19.xbar_random/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3142803562 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random.3142803562' seed=98002625830572685832647389231039119064560559375828096472734205263439883100266 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=98002625830572685832647389231039119064560559375828096472734205263439883100266 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/19.xbar_random/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_zero_delays","qual_name":"19.xbar_random_zero_delays.107270039696226009206620382981126809022669054567478152255734762140604680927094","seed":107270039696226009206620382981126809022669054567478152255734762140604680927094,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/19.xbar_random_zero_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/19.xbar_random_zero_delays/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3305142134 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_zero_delays.3305142134' seed=107270039696226009206620382981126809022669054567478152255734762140604680927094 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=107270039696226009206620382981126809022669054567478152255734762140604680927094 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/19.xbar_random_zero_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_large_delays","qual_name":"19.xbar_random_large_delays.35239173379082272304138976300837958548453622043289306671019417364698286212136","seed":35239173379082272304138976300837958548453622043289306671019417364698286212136,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/19.xbar_random_large_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/19.xbar_random_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1659847720 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_large_delays.1659847720' seed=35239173379082272304138976300837958548453622043289306671019417364698286212136 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=35239173379082272304138976300837958548453622043289306671019417364698286212136 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/19.xbar_random_large_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_slow_rsp","qual_name":"19.xbar_random_slow_rsp.7350010224785588486965755229253855418357927741420729634259343217247727211184","seed":7350010224785588486965755229253855418357927741420729634259343217247727211184,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/19.xbar_random_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/19.xbar_random_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3204272816 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_slow_rsp.3204272816' seed=7350010224785588486965755229253855418357927741420729634259343217247727211184 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=7350010224785588486965755229253855418357927741420729634259343217247727211184 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/19.xbar_random_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device","qual_name":"19.xbar_access_same_device.30246068914339164864876651907982047405769437882813773011903051839874233451936","seed":30246068914339164864876651907982047405769437882813773011903051839874233451936,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/19.xbar_access_same_device/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/19.xbar_access_same_device/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3095315872 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device.3095315872' seed=30246068914339164864876651907982047405769437882813773011903051839874233451936 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=30246068914339164864876651907982047405769437882813773011903051839874233451936 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/19.xbar_access_same_device/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"19.xbar_access_same_device_slow_rsp.38539555805140820402481833377146585948457065940855987069032155371423163466784","seed":38539555805140820402481833377146585948457065940855987069032155371423163466784,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/19.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/19.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4136092704 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device_slow_rsp.4136092704' seed=38539555805140820402481833377146585948457065940855987069032155371423163466784 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=38539555805140820402481833377146585948457065940855987069032155371423163466784 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/19.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_same_source","qual_name":"19.xbar_same_source.77705352301692439699983712612231106705659741761690804479640672689624912181561","seed":77705352301692439699983712612231106705659741761690804479640672689624912181561,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/19.xbar_same_source/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/19.xbar_same_source/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2489006393 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_same_source.2489006393' seed=77705352301692439699983712612231106705659741761690804479640672689624912181561 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=77705352301692439699983712612231106705659741761690804479640672689624912181561 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/19.xbar_same_source/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_same_source_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_random","qual_name":"19.xbar_error_random.40482802495858174328961482767544388590130834953654640039111223809964494277553","seed":40482802495858174328961482767544388590130834953654640039111223809964494277553,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/19.xbar_error_random/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/19.xbar_error_random/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=94096305 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_error_random.94096305' seed=40482802495858174328961482767544388590130834953654640039111223809964494277553 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=40482802495858174328961482767544388590130834953654640039111223809964494277553 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/19.xbar_error_random/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_unmapped_addr","qual_name":"19.xbar_unmapped_addr.89876571400009290519240157472018590206430685689642615795857488881134773258999","seed":89876571400009290519240157472018590206430685689642615795857488881134773258999,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/19.xbar_unmapped_addr/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/19.xbar_unmapped_addr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3610299127 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_unmapped_addr.3610299127' seed=89876571400009290519240157472018590206430685689642615795857488881134773258999 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=89876571400009290519240157472018590206430685689642615795857488881134773258999 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/19.xbar_unmapped_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_and_unmapped_addr","qual_name":"19.xbar_error_and_unmapped_addr.30785478324394742049171144743017092978880777073833600124892302391450122756008","seed":30785478324394742049171144743017092978880777073833600124892302391450122756008,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/19.xbar_error_and_unmapped_addr/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/19.xbar_error_and_unmapped_addr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2375983016 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_error_and_unmapped_addr.2375983016' seed=30785478324394742049171144743017092978880777073833600124892302391450122756008 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=30785478324394742049171144743017092978880777073833600124892302391450122756008 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/19.xbar_error_and_unmapped_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all","qual_name":"19.xbar_stress_all.105266925683314715054166664110864135068477989806271852402566116220518969165256","seed":105266925683314715054166664110864135068477989806271852402566116220518969165256,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/19.xbar_stress_all/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/19.xbar_stress_all/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3608987080 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all.3608987080' seed=105266925683314715054166664110864135068477989806271852402566116220518969165256 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=105266925683314715054166664110864135068477989806271852402566116220518969165256 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/19.xbar_stress_all/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_rand_reset","qual_name":"19.xbar_stress_all_with_rand_reset.109426283693867231911001027734039782130119012280786605077411049556471642709011","seed":109426283693867231911001027734039782130119012280786605077411049556471642709011,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/19.xbar_stress_all_with_rand_reset/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/19.xbar_stress_all_with_rand_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2973883411 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_rand_reset.2973883411' seed=109426283693867231911001027734039782130119012280786605077411049556471642709011 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=109426283693867231911001027734039782130119012280786605077411049556471642709011 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/19.xbar_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"19.xbar_stress_all_with_error.67418138643351635820206278989906430377398308592943411473079829480194640794724","seed":67418138643351635820206278989906430377398308592943411473079829480194640794724,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/19.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/19.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2923779172 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_error.2923779172' seed=67418138643351635820206278989906430377398308592943411473079829480194640794724 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=67418138643351635820206278989906430377398308592943411473079829480194640794724 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/19.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"19.xbar_stress_all_with_reset_error.48633924210798065996187378656706816365855691036945413526032328139727645191355","seed":48633924210798065996187378656706816365855691036945413526032328139727645191355,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/19.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/19.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2101095611 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_reset_error.2101095611' seed=48633924210798065996187378656706816365855691036945413526032328139727645191355 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=48633924210798065996187378656706816365855691036945413526032328139727645191355 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/19.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"20.xbar_access_same_device_slow_rsp.98357634288558063885741893139930091074358722835782805655329065718912884100563","seed":98357634288558063885741893139930091074358722835782805655329065718912884100563,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/20.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/20.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=962547155 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device_slow_rsp.962547155' seed=98357634288558063885741893139930091074358722835782805655329065718912884100563 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=98357634288558063885741893139930091074358722835782805655329065718912884100563 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/20.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"20.xbar_stress_all_with_error.31833183562755046117708124446721226451049266412915447684381258127458102282659","seed":31833183562755046117708124446721226451049266412915447684381258127458102282659,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/20.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/20.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2169112995 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_error.2169112995' seed=31833183562755046117708124446721226451049266412915447684381258127458102282659 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=31833183562755046117708124446721226451049266412915447684381258127458102282659 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/20.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"20.xbar_stress_all_with_reset_error.94427451667352750017136848502586978349402244507239655326110612547480655131057","seed":94427451667352750017136848502586978349402244507239655326110612547480655131057,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/20.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/20.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3829035441 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_reset_error.3829035441' seed=94427451667352750017136848502586978349402244507239655326110612547480655131057 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=94427451667352750017136848502586978349402244507239655326110612547480655131057 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/20.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"21.xbar_access_same_device_slow_rsp.106555950278196218084891945137904764334274151532974707005455287133486021467520","seed":106555950278196218084891945137904764334274151532974707005455287133486021467520,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/21.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/21.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2353651072 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device_slow_rsp.2353651072' seed=106555950278196218084891945137904764334274151532974707005455287133486021467520 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=106555950278196218084891945137904764334274151532974707005455287133486021467520 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/21.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"21.xbar_stress_all_with_error.98360885581635569923454680974222075892514297147615621751704050123815637241451","seed":98360885581635569923454680974222075892514297147615621751704050123815637241451,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/21.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/21.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1362644587 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_error.1362644587' seed=98360885581635569923454680974222075892514297147615621751704050123815637241451 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=98360885581635569923454680974222075892514297147615621751704050123815637241451 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/21.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"21.xbar_stress_all_with_reset_error.11250137786224630993795622345022792482991488577057714472759630899248964412971","seed":11250137786224630993795622345022792482991488577057714472759630899248964412971,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/21.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/21.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3927025195 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_reset_error.3927025195' seed=11250137786224630993795622345022792482991488577057714472759630899248964412971 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=11250137786224630993795622345022792482991488577057714472759630899248964412971 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/21.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"22.xbar_access_same_device_slow_rsp.90336278443659091533805652813028538592727648637646493728367053606116579631331","seed":90336278443659091533805652813028538592727648637646493728367053606116579631331,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/22.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/22.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1826644195 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device_slow_rsp.1826644195' seed=90336278443659091533805652813028538592727648637646493728367053606116579631331 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=90336278443659091533805652813028538592727648637646493728367053606116579631331 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/22.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"22.xbar_stress_all_with_error.97511472226106320535265452373021594695816031036508225297101532427819059374341","seed":97511472226106320535265452373021594695816031036508225297101532427819059374341,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/22.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/22.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=44427525 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_error.44427525' seed=97511472226106320535265452373021594695816031036508225297101532427819059374341 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=97511472226106320535265452373021594695816031036508225297101532427819059374341 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/22.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"22.xbar_stress_all_with_reset_error.40535746537121923753129445019411195160319338144497084476367697704823465075259","seed":40535746537121923753129445019411195160319338144497084476367697704823465075259,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/22.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/22.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1183998523 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_reset_error.1183998523' seed=40535746537121923753129445019411195160319338144497084476367697704823465075259 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=40535746537121923753129445019411195160319338144497084476367697704823465075259 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/22.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"23.xbar_access_same_device_slow_rsp.57092979003076610419146660205870370510816423771833203832411754852837758064764","seed":57092979003076610419146660205870370510816423771833203832411754852837758064764,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/23.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/23.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2899302524 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device_slow_rsp.2899302524' seed=57092979003076610419146660205870370510816423771833203832411754852837758064764 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=57092979003076610419146660205870370510816423771833203832411754852837758064764 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/23.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"23.xbar_stress_all_with_error.87358976277895087873816874378781121405366476655524338157974444681708568587726","seed":87358976277895087873816874378781121405366476655524338157974444681708568587726,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/23.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/23.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=99626446 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_error.99626446' seed=87358976277895087873816874378781121405366476655524338157974444681708568587726 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=87358976277895087873816874378781121405366476655524338157974444681708568587726 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/23.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"23.xbar_stress_all_with_reset_error.33217259160945351454516391141084478467705611892780064482839671955081101880486","seed":33217259160945351454516391141084478467705611892780064482839671955081101880486,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/23.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/23.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3960777894 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_reset_error.3960777894' seed=33217259160945351454516391141084478467705611892780064482839671955081101880486 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=33217259160945351454516391141084478467705611892780064482839671955081101880486 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/23.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"24.xbar_access_same_device_slow_rsp.79688297598147405977898145815505756253566802821475215903391640170566717029406","seed":79688297598147405977898145815505756253566802821475215903391640170566717029406,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/24.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/24.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4159716382 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device_slow_rsp.4159716382' seed=79688297598147405977898145815505756253566802821475215903391640170566717029406 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=79688297598147405977898145815505756253566802821475215903391640170566717029406 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/24.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"24.xbar_stress_all_with_error.72020009170852728686648181610921869258397957450287772416977781069519210962031","seed":72020009170852728686648181610921869258397957450287772416977781069519210962031,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/24.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/24.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2585287791 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_error.2585287791' seed=72020009170852728686648181610921869258397957450287772416977781069519210962031 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=72020009170852728686648181610921869258397957450287772416977781069519210962031 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/24.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"24.xbar_stress_all_with_reset_error.32308578667005475685217148983209367927408025885859790269678071565577457747923","seed":32308578667005475685217148983209367927408025885859790269678071565577457747923,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/24.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/24.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1165739987 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_reset_error.1165739987' seed=32308578667005475685217148983209367927408025885859790269678071565577457747923 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=32308578667005475685217148983209367927408025885859790269678071565577457747923 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/24.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"25.xbar_access_same_device_slow_rsp.39387800925710041529224951199345892581797830304114196179823403112633808665248","seed":39387800925710041529224951199345892581797830304114196179823403112633808665248,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/25.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/25.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1593784992 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device_slow_rsp.1593784992' seed=39387800925710041529224951199345892581797830304114196179823403112633808665248 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=39387800925710041529224951199345892581797830304114196179823403112633808665248 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/25.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"25.xbar_stress_all_with_error.14602430187086155456513940536017449485838280640153178570731731902005999467825","seed":14602430187086155456513940536017449485838280640153178570731731902005999467825,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/25.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/25.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1791655217 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_error.1791655217' seed=14602430187086155456513940536017449485838280640153178570731731902005999467825 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=14602430187086155456513940536017449485838280640153178570731731902005999467825 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/25.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"25.xbar_stress_all_with_reset_error.45726420515310982195287586228447374215074773953969936889566430154669551740025","seed":45726420515310982195287586228447374215074773953969936889566430154669551740025,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/25.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/25.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3587400825 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_reset_error.3587400825' seed=45726420515310982195287586228447374215074773953969936889566430154669551740025 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=45726420515310982195287586228447374215074773953969936889566430154669551740025 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/25.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"26.xbar_access_same_device_slow_rsp.85885954797893868283359021002529068582687405905246815714278706234918921460664","seed":85885954797893868283359021002529068582687405905246815714278706234918921460664,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/26.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/26.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=774003640 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device_slow_rsp.774003640' seed=85885954797893868283359021002529068582687405905246815714278706234918921460664 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=85885954797893868283359021002529068582687405905246815714278706234918921460664 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/26.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"26.xbar_stress_all_with_error.61984550227813475882802161031326660244215744749715686241614651941089242325865","seed":61984550227813475882802161031326660244215744749715686241614651941089242325865,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/26.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/26.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=591209321 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_error.591209321' seed=61984550227813475882802161031326660244215744749715686241614651941089242325865 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=61984550227813475882802161031326660244215744749715686241614651941089242325865 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/26.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"26.xbar_stress_all_with_reset_error.1972929058767002997584101966473745397607725553468292953849569139506781897177","seed":1972929058767002997584101966473745397607725553468292953849569139506781897177,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/26.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/26.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2577678809 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_reset_error.2577678809' seed=1972929058767002997584101966473745397607725553468292953849569139506781897177 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=1972929058767002997584101966473745397607725553468292953849569139506781897177 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/26.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"27.xbar_access_same_device_slow_rsp.73007940766996391369700443374843867018984688169668629035450759859460469340784","seed":73007940766996391369700443374843867018984688169668629035450759859460469340784,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/27.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/27.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=656849520 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device_slow_rsp.656849520' seed=73007940766996391369700443374843867018984688169668629035450759859460469340784 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=73007940766996391369700443374843867018984688169668629035450759859460469340784 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/27.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"27.xbar_stress_all_with_error.25540265881060435496011791187583168333643376195788022119031513029760487322215","seed":25540265881060435496011791187583168333643376195788022119031513029760487322215,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/27.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/27.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3498635879 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_error.3498635879' seed=25540265881060435496011791187583168333643376195788022119031513029760487322215 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=25540265881060435496011791187583168333643376195788022119031513029760487322215 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/27.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"27.xbar_stress_all_with_reset_error.87011078857281751401771230794436149909324370459669923261928748930572451347547","seed":87011078857281751401771230794436149909324370459669923261928748930572451347547,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/27.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/27.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2198109275 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_reset_error.2198109275' seed=87011078857281751401771230794436149909324370459669923261928748930572451347547 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=87011078857281751401771230794436149909324370459669923261928748930572451347547 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/27.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"28.xbar_access_same_device_slow_rsp.28421171962552853253970552112195013061368470610770912047609516745251921818792","seed":28421171962552853253970552112195013061368470610770912047609516745251921818792,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/28.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/28.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2423223464 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device_slow_rsp.2423223464' seed=28421171962552853253970552112195013061368470610770912047609516745251921818792 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=28421171962552853253970552112195013061368470610770912047609516745251921818792 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/28.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"28.xbar_stress_all_with_error.50078595367169071002274458316741738805386850929863233788289020935299976031403","seed":50078595367169071002274458316741738805386850929863233788289020935299976031403,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/28.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/28.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2075815083 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_error.2075815083' seed=50078595367169071002274458316741738805386850929863233788289020935299976031403 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=50078595367169071002274458316741738805386850929863233788289020935299976031403 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/28.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"28.xbar_stress_all_with_reset_error.83326781836950929334657533191315496803128582024343574898241463663463424353656","seed":83326781836950929334657533191315496803128582024343574898241463663463424353656,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/28.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/28.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4179649912 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_reset_error.4179649912' seed=83326781836950929334657533191315496803128582024343574898241463663463424353656 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=83326781836950929334657533191315496803128582024343574898241463663463424353656 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/28.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"29.xbar_access_same_device_slow_rsp.64324946128508820710967552663875204398854108237922595582357070903218470779778","seed":64324946128508820710967552663875204398854108237922595582357070903218470779778,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/29.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/29.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2408971138 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device_slow_rsp.2408971138' seed=64324946128508820710967552663875204398854108237922595582357070903218470779778 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=64324946128508820710967552663875204398854108237922595582357070903218470779778 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/29.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"29.xbar_stress_all_with_error.29349063729396377800371873932757030048129256198061495183574580120381911189384","seed":29349063729396377800371873932757030048129256198061495183574580120381911189384,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/29.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/29.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2019542920 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_error.2019542920' seed=29349063729396377800371873932757030048129256198061495183574580120381911189384 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=29349063729396377800371873932757030048129256198061495183574580120381911189384 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/29.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"29.xbar_stress_all_with_reset_error.98119112257407824636183980717342473528475862446479128612911831876753676384655","seed":98119112257407824636183980717342473528475862446479128612911831876753676384655,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/29.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/29.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4213520783 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_reset_error.4213520783' seed=98119112257407824636183980717342473528475862446479128612911831876753676384655 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=98119112257407824636183980717342473528475862446479128612911831876753676384655 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/29.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"30.xbar_access_same_device_slow_rsp.96615263442232551393519510855874020552718719777685824514024219271899394968438","seed":96615263442232551393519510855874020552718719777685824514024219271899394968438,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/30.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/30.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1732873078 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device_slow_rsp.1732873078' seed=96615263442232551393519510855874020552718719777685824514024219271899394968438 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=96615263442232551393519510855874020552718719777685824514024219271899394968438 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/30.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"30.xbar_stress_all_with_error.51705103627344288453593116877044963700369554600479814317003341616186828770258","seed":51705103627344288453593116877044963700369554600479814317003341616186828770258,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/30.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/30.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1371524050 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_error.1371524050' seed=51705103627344288453593116877044963700369554600479814317003341616186828770258 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=51705103627344288453593116877044963700369554600479814317003341616186828770258 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/30.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"30.xbar_stress_all_with_reset_error.18309050844211624486448453062761689012286301670355569973144322392304783091436","seed":18309050844211624486448453062761689012286301670355569973144322392304783091436,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/30.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/30.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=877291244 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_reset_error.877291244' seed=18309050844211624486448453062761689012286301670355569973144322392304783091436 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=18309050844211624486448453062761689012286301670355569973144322392304783091436 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/30.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"31.xbar_access_same_device_slow_rsp.11706216013343165734909645228633052998691778534048594333112354821373126582202","seed":11706216013343165734909645228633052998691778534048594333112354821373126582202,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/31.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/31.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=332210106 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device_slow_rsp.332210106' seed=11706216013343165734909645228633052998691778534048594333112354821373126582202 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=11706216013343165734909645228633052998691778534048594333112354821373126582202 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/31.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"31.xbar_stress_all_with_error.89458255770858712756504103004058489602705125416767351248274881989121189550659","seed":89458255770858712756504103004058489602705125416767351248274881989121189550659,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/31.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/31.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1934301763 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_error.1934301763' seed=89458255770858712756504103004058489602705125416767351248274881989121189550659 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=89458255770858712756504103004058489602705125416767351248274881989121189550659 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/31.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"31.xbar_stress_all_with_reset_error.26715451319700878436502404606052639637256002844170300795905333371434274251462","seed":26715451319700878436502404606052639637256002844170300795905333371434274251462,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/31.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/31.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1972495046 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_reset_error.1972495046' seed=26715451319700878436502404606052639637256002844170300795905333371434274251462 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=26715451319700878436502404606052639637256002844170300795905333371434274251462 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/31.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"32.xbar_access_same_device_slow_rsp.8538004144302617281870912883171689874350958702783190423345508287547858665152","seed":8538004144302617281870912883171689874350958702783190423345508287547858665152,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/32.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/32.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4093820608 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device_slow_rsp.4093820608' seed=8538004144302617281870912883171689874350958702783190423345508287547858665152 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=8538004144302617281870912883171689874350958702783190423345508287547858665152 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/32.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"32.xbar_stress_all_with_error.37918504112044647231919044214418494398197828385154935815549475784293386464785","seed":37918504112044647231919044214418494398197828385154935815549475784293386464785,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/32.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/32.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3570839057 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_error.3570839057' seed=37918504112044647231919044214418494398197828385154935815549475784293386464785 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=37918504112044647231919044214418494398197828385154935815549475784293386464785 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/32.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"32.xbar_stress_all_with_reset_error.76278297635745678323463629405558667920921369503828826074060862045858093091046","seed":76278297635745678323463629405558667920921369503828826074060862045858093091046,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/32.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/32.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=795625702 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_reset_error.795625702' seed=76278297635745678323463629405558667920921369503828826074060862045858093091046 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=76278297635745678323463629405558667920921369503828826074060862045858093091046 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/32.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"33.xbar_access_same_device_slow_rsp.69727175554898292482824372122022673546159091533664517630112272522094945933857","seed":69727175554898292482824372122022673546159091533664517630112272522094945933857,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/33.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/33.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=87202337 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device_slow_rsp.87202337' seed=69727175554898292482824372122022673546159091533664517630112272522094945933857 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=69727175554898292482824372122022673546159091533664517630112272522094945933857 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/33.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"33.xbar_stress_all_with_error.39520117262789876355579010424343800148374655572211970710134063925094028700319","seed":39520117262789876355579010424343800148374655572211970710134063925094028700319,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/33.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/33.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=434662047 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_error.434662047' seed=39520117262789876355579010424343800148374655572211970710134063925094028700319 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=39520117262789876355579010424343800148374655572211970710134063925094028700319 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/33.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"33.xbar_stress_all_with_reset_error.12883576830809661799097457019042175213967936355175708115182681275999982185374","seed":12883576830809661799097457019042175213967936355175708115182681275999982185374,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/33.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/33.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=870837150 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_reset_error.870837150' seed=12883576830809661799097457019042175213967936355175708115182681275999982185374 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=12883576830809661799097457019042175213967936355175708115182681275999982185374 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/33.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"34.xbar_access_same_device_slow_rsp.59683367074285092977176986346039223285755157573466503846496081075310681300201","seed":59683367074285092977176986346039223285755157573466503846496081075310681300201,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/34.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/34.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2998312169 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device_slow_rsp.2998312169' seed=59683367074285092977176986346039223285755157573466503846496081075310681300201 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=59683367074285092977176986346039223285755157573466503846496081075310681300201 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/34.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"34.xbar_stress_all_with_error.68807282258954000471089806176039114832280021089466213619375640865466577625482","seed":68807282258954000471089806176039114832280021089466213619375640865466577625482,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/34.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/34.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=428384650 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_error.428384650' seed=68807282258954000471089806176039114832280021089466213619375640865466577625482 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=68807282258954000471089806176039114832280021089466213619375640865466577625482 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/34.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"34.xbar_stress_all_with_reset_error.59732676769307676003090485899086890973471569129241804326290561057598322093345","seed":59732676769307676003090485899086890973471569129241804326290561057598322093345,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/34.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/34.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=697150753 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_reset_error.697150753' seed=59732676769307676003090485899086890973471569129241804326290561057598322093345 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=59732676769307676003090485899086890973471569129241804326290561057598322093345 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/34.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"35.xbar_access_same_device_slow_rsp.35907503896853498101603996362911989296308058036886197238558423308065806100437","seed":35907503896853498101603996362911989296308058036886197238558423308065806100437,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/35.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/35.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=379987925 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device_slow_rsp.379987925' seed=35907503896853498101603996362911989296308058036886197238558423308065806100437 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=35907503896853498101603996362911989296308058036886197238558423308065806100437 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/35.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"35.xbar_stress_all_with_error.6109632170328129420338110209102014235562469297714931742695721572054691026950","seed":6109632170328129420338110209102014235562469297714931742695721572054691026950,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/35.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/35.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1995511814 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_error.1995511814' seed=6109632170328129420338110209102014235562469297714931742695721572054691026950 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=6109632170328129420338110209102014235562469297714931742695721572054691026950 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/35.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"35.xbar_stress_all_with_reset_error.105599021010755068554585671376148964816844871658077681111078596184167755403058","seed":105599021010755068554585671376148964816844871658077681111078596184167755403058,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/35.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/35.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2627587890 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_reset_error.2627587890' seed=105599021010755068554585671376148964816844871658077681111078596184167755403058 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=105599021010755068554585671376148964816844871658077681111078596184167755403058 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/35.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"36.xbar_access_same_device_slow_rsp.99251346867412607152610641892259277157399625522277377632721915467969403923681","seed":99251346867412607152610641892259277157399625522277377632721915467969403923681,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/36.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/36.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1010150625 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device_slow_rsp.1010150625' seed=99251346867412607152610641892259277157399625522277377632721915467969403923681 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=99251346867412607152610641892259277157399625522277377632721915467969403923681 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/36.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"36.xbar_stress_all_with_error.25505656004441655411745569827641781885054716005478955723543266298186335624877","seed":25505656004441655411745569827641781885054716005478955723543266298186335624877,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/36.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/36.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4141457069 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_error.4141457069' seed=25505656004441655411745569827641781885054716005478955723543266298186335624877 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=25505656004441655411745569827641781885054716005478955723543266298186335624877 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/36.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"36.xbar_stress_all_with_reset_error.14271563546907583718390986989971352032858866609643825772721571352747134020072","seed":14271563546907583718390986989971352032858866609643825772721571352747134020072,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/36.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/36.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2055334376 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_reset_error.2055334376' seed=14271563546907583718390986989971352032858866609643825772721571352747134020072 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=14271563546907583718390986989971352032858866609643825772721571352747134020072 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/36.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"37.xbar_access_same_device_slow_rsp.57443594503724743677656143586140006290650733184813318561421563880969950072701","seed":57443594503724743677656143586140006290650733184813318561421563880969950072701,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/37.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/37.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=395186045 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device_slow_rsp.395186045' seed=57443594503724743677656143586140006290650733184813318561421563880969950072701 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=57443594503724743677656143586140006290650733184813318561421563880969950072701 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/37.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"37.xbar_stress_all_with_error.105867618627645370754109842810748984467049764647575223049276931059817541066046","seed":105867618627645370754109842810748984467049764647575223049276931059817541066046,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/37.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/37.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3298614590 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_error.3298614590' seed=105867618627645370754109842810748984467049764647575223049276931059817541066046 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=105867618627645370754109842810748984467049764647575223049276931059817541066046 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/37.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"37.xbar_stress_all_with_reset_error.115155174772241206008782379361093527382668566095852595817687457876609598895642","seed":115155174772241206008782379361093527382668566095852595817687457876609598895642,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/37.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/37.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2132162074 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_reset_error.2132162074' seed=115155174772241206008782379361093527382668566095852595817687457876609598895642 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=115155174772241206008782379361093527382668566095852595817687457876609598895642 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/37.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"38.xbar_access_same_device_slow_rsp.68873834447326887665534621967011587734538963759227721443899497202966689806319","seed":68873834447326887665534621967011587734538963759227721443899497202966689806319,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/38.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/38.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3202152431 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device_slow_rsp.3202152431' seed=68873834447326887665534621967011587734538963759227721443899497202966689806319 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=68873834447326887665534621967011587734538963759227721443899497202966689806319 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/38.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"38.xbar_stress_all_with_error.95652771319084201514388894847403727536206303199864287022761064245691412745695","seed":95652771319084201514388894847403727536206303199864287022761064245691412745695,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/38.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/38.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2818936287 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_error.2818936287' seed=95652771319084201514388894847403727536206303199864287022761064245691412745695 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=95652771319084201514388894847403727536206303199864287022761064245691412745695 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/38.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"38.xbar_stress_all_with_reset_error.102249825128243796441235186445064130480405312055030296799090019236281180281343","seed":102249825128243796441235186445064130480405312055030296799090019236281180281343,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/38.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/38.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2165627391 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_reset_error.2165627391' seed=102249825128243796441235186445064130480405312055030296799090019236281180281343 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=102249825128243796441235186445064130480405312055030296799090019236281180281343 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/38.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"39.xbar_access_same_device_slow_rsp.84228506125969814248015533173088888126395170972874126215768247635767043083931","seed":84228506125969814248015533173088888126395170972874126215768247635767043083931,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/39.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/39.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2057883291 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device_slow_rsp.2057883291' seed=84228506125969814248015533173088888126395170972874126215768247635767043083931 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=84228506125969814248015533173088888126395170972874126215768247635767043083931 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/39.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"39.xbar_stress_all_with_error.13789546574640150249514934662893514508662170388788481247745621772023258600970","seed":13789546574640150249514934662893514508662170388788481247745621772023258600970,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/39.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/39.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4043232778 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_error.4043232778' seed=13789546574640150249514934662893514508662170388788481247745621772023258600970 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=13789546574640150249514934662893514508662170388788481247745621772023258600970 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/39.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"39.xbar_stress_all_with_reset_error.26876322888739212826018857970987115335803879651423185567397144486353525926484","seed":26876322888739212826018857970987115335803879651423185567397144486353525926484,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/39.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/39.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3426871892 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_reset_error.3426871892' seed=26876322888739212826018857970987115335803879651423185567397144486353525926484 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=26876322888739212826018857970987115335803879651423185567397144486353525926484 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/39.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"40.xbar_access_same_device_slow_rsp.95430898993795442334669539591522815815744964421882191316269802136799009172908","seed":95430898993795442334669539591522815815744964421882191316269802136799009172908,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/40.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/40.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2529815980 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device_slow_rsp.2529815980' seed=95430898993795442334669539591522815815744964421882191316269802136799009172908 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=95430898993795442334669539591522815815744964421882191316269802136799009172908 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/40.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"40.xbar_stress_all_with_error.56125064421471835660396425652538629223758231677288265236577747279350706798551","seed":56125064421471835660396425652538629223758231677288265236577747279350706798551,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/40.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/40.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2747334615 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_error.2747334615' seed=56125064421471835660396425652538629223758231677288265236577747279350706798551 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=56125064421471835660396425652538629223758231677288265236577747279350706798551 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/40.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"40.xbar_stress_all_with_reset_error.26810993311584367831226144284110754483218087735627042146804024519815330076249","seed":26810993311584367831226144284110754483218087735627042146804024519815330076249,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/40.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/40.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1912936025 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_reset_error.1912936025' seed=26810993311584367831226144284110754483218087735627042146804024519815330076249 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=26810993311584367831226144284110754483218087735627042146804024519815330076249 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/40.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"41.xbar_access_same_device_slow_rsp.107012314622127688034407790653130947848479355752106912222199250889033214812443","seed":107012314622127688034407790653130947848479355752106912222199250889033214812443,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/41.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/41.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3830145307 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device_slow_rsp.3830145307' seed=107012314622127688034407790653130947848479355752106912222199250889033214812443 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=107012314622127688034407790653130947848479355752106912222199250889033214812443 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/41.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"41.xbar_stress_all_with_error.18005114275378240962583123232001299867827637489729932105251495389737009288726","seed":18005114275378240962583123232001299867827637489729932105251495389737009288726,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/41.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/41.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3464238614 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_error.3464238614' seed=18005114275378240962583123232001299867827637489729932105251495389737009288726 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=18005114275378240962583123232001299867827637489729932105251495389737009288726 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/41.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"41.xbar_stress_all_with_reset_error.27799266460430615148019600581637415763013412630434672707464926262752113759125","seed":27799266460430615148019600581637415763013412630434672707464926262752113759125,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/41.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/41.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1837798293 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_reset_error.1837798293' seed=27799266460430615148019600581637415763013412630434672707464926262752113759125 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=27799266460430615148019600581637415763013412630434672707464926262752113759125 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/41.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"42.xbar_access_same_device_slow_rsp.46763779927454626186855301218399623406091172314439778518704358259266677906461","seed":46763779927454626186855301218399623406091172314439778518704358259266677906461,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/42.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/42.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=345250845 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device_slow_rsp.345250845' seed=46763779927454626186855301218399623406091172314439778518704358259266677906461 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=46763779927454626186855301218399623406091172314439778518704358259266677906461 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/42.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"42.xbar_stress_all_with_error.67130366822919932503200393003360557410512062999164631125380326563871241575376","seed":67130366822919932503200393003360557410512062999164631125380326563871241575376,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/42.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/42.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3110378448 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_error.3110378448' seed=67130366822919932503200393003360557410512062999164631125380326563871241575376 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=67130366822919932503200393003360557410512062999164631125380326563871241575376 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/42.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"42.xbar_stress_all_with_reset_error.87186461615171994641457237065468294660337182627122747231524394780110244607904","seed":87186461615171994641457237065468294660337182627122747231524394780110244607904,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/42.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/42.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3381983136 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_reset_error.3381983136' seed=87186461615171994641457237065468294660337182627122747231524394780110244607904 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=87186461615171994641457237065468294660337182627122747231524394780110244607904 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/42.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"43.xbar_access_same_device_slow_rsp.41226145493964837239762189498428587373332436828765626949188694294485518518479","seed":41226145493964837239762189498428587373332436828765626949188694294485518518479,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/43.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/43.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=560466127 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device_slow_rsp.560466127' seed=41226145493964837239762189498428587373332436828765626949188694294485518518479 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=41226145493964837239762189498428587373332436828765626949188694294485518518479 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/43.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"43.xbar_stress_all_with_error.60096444943337190099571129245738704033568057230341636948331276283580402991039","seed":60096444943337190099571129245738704033568057230341636948331276283580402991039,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/43.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/43.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=905805759 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_error.905805759' seed=60096444943337190099571129245738704033568057230341636948331276283580402991039 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=60096444943337190099571129245738704033568057230341636948331276283580402991039 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/43.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"43.xbar_stress_all_with_reset_error.2242410052547387811037507437558318865239587778181493672476511406414716273392","seed":2242410052547387811037507437558318865239587778181493672476511406414716273392,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/43.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/43.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3958702832 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_reset_error.3958702832' seed=2242410052547387811037507437558318865239587778181493672476511406414716273392 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=2242410052547387811037507437558318865239587778181493672476511406414716273392 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/43.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"44.xbar_access_same_device_slow_rsp.68204312165335992863987743796489528023059889080061158940156679571583549046670","seed":68204312165335992863987743796489528023059889080061158940156679571583549046670,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/44.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/44.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1330904974 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device_slow_rsp.1330904974' seed=68204312165335992863987743796489528023059889080061158940156679571583549046670 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=68204312165335992863987743796489528023059889080061158940156679571583549046670 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/44.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"44.xbar_stress_all_with_error.89335464613938612487308187876872304149908992286575732174204891284067356165840","seed":89335464613938612487308187876872304149908992286575732174204891284067356165840,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/44.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/44.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3173697232 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_error.3173697232' seed=89335464613938612487308187876872304149908992286575732174204891284067356165840 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=89335464613938612487308187876872304149908992286575732174204891284067356165840 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/44.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"44.xbar_stress_all_with_reset_error.111873940309968114293177691567744862815071761014685975193696437261965859930433","seed":111873940309968114293177691567744862815071761014685975193696437261965859930433,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/44.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/44.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1516159297 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_reset_error.1516159297' seed=111873940309968114293177691567744862815071761014685975193696437261965859930433 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=111873940309968114293177691567744862815071761014685975193696437261965859930433 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/44.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"45.xbar_access_same_device_slow_rsp.104849401129426731984591896973627961937000629690546993595372425006248346297461","seed":104849401129426731984591896973627961937000629690546993595372425006248346297461,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/45.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/45.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3627066485 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device_slow_rsp.3627066485' seed=104849401129426731984591896973627961937000629690546993595372425006248346297461 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=104849401129426731984591896973627961937000629690546993595372425006248346297461 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/45.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"45.xbar_stress_all_with_error.68313820917730063055936329403113137412495345757137877707964519456599230177173","seed":68313820917730063055936329403113137412495345757137877707964519456599230177173,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/45.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/45.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1992875925 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_error.1992875925' seed=68313820917730063055936329403113137412495345757137877707964519456599230177173 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=68313820917730063055936329403113137412495345757137877707964519456599230177173 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/45.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"45.xbar_stress_all_with_reset_error.32186104940721784382614987963451275320647864401521946934896545101199124735059","seed":32186104940721784382614987963451275320647864401521946934896545101199124735059,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/45.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/45.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2151162963 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_reset_error.2151162963' seed=32186104940721784382614987963451275320647864401521946934896545101199124735059 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=32186104940721784382614987963451275320647864401521946934896545101199124735059 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/45.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"46.xbar_access_same_device_slow_rsp.21312462665189684432109016619752939834665259131470296494303550999112882460401","seed":21312462665189684432109016619752939834665259131470296494303550999112882460401,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/46.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/46.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2869303025 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device_slow_rsp.2869303025' seed=21312462665189684432109016619752939834665259131470296494303550999112882460401 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=21312462665189684432109016619752939834665259131470296494303550999112882460401 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/46.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"46.xbar_stress_all_with_error.79408206181106786515688754047978428949384976687969409636850522955584317945235","seed":79408206181106786515688754047978428949384976687969409636850522955584317945235,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/46.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/46.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1293677971 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_error.1293677971' seed=79408206181106786515688754047978428949384976687969409636850522955584317945235 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=79408206181106786515688754047978428949384976687969409636850522955584317945235 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/46.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"46.xbar_stress_all_with_reset_error.106819222204907449845036354394706926264991826957606634768387577358568693940774","seed":106819222204907449845036354394706926264991826957606634768387577358568693940774,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/46.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/46.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1093911078 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_reset_error.1093911078' seed=106819222204907449845036354394706926264991826957606634768387577358568693940774 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=106819222204907449845036354394706926264991826957606634768387577358568693940774 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/46.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"47.xbar_access_same_device_slow_rsp.21784920642216199337558642209002706537838609338299495775380595198078867462373","seed":21784920642216199337558642209002706537838609338299495775380595198078867462373,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/47.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/47.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=62118117 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device_slow_rsp.62118117' seed=21784920642216199337558642209002706537838609338299495775380595198078867462373 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=21784920642216199337558642209002706537838609338299495775380595198078867462373 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/47.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"47.xbar_stress_all_with_error.102028044777191762028703305134314078001038432380659537043172244244355684904258","seed":102028044777191762028703305134314078001038432380659537043172244244355684904258,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/47.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/47.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1477324098 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_error.1477324098' seed=102028044777191762028703305134314078001038432380659537043172244244355684904258 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=102028044777191762028703305134314078001038432380659537043172244244355684904258 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/47.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"47.xbar_stress_all_with_reset_error.17407669655316434766929901176376349768606204100146228733427800680781525655898","seed":17407669655316434766929901176376349768606204100146228733427800680781525655898,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/47.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/47.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=289251674 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_reset_error.289251674' seed=17407669655316434766929901176376349768606204100146228733427800680781525655898 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=17407669655316434766929901176376349768606204100146228733427800680781525655898 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/47.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"48.xbar_access_same_device_slow_rsp.16044417554305496500763687133376262380229082438210386687729589401332544121844","seed":16044417554305496500763687133376262380229082438210386687729589401332544121844,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/48.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/48.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1301490676 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device_slow_rsp.1301490676' seed=16044417554305496500763687133376262380229082438210386687729589401332544121844 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=16044417554305496500763687133376262380229082438210386687729589401332544121844 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/48.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"48.xbar_stress_all_with_error.36210723286690871598040325476943890370973669233316110310047648552794210137547","seed":36210723286690871598040325476943890370973669233316110310047648552794210137547,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/48.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/48.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2753000907 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_error.2753000907' seed=36210723286690871598040325476943890370973669233316110310047648552794210137547 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=36210723286690871598040325476943890370973669233316110310047648552794210137547 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/48.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"48.xbar_stress_all_with_reset_error.27907679349922677555204789192862340569624042715217130878133544375015988239728","seed":27907679349922677555204789192862340569624042715217130878133544375015988239728,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/48.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/48.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=105356656 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_reset_error.105356656' seed=27907679349922677555204789192862340569624042715217130878133544375015988239728 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=27907679349922677555204789192862340569624042715217130878133544375015988239728 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/48.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"49.xbar_access_same_device_slow_rsp.9075369707622831850590325662212908911949382743638028752850707436507731799245","seed":9075369707622831850590325662212908911949382743638028752850707436507731799245,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/49.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/49.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3162975437 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device_slow_rsp.3162975437' seed=9075369707622831850590325662212908911949382743638028752850707436507731799245 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=9075369707622831850590325662212908911949382743638028752850707436507731799245 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/49.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"49.xbar_stress_all_with_error.98821671669471612382840450283026412471753060814993284314143014204249389144607","seed":98821671669471612382840450283026412471753060814993284314143014204249389144607,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/49.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/49.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=473963039 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_error.473963039' seed=98821671669471612382840450283026412471753060814993284314143014204249389144607 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=98821671669471612382840450283026412471753060814993284314143014204249389144607 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/49.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"49.xbar_stress_all_with_reset_error.14325049887391635798652419145778878209885745414393828741760079110214961810984","seed":14325049887391635798652419145778878209885745414393828741760079110214961810984,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/49.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_main-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/49.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4276571688 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_main-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_reset_error.4276571688' seed=14325049887391635798652419145778878209885745414393828741760079110214961810984 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=14325049887391635798652419145778878209885745414393828741760079110214961810984 --run-dir=/nightly/current_run/scratch/master/xbar_main-sim-vcs/49.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]}],"Job cancelled because all of its dependencies failed or were killed.":[{"name":"xbar_main","qual_name":"cov_merge","seed":null,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/cov_merge/merged.vdb/cov_merge.log","log_context":[]}],"Job cancelled because one of its dependencies failed or was killed.":[{"name":"xbar_main","qual_name":"cov_report","seed":null,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_main-sim-vcs/cov_report/cov_report.log","log_context":[]}]}},"passed":0,"total":450,"percent":0.0}