{"block":{"name":"xbar_mbx","variant":null,"commit":"a0994129303fcb17a56df9a84a3babc5b4069141","commit_short":"a099412","branch":"master","url":"https://github.com/lowRISC/opentitan/tree/a0994129303fcb17a56df9a84a3babc5b4069141","revision_info":"GitHub Revision: [`a099412`](https://github.com/lowrisc/opentitan/tree/a0994129303fcb17a56df9a84a3babc5b4069141)"},"tool":{"name":"vcs","version":"unknown"},"timestamp":"2026-08-28T21:54:34Z","build_seed":null,"testplan_ref":"https://opentitan.org/book/hw/ip/tlul/data/tlul_testplan.html","stages":{"V1":{"testpoints":{"xbar_smoke":{"tests":{"xbar_smoke":{"max_time":1.5357214882969856,"sim_time":0.0,"passed":0,"total":20,"percent":0.0}},"passed":0,"total":20,"percent":0.0}},"passed":0,"total":20,"percent":0.0},"V2":{"testpoints":{"xbar_base_random_sequence":{"tests":{"xbar_random":{"max_time":1.5422203168272972,"sim_time":0.0,"passed":0,"total":20,"percent":0.0}},"passed":0,"total":20,"percent":0.0},"xbar_random_delay":{"tests":{"xbar_smoke_zero_delays":{"max_time":0.8993842843919992,"sim_time":0.0,"passed":0,"total":20,"percent":0.0},"xbar_smoke_large_delays":{"max_time":1.4257998308166862,"sim_time":0.0,"passed":0,"total":20,"percent":0.0},"xbar_smoke_slow_rsp":{"max_time":1.583359332755208,"sim_time":0.0,"passed":0,"total":20,"percent":0.0},"xbar_random_zero_delays":{"max_time":1.543592493981123,"sim_time":0.0,"passed":0,"total":20,"percent":0.0},"xbar_random_large_delays":{"max_time":1.317290616221726,"sim_time":0.0,"passed":0,"total":20,"percent":0.0},"xbar_random_slow_rsp":{"max_time":1.5901146223768592,"sim_time":0.0,"passed":0,"total":20,"percent":0.0}},"passed":0,"total":120,"percent":0.0},"xbar_unmapped_address":{"tests":{"xbar_unmapped_addr":{"max_time":1.5874177757650614,"sim_time":0.0,"passed":0,"total":20,"percent":0.0},"xbar_error_and_unmapped_addr":{"max_time":0.8997046034783125,"sim_time":0.0,"passed":0,"total":20,"percent":0.0}},"passed":0,"total":40,"percent":0.0},"xbar_error_cases":{"tests":{"xbar_error_random":{"max_time":1.574193337932229,"sim_time":0.0,"passed":0,"total":20,"percent":0.0},"xbar_error_and_unmapped_addr":{"max_time":0.8997046034783125,"sim_time":0.0,"passed":0,"total":20,"percent":0.0}},"passed":0,"total":40,"percent":0.0},"xbar_all_access_same_device":{"tests":{"xbar_access_same_device":{"max_time":0.873483988456428,"sim_time":0.0,"passed":0,"total":20,"percent":0.0},"xbar_access_same_device_slow_rsp":{"max_time":1.6000348748639226,"sim_time":0.0,"passed":0,"total":50,"percent":0.0}},"passed":0,"total":70,"percent":0.0},"xbar_all_hosts_use_same_source_id":{"tests":{"xbar_same_source":{"max_time":0.8858344927430153,"sim_time":0.0,"passed":0,"total":20,"percent":0.0}},"passed":0,"total":20,"percent":0.0},"xbar_stress_all":{"tests":{"xbar_stress_all":{"max_time":1.5475973235443234,"sim_time":0.0,"passed":0,"total":20,"percent":0.0},"xbar_stress_all_with_error":{"max_time":1.5489040538668633,"sim_time":0.0,"passed":0,"total":50,"percent":0.0}},"passed":0,"total":70,"percent":0.0},"xbar_stress_with_reset":{"tests":{"xbar_stress_all_with_rand_reset":{"max_time":0.8720781989395618,"sim_time":0.0,"passed":0,"total":20,"percent":0.0},"xbar_stress_all_with_reset_error":{"max_time":1.579480086453259,"sim_time":0.0,"passed":0,"total":50,"percent":0.0}},"passed":0,"total":70,"percent":0.0}},"passed":0,"total":430,"percent":0.0}},"coverage":{"code":{"block":null,"line_statement":null,"branch":null,"condition_expression":null,"toggle":null,"fsm":null},"assertion":null,"functional":null},"cov_report_page":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/cov_report/dashboard.html","vplan_report_page":null,"vplan_coverage":null,"failed_jobs":{"buckets":{"Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$']":[{"name":"xbar_smoke","qual_name":"0.xbar_smoke.85369096313494131489334185037039729449072023337799094730539382552547392654357","seed":85369096313494131489334185037039729449072023337799094730539382552547392654357,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/0.xbar_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/0.xbar_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2433649685 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke.2433649685' seed=85369096313494131489334185037039729449072023337799094730539382552547392654357 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=85369096313494131489334185037039729449072023337799094730539382552547392654357 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/0.xbar_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_zero_delays","qual_name":"0.xbar_smoke_zero_delays.46518231146582055281782318532032866707080525149275277923369017052102618824790","seed":46518231146582055281782318532032866707080525149275277923369017052102618824790,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/0.xbar_smoke_zero_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/0.xbar_smoke_zero_delays/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2789785686 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_zero_delays.2789785686' seed=46518231146582055281782318532032866707080525149275277923369017052102618824790 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=46518231146582055281782318532032866707080525149275277923369017052102618824790 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/0.xbar_smoke_zero_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_large_delays","qual_name":"0.xbar_smoke_large_delays.46923883394606561837779663408505742630061546584554578114499589561542956469525","seed":46923883394606561837779663408505742630061546584554578114499589561542956469525,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/0.xbar_smoke_large_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/0.xbar_smoke_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2186464533 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_large_delays.2186464533' seed=46923883394606561837779663408505742630061546584554578114499589561542956469525 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=46923883394606561837779663408505742630061546584554578114499589561542956469525 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/0.xbar_smoke_large_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_slow_rsp","qual_name":"0.xbar_smoke_slow_rsp.11689535212224094344254478108149171984919414781381791615612200144014884747001","seed":11689535212224094344254478108149171984919414781381791615612200144014884747001,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/0.xbar_smoke_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/0.xbar_smoke_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3415226105 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_slow_rsp.3415226105' seed=11689535212224094344254478108149171984919414781381791615612200144014884747001 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=11689535212224094344254478108149171984919414781381791615612200144014884747001 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/0.xbar_smoke_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random","qual_name":"0.xbar_random.29471598907613706028790273410784131775120818946437427781511269079855639654130","seed":29471598907613706028790273410784131775120818946437427781511269079855639654130,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/0.xbar_random/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/0.xbar_random/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1566142194 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random.1566142194' seed=29471598907613706028790273410784131775120818946437427781511269079855639654130 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=29471598907613706028790273410784131775120818946437427781511269079855639654130 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/0.xbar_random/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_zero_delays","qual_name":"0.xbar_random_zero_delays.51026281679783981618911261362571141518105996078934609297510993066661816279360","seed":51026281679783981618911261362571141518105996078934609297510993066661816279360,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/0.xbar_random_zero_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/0.xbar_random_zero_delays/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3249512768 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_zero_delays.3249512768' seed=51026281679783981618911261362571141518105996078934609297510993066661816279360 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=51026281679783981618911261362571141518105996078934609297510993066661816279360 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/0.xbar_random_zero_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_large_delays","qual_name":"0.xbar_random_large_delays.42222251679020028533581211148802156432603748404959567443076842528728876995228","seed":42222251679020028533581211148802156432603748404959567443076842528728876995228,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/0.xbar_random_large_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/0.xbar_random_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3713421980 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_large_delays.3713421980' seed=42222251679020028533581211148802156432603748404959567443076842528728876995228 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=42222251679020028533581211148802156432603748404959567443076842528728876995228 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/0.xbar_random_large_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_slow_rsp","qual_name":"0.xbar_random_slow_rsp.53291815044525569360145820160109527900615734142120553970674651522946095805724","seed":53291815044525569360145820160109527900615734142120553970674651522946095805724,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/0.xbar_random_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/0.xbar_random_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=764835100 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_slow_rsp.764835100' seed=53291815044525569360145820160109527900615734142120553970674651522946095805724 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=53291815044525569360145820160109527900615734142120553970674651522946095805724 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/0.xbar_random_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device","qual_name":"0.xbar_access_same_device.33741836275585991661421076213729652344604366952371598029519233365123128864025","seed":33741836275585991661421076213729652344604366952371598029519233365123128864025,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/0.xbar_access_same_device/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/0.xbar_access_same_device/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3035344153 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device.3035344153' seed=33741836275585991661421076213729652344604366952371598029519233365123128864025 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=33741836275585991661421076213729652344604366952371598029519233365123128864025 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/0.xbar_access_same_device/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"0.xbar_access_same_device_slow_rsp.19153323701747111784268920877358960954193699455577152016764081657497948013172","seed":19153323701747111784268920877358960954193699455577152016764081657497948013172,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/0.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/0.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2262844020 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device_slow_rsp.2262844020' seed=19153323701747111784268920877358960954193699455577152016764081657497948013172 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=19153323701747111784268920877358960954193699455577152016764081657497948013172 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/0.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_same_source","qual_name":"0.xbar_same_source.39108755375002209126049483865705321336384686233500124376439982879195321325118","seed":39108755375002209126049483865705321336384686233500124376439982879195321325118,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/0.xbar_same_source/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/0.xbar_same_source/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=297522750 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_same_source.297522750' seed=39108755375002209126049483865705321336384686233500124376439982879195321325118 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=39108755375002209126049483865705321336384686233500124376439982879195321325118 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/0.xbar_same_source/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_same_source_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_random","qual_name":"0.xbar_error_random.109104410063579404135208277384803234410074977984927031410205500334909830627066","seed":109104410063579404135208277384803234410074977984927031410205500334909830627066,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/0.xbar_error_random/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/0.xbar_error_random/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1199734522 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_error_random.1199734522' seed=109104410063579404135208277384803234410074977984927031410205500334909830627066 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=109104410063579404135208277384803234410074977984927031410205500334909830627066 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/0.xbar_error_random/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_unmapped_addr","qual_name":"0.xbar_unmapped_addr.112933137317613575876558892434001028622148936500777057732742354268527865848860","seed":112933137317613575876558892434001028622148936500777057732742354268527865848860,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/0.xbar_unmapped_addr/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/0.xbar_unmapped_addr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=484664348 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_unmapped_addr.484664348' seed=112933137317613575876558892434001028622148936500777057732742354268527865848860 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=112933137317613575876558892434001028622148936500777057732742354268527865848860 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/0.xbar_unmapped_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_and_unmapped_addr","qual_name":"0.xbar_error_and_unmapped_addr.101429312403352910967265653496927411101722894313235623863370969131557673208967","seed":101429312403352910967265653496927411101722894313235623863370969131557673208967,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/0.xbar_error_and_unmapped_addr/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/0.xbar_error_and_unmapped_addr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3466824839 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_error_and_unmapped_addr.3466824839' seed=101429312403352910967265653496927411101722894313235623863370969131557673208967 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=101429312403352910967265653496927411101722894313235623863370969131557673208967 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/0.xbar_error_and_unmapped_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all","qual_name":"0.xbar_stress_all.55345314541876362414401854280678393151872166831328470175992052071300465488450","seed":55345314541876362414401854280678393151872166831328470175992052071300465488450,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/0.xbar_stress_all/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/0.xbar_stress_all/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3491557954 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all.3491557954' seed=55345314541876362414401854280678393151872166831328470175992052071300465488450 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=55345314541876362414401854280678393151872166831328470175992052071300465488450 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/0.xbar_stress_all/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_rand_reset","qual_name":"0.xbar_stress_all_with_rand_reset.68343586448294685891481171367853168575851581706277984077236038211428641244167","seed":68343586448294685891481171367853168575851581706277984077236038211428641244167,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/0.xbar_stress_all_with_rand_reset/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/0.xbar_stress_all_with_rand_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=752190471 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_rand_reset.752190471' seed=68343586448294685891481171367853168575851581706277984077236038211428641244167 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=68343586448294685891481171367853168575851581706277984077236038211428641244167 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/0.xbar_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"0.xbar_stress_all_with_error.5480203602520588231721435847913124975239418325184258561095451093682160256206","seed":5480203602520588231721435847913124975239418325184258561095451093682160256206,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/0.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/0.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2589050062 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_error.2589050062' seed=5480203602520588231721435847913124975239418325184258561095451093682160256206 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=5480203602520588231721435847913124975239418325184258561095451093682160256206 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/0.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"0.xbar_stress_all_with_reset_error.24012985310640784388207731663508364382742664113597830866442199850576011674710","seed":24012985310640784388207731663508364382742664113597830866442199850576011674710,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/0.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/0.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2705146966 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_reset_error.2705146966' seed=24012985310640784388207731663508364382742664113597830866442199850576011674710 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=24012985310640784388207731663508364382742664113597830866442199850576011674710 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/0.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke","qual_name":"1.xbar_smoke.16190915109601732946684462843656412525967420270658528672951439138947534559079","seed":16190915109601732946684462843656412525967420270658528672951439138947534559079,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/1.xbar_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/1.xbar_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3880916839 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke.3880916839' seed=16190915109601732946684462843656412525967420270658528672951439138947534559079 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=16190915109601732946684462843656412525967420270658528672951439138947534559079 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/1.xbar_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_zero_delays","qual_name":"1.xbar_smoke_zero_delays.78026165367535100206697811551520193440459548905000906483990834851502682872203","seed":78026165367535100206697811551520193440459548905000906483990834851502682872203,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/1.xbar_smoke_zero_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/1.xbar_smoke_zero_delays/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=540350859 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_zero_delays.540350859' seed=78026165367535100206697811551520193440459548905000906483990834851502682872203 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=78026165367535100206697811551520193440459548905000906483990834851502682872203 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/1.xbar_smoke_zero_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_large_delays","qual_name":"1.xbar_smoke_large_delays.102787466905651379660149050864234162657132945235112922921181351357791419892619","seed":102787466905651379660149050864234162657132945235112922921181351357791419892619,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/1.xbar_smoke_large_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/1.xbar_smoke_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=469369739 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_large_delays.469369739' seed=102787466905651379660149050864234162657132945235112922921181351357791419892619 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=102787466905651379660149050864234162657132945235112922921181351357791419892619 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/1.xbar_smoke_large_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_slow_rsp","qual_name":"1.xbar_smoke_slow_rsp.27739234519295455670843397312454700424714945458750390651177598596953254791142","seed":27739234519295455670843397312454700424714945458750390651177598596953254791142,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/1.xbar_smoke_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/1.xbar_smoke_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1030096870 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_slow_rsp.1030096870' seed=27739234519295455670843397312454700424714945458750390651177598596953254791142 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=27739234519295455670843397312454700424714945458750390651177598596953254791142 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/1.xbar_smoke_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random","qual_name":"1.xbar_random.98005022649721661261406320505344707329318939010043034354716929325343037540807","seed":98005022649721661261406320505344707329318939010043034354716929325343037540807,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/1.xbar_random/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/1.xbar_random/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2809481671 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random.2809481671' seed=98005022649721661261406320505344707329318939010043034354716929325343037540807 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=98005022649721661261406320505344707329318939010043034354716929325343037540807 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/1.xbar_random/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_zero_delays","qual_name":"1.xbar_random_zero_delays.94822520643930183790405149053858507145948369778548939487756267622669635712778","seed":94822520643930183790405149053858507145948369778548939487756267622669635712778,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/1.xbar_random_zero_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/1.xbar_random_zero_delays/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3995760394 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_zero_delays.3995760394' seed=94822520643930183790405149053858507145948369778548939487756267622669635712778 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=94822520643930183790405149053858507145948369778548939487756267622669635712778 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/1.xbar_random_zero_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_large_delays","qual_name":"1.xbar_random_large_delays.37655919525684249410141381629663220071903945798287980145356595530258466249278","seed":37655919525684249410141381629663220071903945798287980145356595530258466249278,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/1.xbar_random_large_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/1.xbar_random_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=814783038 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_large_delays.814783038' seed=37655919525684249410141381629663220071903945798287980145356595530258466249278 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=37655919525684249410141381629663220071903945798287980145356595530258466249278 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/1.xbar_random_large_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_slow_rsp","qual_name":"1.xbar_random_slow_rsp.41236997365008993782427399071746870352308241025847635832968192097705310144065","seed":41236997365008993782427399071746870352308241025847635832968192097705310144065,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/1.xbar_random_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/1.xbar_random_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=206423617 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_slow_rsp.206423617' seed=41236997365008993782427399071746870352308241025847635832968192097705310144065 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=41236997365008993782427399071746870352308241025847635832968192097705310144065 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/1.xbar_random_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device","qual_name":"1.xbar_access_same_device.109323306972018653279437010853993165054850515757128058382048828675703303764270","seed":109323306972018653279437010853993165054850515757128058382048828675703303764270,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/1.xbar_access_same_device/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/1.xbar_access_same_device/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2968189230 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device.2968189230' seed=109323306972018653279437010853993165054850515757128058382048828675703303764270 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=109323306972018653279437010853993165054850515757128058382048828675703303764270 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/1.xbar_access_same_device/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"1.xbar_access_same_device_slow_rsp.60314435469287247320853142413622734312258796958796464656095270286938115262795","seed":60314435469287247320853142413622734312258796958796464656095270286938115262795,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/1.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/1.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=233163083 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device_slow_rsp.233163083' seed=60314435469287247320853142413622734312258796958796464656095270286938115262795 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=60314435469287247320853142413622734312258796958796464656095270286938115262795 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/1.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_same_source","qual_name":"1.xbar_same_source.69972283002938081726586843613362674670097738862650544660716840501256100629139","seed":69972283002938081726586843613362674670097738862650544660716840501256100629139,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/1.xbar_same_source/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/1.xbar_same_source/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1129695891 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_same_source.1129695891' seed=69972283002938081726586843613362674670097738862650544660716840501256100629139 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=69972283002938081726586843613362674670097738862650544660716840501256100629139 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/1.xbar_same_source/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_same_source_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_random","qual_name":"1.xbar_error_random.16415393944228863582227810205569735253323103998321494527958499766221375725538","seed":16415393944228863582227810205569735253323103998321494527958499766221375725538,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/1.xbar_error_random/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/1.xbar_error_random/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3379486690 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_error_random.3379486690' seed=16415393944228863582227810205569735253323103998321494527958499766221375725538 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=16415393944228863582227810205569735253323103998321494527958499766221375725538 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/1.xbar_error_random/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_unmapped_addr","qual_name":"1.xbar_unmapped_addr.91131428229966206677983710061344528233589659540849723460722655512593553444997","seed":91131428229966206677983710061344528233589659540849723460722655512593553444997,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/1.xbar_unmapped_addr/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/1.xbar_unmapped_addr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1326731397 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_unmapped_addr.1326731397' seed=91131428229966206677983710061344528233589659540849723460722655512593553444997 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=91131428229966206677983710061344528233589659540849723460722655512593553444997 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/1.xbar_unmapped_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_and_unmapped_addr","qual_name":"1.xbar_error_and_unmapped_addr.88500065457792252565534241545133197854497379003110329163730504298983352688761","seed":88500065457792252565534241545133197854497379003110329163730504298983352688761,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/1.xbar_error_and_unmapped_addr/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/1.xbar_error_and_unmapped_addr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1331421305 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_error_and_unmapped_addr.1331421305' seed=88500065457792252565534241545133197854497379003110329163730504298983352688761 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=88500065457792252565534241545133197854497379003110329163730504298983352688761 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/1.xbar_error_and_unmapped_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all","qual_name":"1.xbar_stress_all.49953467690591677164886854948487113545027127554053570777986456346596577673842","seed":49953467690591677164886854948487113545027127554053570777986456346596577673842,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/1.xbar_stress_all/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/1.xbar_stress_all/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1010860658 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all.1010860658' seed=49953467690591677164886854948487113545027127554053570777986456346596577673842 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=49953467690591677164886854948487113545027127554053570777986456346596577673842 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/1.xbar_stress_all/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_rand_reset","qual_name":"1.xbar_stress_all_with_rand_reset.94395833849682655209010670381150802946783384271085323289829988069758865279316","seed":94395833849682655209010670381150802946783384271085323289829988069758865279316,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/1.xbar_stress_all_with_rand_reset/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/1.xbar_stress_all_with_rand_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=988580180 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_rand_reset.988580180' seed=94395833849682655209010670381150802946783384271085323289829988069758865279316 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=94395833849682655209010670381150802946783384271085323289829988069758865279316 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/1.xbar_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"1.xbar_stress_all_with_error.78955661851488338263102428922843721633243558176355807701537093309350328280106","seed":78955661851488338263102428922843721633243558176355807701537093309350328280106,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/1.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/1.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=342762538 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_error.342762538' seed=78955661851488338263102428922843721633243558176355807701537093309350328280106 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=78955661851488338263102428922843721633243558176355807701537093309350328280106 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/1.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"1.xbar_stress_all_with_reset_error.101327825884170304901074707292617283240706058228229846133304997678892075605643","seed":101327825884170304901074707292617283240706058228229846133304997678892075605643,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/1.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/1.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2683461259 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_reset_error.2683461259' seed=101327825884170304901074707292617283240706058228229846133304997678892075605643 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=101327825884170304901074707292617283240706058228229846133304997678892075605643 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/1.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke","qual_name":"2.xbar_smoke.64257923436603792590218606675737713837845959135141153896734744083804457727931","seed":64257923436603792590218606675737713837845959135141153896734744083804457727931,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/2.xbar_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/2.xbar_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=25884603 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke.25884603' seed=64257923436603792590218606675737713837845959135141153896734744083804457727931 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=64257923436603792590218606675737713837845959135141153896734744083804457727931 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/2.xbar_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_zero_delays","qual_name":"2.xbar_smoke_zero_delays.46595579635931056620379687067506543932275338381212889973460551859079509441959","seed":46595579635931056620379687067506543932275338381212889973460551859079509441959,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/2.xbar_smoke_zero_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/2.xbar_smoke_zero_delays/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=386661799 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_zero_delays.386661799' seed=46595579635931056620379687067506543932275338381212889973460551859079509441959 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=46595579635931056620379687067506543932275338381212889973460551859079509441959 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/2.xbar_smoke_zero_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_large_delays","qual_name":"2.xbar_smoke_large_delays.37775633757774533342104221336450670993660128388443078936510797176573489349903","seed":37775633757774533342104221336450670993660128388443078936510797176573489349903,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/2.xbar_smoke_large_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/2.xbar_smoke_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2924512527 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_large_delays.2924512527' seed=37775633757774533342104221336450670993660128388443078936510797176573489349903 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=37775633757774533342104221336450670993660128388443078936510797176573489349903 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/2.xbar_smoke_large_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_slow_rsp","qual_name":"2.xbar_smoke_slow_rsp.107882509370717405603198959512714924687617472061451591149907434073740347036760","seed":107882509370717405603198959512714924687617472061451591149907434073740347036760,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/2.xbar_smoke_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/2.xbar_smoke_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2770457688 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_slow_rsp.2770457688' seed=107882509370717405603198959512714924687617472061451591149907434073740347036760 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=107882509370717405603198959512714924687617472061451591149907434073740347036760 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/2.xbar_smoke_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random","qual_name":"2.xbar_random.50130958676722625230016109325697713693503221969160285673936347559813423436740","seed":50130958676722625230016109325697713693503221969160285673936347559813423436740,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/2.xbar_random/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/2.xbar_random/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3599635396 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random.3599635396' seed=50130958676722625230016109325697713693503221969160285673936347559813423436740 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=50130958676722625230016109325697713693503221969160285673936347559813423436740 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/2.xbar_random/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_zero_delays","qual_name":"2.xbar_random_zero_delays.47749859120446527369595294416149365667351414967481731165121343207190038197174","seed":47749859120446527369595294416149365667351414967481731165121343207190038197174,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/2.xbar_random_zero_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/2.xbar_random_zero_delays/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4110037942 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_zero_delays.4110037942' seed=47749859120446527369595294416149365667351414967481731165121343207190038197174 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=47749859120446527369595294416149365667351414967481731165121343207190038197174 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/2.xbar_random_zero_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_large_delays","qual_name":"2.xbar_random_large_delays.35525026748923033146036420451440212509671977670812247370013363921629038513750","seed":35525026748923033146036420451440212509671977670812247370013363921629038513750,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/2.xbar_random_large_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/2.xbar_random_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=457182806 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_large_delays.457182806' seed=35525026748923033146036420451440212509671977670812247370013363921629038513750 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=35525026748923033146036420451440212509671977670812247370013363921629038513750 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/2.xbar_random_large_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_slow_rsp","qual_name":"2.xbar_random_slow_rsp.7250712241584075421243359825145712321637037576050268788311706722073041132376","seed":7250712241584075421243359825145712321637037576050268788311706722073041132376,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/2.xbar_random_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/2.xbar_random_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2710002520 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_slow_rsp.2710002520' seed=7250712241584075421243359825145712321637037576050268788311706722073041132376 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=7250712241584075421243359825145712321637037576050268788311706722073041132376 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/2.xbar_random_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device","qual_name":"2.xbar_access_same_device.18948937062447119035889464687117620925072825964455970229367820330937335387585","seed":18948937062447119035889464687117620925072825964455970229367820330937335387585,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/2.xbar_access_same_device/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/2.xbar_access_same_device/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2778699201 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device.2778699201' seed=18948937062447119035889464687117620925072825964455970229367820330937335387585 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=18948937062447119035889464687117620925072825964455970229367820330937335387585 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/2.xbar_access_same_device/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"2.xbar_access_same_device_slow_rsp.1098524752319530807169858410140124096490103891692665065679773144268949084597","seed":1098524752319530807169858410140124096490103891692665065679773144268949084597,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/2.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/2.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1622333877 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device_slow_rsp.1622333877' seed=1098524752319530807169858410140124096490103891692665065679773144268949084597 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=1098524752319530807169858410140124096490103891692665065679773144268949084597 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/2.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_same_source","qual_name":"2.xbar_same_source.60428426493954009627677847301953007400679983725071632418012256341483155245652","seed":60428426493954009627677847301953007400679983725071632418012256341483155245652,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/2.xbar_same_source/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/2.xbar_same_source/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4003088980 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_same_source.4003088980' seed=60428426493954009627677847301953007400679983725071632418012256341483155245652 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=60428426493954009627677847301953007400679983725071632418012256341483155245652 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/2.xbar_same_source/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_same_source_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_random","qual_name":"2.xbar_error_random.8809074812575101344024299197421843714260761314072904624437137531045352690881","seed":8809074812575101344024299197421843714260761314072904624437137531045352690881,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/2.xbar_error_random/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/2.xbar_error_random/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2072630465 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_error_random.2072630465' seed=8809074812575101344024299197421843714260761314072904624437137531045352690881 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=8809074812575101344024299197421843714260761314072904624437137531045352690881 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/2.xbar_error_random/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_unmapped_addr","qual_name":"2.xbar_unmapped_addr.7530478090294421072491488442843318955491488195366621741758917271076344264626","seed":7530478090294421072491488442843318955491488195366621741758917271076344264626,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/2.xbar_unmapped_addr/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/2.xbar_unmapped_addr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=544569266 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_unmapped_addr.544569266' seed=7530478090294421072491488442843318955491488195366621741758917271076344264626 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=7530478090294421072491488442843318955491488195366621741758917271076344264626 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/2.xbar_unmapped_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_and_unmapped_addr","qual_name":"2.xbar_error_and_unmapped_addr.24521098115040654051897982836720355520379046982835020560555506930075592515396","seed":24521098115040654051897982836720355520379046982835020560555506930075592515396,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/2.xbar_error_and_unmapped_addr/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/2.xbar_error_and_unmapped_addr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2037604164 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_error_and_unmapped_addr.2037604164' seed=24521098115040654051897982836720355520379046982835020560555506930075592515396 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=24521098115040654051897982836720355520379046982835020560555506930075592515396 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/2.xbar_error_and_unmapped_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all","qual_name":"2.xbar_stress_all.72063436411801011457604521633924705850852436585852418205352306605534266881111","seed":72063436411801011457604521633924705850852436585852418205352306605534266881111,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/2.xbar_stress_all/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/2.xbar_stress_all/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2512745559 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all.2512745559' seed=72063436411801011457604521633924705850852436585852418205352306605534266881111 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=72063436411801011457604521633924705850852436585852418205352306605534266881111 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/2.xbar_stress_all/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_rand_reset","qual_name":"2.xbar_stress_all_with_rand_reset.56775353183220521293865431296170326868157738205145475685037315917257620115822","seed":56775353183220521293865431296170326868157738205145475685037315917257620115822,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/2.xbar_stress_all_with_rand_reset/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/2.xbar_stress_all_with_rand_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3044069742 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_rand_reset.3044069742' seed=56775353183220521293865431296170326868157738205145475685037315917257620115822 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=56775353183220521293865431296170326868157738205145475685037315917257620115822 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/2.xbar_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"2.xbar_stress_all_with_error.102933753348624002885873258001473578145491449941269198069852525493865773718619","seed":102933753348624002885873258001473578145491449941269198069852525493865773718619,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/2.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/2.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2835799131 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_error.2835799131' seed=102933753348624002885873258001473578145491449941269198069852525493865773718619 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=102933753348624002885873258001473578145491449941269198069852525493865773718619 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/2.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"2.xbar_stress_all_with_reset_error.67995091729626661822517809950590049708256279864516955544806845346447984799565","seed":67995091729626661822517809950590049708256279864516955544806845346447984799565,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/2.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/2.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3961368397 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_reset_error.3961368397' seed=67995091729626661822517809950590049708256279864516955544806845346447984799565 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=67995091729626661822517809950590049708256279864516955544806845346447984799565 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/2.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke","qual_name":"3.xbar_smoke.100370247035898731978237906204454853808942504005991771982767943998237602325939","seed":100370247035898731978237906204454853808942504005991771982767943998237602325939,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/3.xbar_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/3.xbar_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4265452979 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke.4265452979' seed=100370247035898731978237906204454853808942504005991771982767943998237602325939 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=100370247035898731978237906204454853808942504005991771982767943998237602325939 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/3.xbar_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_zero_delays","qual_name":"3.xbar_smoke_zero_delays.62182672758962465205336218369882522404642052103857490635921944630997518099711","seed":62182672758962465205336218369882522404642052103857490635921944630997518099711,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/3.xbar_smoke_zero_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/3.xbar_smoke_zero_delays/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=713532671 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_zero_delays.713532671' seed=62182672758962465205336218369882522404642052103857490635921944630997518099711 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=62182672758962465205336218369882522404642052103857490635921944630997518099711 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/3.xbar_smoke_zero_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_large_delays","qual_name":"3.xbar_smoke_large_delays.70464350465874352345911218663883857450127962570123815590542128230833890371224","seed":70464350465874352345911218663883857450127962570123815590542128230833890371224,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/3.xbar_smoke_large_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/3.xbar_smoke_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2562827928 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_large_delays.2562827928' seed=70464350465874352345911218663883857450127962570123815590542128230833890371224 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=70464350465874352345911218663883857450127962570123815590542128230833890371224 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/3.xbar_smoke_large_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_slow_rsp","qual_name":"3.xbar_smoke_slow_rsp.45579866981606793153564008274767056204784427196003803518486627089605276356314","seed":45579866981606793153564008274767056204784427196003803518486627089605276356314,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/3.xbar_smoke_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/3.xbar_smoke_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1735282394 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_slow_rsp.1735282394' seed=45579866981606793153564008274767056204784427196003803518486627089605276356314 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=45579866981606793153564008274767056204784427196003803518486627089605276356314 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/3.xbar_smoke_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random","qual_name":"3.xbar_random.2171542085325681417519696397131066320326399244285924441378053297307832631848","seed":2171542085325681417519696397131066320326399244285924441378053297307832631848,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/3.xbar_random/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/3.xbar_random/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2350989864 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random.2350989864' seed=2171542085325681417519696397131066320326399244285924441378053297307832631848 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=2171542085325681417519696397131066320326399244285924441378053297307832631848 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/3.xbar_random/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_zero_delays","qual_name":"3.xbar_random_zero_delays.17680846996517943254640536881151067780609502579062468128425258328381702918253","seed":17680846996517943254640536881151067780609502579062468128425258328381702918253,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/3.xbar_random_zero_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/3.xbar_random_zero_delays/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3687960685 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_zero_delays.3687960685' seed=17680846996517943254640536881151067780609502579062468128425258328381702918253 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=17680846996517943254640536881151067780609502579062468128425258328381702918253 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/3.xbar_random_zero_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_large_delays","qual_name":"3.xbar_random_large_delays.99789026165837823419661486755752610707125488210700213945219202619236714771731","seed":99789026165837823419661486755752610707125488210700213945219202619236714771731,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/3.xbar_random_large_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/3.xbar_random_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=557282579 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_large_delays.557282579' seed=99789026165837823419661486755752610707125488210700213945219202619236714771731 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=99789026165837823419661486755752610707125488210700213945219202619236714771731 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/3.xbar_random_large_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_slow_rsp","qual_name":"3.xbar_random_slow_rsp.74511372784616924833840762681753085290731457448903313409364901554729152178603","seed":74511372784616924833840762681753085290731457448903313409364901554729152178603,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/3.xbar_random_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/3.xbar_random_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3246418347 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_slow_rsp.3246418347' seed=74511372784616924833840762681753085290731457448903313409364901554729152178603 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=74511372784616924833840762681753085290731457448903313409364901554729152178603 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/3.xbar_random_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device","qual_name":"3.xbar_access_same_device.13742982789857571804900181614875718685818845074810093067734301596567650630202","seed":13742982789857571804900181614875718685818845074810093067734301596567650630202,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/3.xbar_access_same_device/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/3.xbar_access_same_device/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=971176506 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device.971176506' seed=13742982789857571804900181614875718685818845074810093067734301596567650630202 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=13742982789857571804900181614875718685818845074810093067734301596567650630202 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/3.xbar_access_same_device/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"3.xbar_access_same_device_slow_rsp.89913564379019694968744862785799943564901894546436863799177295536075157670451","seed":89913564379019694968744862785799943564901894546436863799177295536075157670451,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/3.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/3.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2325350963 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device_slow_rsp.2325350963' seed=89913564379019694968744862785799943564901894546436863799177295536075157670451 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=89913564379019694968744862785799943564901894546436863799177295536075157670451 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/3.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_same_source","qual_name":"3.xbar_same_source.42887602033319241887244525158250873971131721675240872204518581167512051552786","seed":42887602033319241887244525158250873971131721675240872204518581167512051552786,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/3.xbar_same_source/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/3.xbar_same_source/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2863436306 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_same_source.2863436306' seed=42887602033319241887244525158250873971131721675240872204518581167512051552786 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=42887602033319241887244525158250873971131721675240872204518581167512051552786 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/3.xbar_same_source/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_same_source_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_random","qual_name":"3.xbar_error_random.36825770702263693852756790341656420917311581834489600793138634276606919254840","seed":36825770702263693852756790341656420917311581834489600793138634276606919254840,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/3.xbar_error_random/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/3.xbar_error_random/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2118853432 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_error_random.2118853432' seed=36825770702263693852756790341656420917311581834489600793138634276606919254840 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=36825770702263693852756790341656420917311581834489600793138634276606919254840 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/3.xbar_error_random/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_unmapped_addr","qual_name":"3.xbar_unmapped_addr.102605681707259189917799655060627553636542830385192338523634101288454670310904","seed":102605681707259189917799655060627553636542830385192338523634101288454670310904,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/3.xbar_unmapped_addr/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/3.xbar_unmapped_addr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1224793592 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_unmapped_addr.1224793592' seed=102605681707259189917799655060627553636542830385192338523634101288454670310904 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=102605681707259189917799655060627553636542830385192338523634101288454670310904 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/3.xbar_unmapped_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_and_unmapped_addr","qual_name":"3.xbar_error_and_unmapped_addr.80503571155687310430805873631087958314050454127692124127291031326829849379355","seed":80503571155687310430805873631087958314050454127692124127291031326829849379355,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/3.xbar_error_and_unmapped_addr/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/3.xbar_error_and_unmapped_addr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2301133339 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_error_and_unmapped_addr.2301133339' seed=80503571155687310430805873631087958314050454127692124127291031326829849379355 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=80503571155687310430805873631087958314050454127692124127291031326829849379355 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/3.xbar_error_and_unmapped_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all","qual_name":"3.xbar_stress_all.66651693164676256220840414533854823881276293671931945960332638465285730518794","seed":66651693164676256220840414533854823881276293671931945960332638465285730518794,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/3.xbar_stress_all/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/3.xbar_stress_all/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=605210378 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all.605210378' seed=66651693164676256220840414533854823881276293671931945960332638465285730518794 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=66651693164676256220840414533854823881276293671931945960332638465285730518794 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/3.xbar_stress_all/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_rand_reset","qual_name":"3.xbar_stress_all_with_rand_reset.108275640764492712115361464743651000746093683667366970413313134836330057394813","seed":108275640764492712115361464743651000746093683667366970413313134836330057394813,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/3.xbar_stress_all_with_rand_reset/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/3.xbar_stress_all_with_rand_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3477564029 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_rand_reset.3477564029' seed=108275640764492712115361464743651000746093683667366970413313134836330057394813 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=108275640764492712115361464743651000746093683667366970413313134836330057394813 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/3.xbar_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"3.xbar_stress_all_with_error.5554224530506345717085914581094765676304073452868525631986190226297632267668","seed":5554224530506345717085914581094765676304073452868525631986190226297632267668,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/3.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/3.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2446794132 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_error.2446794132' seed=5554224530506345717085914581094765676304073452868525631986190226297632267668 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=5554224530506345717085914581094765676304073452868525631986190226297632267668 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/3.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"3.xbar_stress_all_with_reset_error.34149382576695751427421632119792259083217614809980364604327312200190716710421","seed":34149382576695751427421632119792259083217614809980364604327312200190716710421,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/3.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/3.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3098971669 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_reset_error.3098971669' seed=34149382576695751427421632119792259083217614809980364604327312200190716710421 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=34149382576695751427421632119792259083217614809980364604327312200190716710421 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/3.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke","qual_name":"4.xbar_smoke.36240779983399889027185911083343608099310498976595681674472898387029564879293","seed":36240779983399889027185911083343608099310498976595681674472898387029564879293,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/4.xbar_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/4.xbar_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2594730429 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke.2594730429' seed=36240779983399889027185911083343608099310498976595681674472898387029564879293 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=36240779983399889027185911083343608099310498976595681674472898387029564879293 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/4.xbar_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_zero_delays","qual_name":"4.xbar_smoke_zero_delays.58585954177107837652384031735577076889782472862805309282682359296473006389583","seed":58585954177107837652384031735577076889782472862805309282682359296473006389583,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/4.xbar_smoke_zero_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/4.xbar_smoke_zero_delays/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2621487439 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_zero_delays.2621487439' seed=58585954177107837652384031735577076889782472862805309282682359296473006389583 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=58585954177107837652384031735577076889782472862805309282682359296473006389583 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/4.xbar_smoke_zero_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_large_delays","qual_name":"4.xbar_smoke_large_delays.48896388005181804612203031543471790055450316014338593934022812922422233279968","seed":48896388005181804612203031543471790055450316014338593934022812922422233279968,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/4.xbar_smoke_large_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/4.xbar_smoke_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=780283360 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_large_delays.780283360' seed=48896388005181804612203031543471790055450316014338593934022812922422233279968 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=48896388005181804612203031543471790055450316014338593934022812922422233279968 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/4.xbar_smoke_large_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_slow_rsp","qual_name":"4.xbar_smoke_slow_rsp.26672086478897806850571212001105292742439811635431634417642868711080192014385","seed":26672086478897806850571212001105292742439811635431634417642868711080192014385,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/4.xbar_smoke_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/4.xbar_smoke_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1890744369 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_slow_rsp.1890744369' seed=26672086478897806850571212001105292742439811635431634417642868711080192014385 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=26672086478897806850571212001105292742439811635431634417642868711080192014385 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/4.xbar_smoke_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random","qual_name":"4.xbar_random.92267849298535585720021683243441706041279085675649735498828248433199247451371","seed":92267849298535585720021683243441706041279085675649735498828248433199247451371,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/4.xbar_random/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/4.xbar_random/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1363076331 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random.1363076331' seed=92267849298535585720021683243441706041279085675649735498828248433199247451371 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=92267849298535585720021683243441706041279085675649735498828248433199247451371 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/4.xbar_random/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_zero_delays","qual_name":"4.xbar_random_zero_delays.24886688068752221187374061839028754042368260179192461433661476396433255740537","seed":24886688068752221187374061839028754042368260179192461433661476396433255740537,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/4.xbar_random_zero_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/4.xbar_random_zero_delays/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2672604281 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_zero_delays.2672604281' seed=24886688068752221187374061839028754042368260179192461433661476396433255740537 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=24886688068752221187374061839028754042368260179192461433661476396433255740537 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/4.xbar_random_zero_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_large_delays","qual_name":"4.xbar_random_large_delays.98347245288881951120841476233665693154922958326561121079539066581189427996670","seed":98347245288881951120841476233665693154922958326561121079539066581189427996670,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/4.xbar_random_large_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/4.xbar_random_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1417684990 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_large_delays.1417684990' seed=98347245288881951120841476233665693154922958326561121079539066581189427996670 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=98347245288881951120841476233665693154922958326561121079539066581189427996670 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/4.xbar_random_large_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_slow_rsp","qual_name":"4.xbar_random_slow_rsp.46962324816201876961029670868674403485510743870645984490626761059735206642307","seed":46962324816201876961029670868674403485510743870645984490626761059735206642307,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/4.xbar_random_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/4.xbar_random_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1386234499 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_slow_rsp.1386234499' seed=46962324816201876961029670868674403485510743870645984490626761059735206642307 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=46962324816201876961029670868674403485510743870645984490626761059735206642307 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/4.xbar_random_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device","qual_name":"4.xbar_access_same_device.93033240051206794343500855981574822786032611059576287237146491968190333604982","seed":93033240051206794343500855981574822786032611059576287237146491968190333604982,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/4.xbar_access_same_device/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/4.xbar_access_same_device/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=969430134 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device.969430134' seed=93033240051206794343500855981574822786032611059576287237146491968190333604982 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=93033240051206794343500855981574822786032611059576287237146491968190333604982 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/4.xbar_access_same_device/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"4.xbar_access_same_device_slow_rsp.60786086956759704080385474265135358023866037786803775981377667080192276970432","seed":60786086956759704080385474265135358023866037786803775981377667080192276970432,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/4.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/4.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3317840832 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device_slow_rsp.3317840832' seed=60786086956759704080385474265135358023866037786803775981377667080192276970432 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=60786086956759704080385474265135358023866037786803775981377667080192276970432 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/4.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_same_source","qual_name":"4.xbar_same_source.113688683081841962284549690316454511575108917580735507772317998083954752571428","seed":113688683081841962284549690316454511575108917580735507772317998083954752571428,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/4.xbar_same_source/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/4.xbar_same_source/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=794773540 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_same_source.794773540' seed=113688683081841962284549690316454511575108917580735507772317998083954752571428 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=113688683081841962284549690316454511575108917580735507772317998083954752571428 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/4.xbar_same_source/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_same_source_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_random","qual_name":"4.xbar_error_random.91341289381693964889041116929142740260631605987479223937883946442820233683969","seed":91341289381693964889041116929142740260631605987479223937883946442820233683969,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/4.xbar_error_random/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/4.xbar_error_random/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1355506689 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_error_random.1355506689' seed=91341289381693964889041116929142740260631605987479223937883946442820233683969 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=91341289381693964889041116929142740260631605987479223937883946442820233683969 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/4.xbar_error_random/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_unmapped_addr","qual_name":"4.xbar_unmapped_addr.84333653943352694638075658958021858604896983229785357158357139704593772800846","seed":84333653943352694638075658958021858604896983229785357158357139704593772800846,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/4.xbar_unmapped_addr/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/4.xbar_unmapped_addr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2139450190 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_unmapped_addr.2139450190' seed=84333653943352694638075658958021858604896983229785357158357139704593772800846 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=84333653943352694638075658958021858604896983229785357158357139704593772800846 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/4.xbar_unmapped_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_and_unmapped_addr","qual_name":"4.xbar_error_and_unmapped_addr.13830036036214329326325641883850883136037011283698363831676453786181044741935","seed":13830036036214329326325641883850883136037011283698363831676453786181044741935,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/4.xbar_error_and_unmapped_addr/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/4.xbar_error_and_unmapped_addr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3851888431 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_error_and_unmapped_addr.3851888431' seed=13830036036214329326325641883850883136037011283698363831676453786181044741935 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=13830036036214329326325641883850883136037011283698363831676453786181044741935 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/4.xbar_error_and_unmapped_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all","qual_name":"4.xbar_stress_all.60970701528397613130249145523558862814219846322889265770572572060340205363387","seed":60970701528397613130249145523558862814219846322889265770572572060340205363387,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/4.xbar_stress_all/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/4.xbar_stress_all/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2847383739 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all.2847383739' seed=60970701528397613130249145523558862814219846322889265770572572060340205363387 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=60970701528397613130249145523558862814219846322889265770572572060340205363387 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/4.xbar_stress_all/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_rand_reset","qual_name":"4.xbar_stress_all_with_rand_reset.28630867496214727702893029737518836455564737498726322792929986623566973523736","seed":28630867496214727702893029737518836455564737498726322792929986623566973523736,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/4.xbar_stress_all_with_rand_reset/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/4.xbar_stress_all_with_rand_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1197496088 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_rand_reset.1197496088' seed=28630867496214727702893029737518836455564737498726322792929986623566973523736 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=28630867496214727702893029737518836455564737498726322792929986623566973523736 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/4.xbar_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"4.xbar_stress_all_with_error.13910145110593090945965667009494479014398297755923139405188492083731942120741","seed":13910145110593090945965667009494479014398297755923139405188492083731942120741,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/4.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/4.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3451428133 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_error.3451428133' seed=13910145110593090945965667009494479014398297755923139405188492083731942120741 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=13910145110593090945965667009494479014398297755923139405188492083731942120741 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/4.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"4.xbar_stress_all_with_reset_error.65955078262669015328333942034384584133569916831870509916088663476653151645116","seed":65955078262669015328333942034384584133569916831870509916088663476653151645116,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/4.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/4.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2680057276 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_reset_error.2680057276' seed=65955078262669015328333942034384584133569916831870509916088663476653151645116 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=65955078262669015328333942034384584133569916831870509916088663476653151645116 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/4.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke","qual_name":"5.xbar_smoke.44751545453253219019582882703898440719488249766650203372713444412514854377814","seed":44751545453253219019582882703898440719488249766650203372713444412514854377814,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/5.xbar_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/5.xbar_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3534100822 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke.3534100822' seed=44751545453253219019582882703898440719488249766650203372713444412514854377814 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=44751545453253219019582882703898440719488249766650203372713444412514854377814 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/5.xbar_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_zero_delays","qual_name":"5.xbar_smoke_zero_delays.3179746950555491047089650814053629027662762617884145689149558714878666746376","seed":3179746950555491047089650814053629027662762617884145689149558714878666746376,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/5.xbar_smoke_zero_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/5.xbar_smoke_zero_delays/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4235995656 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_zero_delays.4235995656' seed=3179746950555491047089650814053629027662762617884145689149558714878666746376 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=3179746950555491047089650814053629027662762617884145689149558714878666746376 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/5.xbar_smoke_zero_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_large_delays","qual_name":"5.xbar_smoke_large_delays.60139289287714077323059658910655423237077015213673541818671292555761217776980","seed":60139289287714077323059658910655423237077015213673541818671292555761217776980,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/5.xbar_smoke_large_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/5.xbar_smoke_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2948410708 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_large_delays.2948410708' seed=60139289287714077323059658910655423237077015213673541818671292555761217776980 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=60139289287714077323059658910655423237077015213673541818671292555761217776980 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/5.xbar_smoke_large_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_slow_rsp","qual_name":"5.xbar_smoke_slow_rsp.92612224779401258959991245669390047589551971218804616292555438752796139309428","seed":92612224779401258959991245669390047589551971218804616292555438752796139309428,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/5.xbar_smoke_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/5.xbar_smoke_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1248053620 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_slow_rsp.1248053620' seed=92612224779401258959991245669390047589551971218804616292555438752796139309428 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=92612224779401258959991245669390047589551971218804616292555438752796139309428 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/5.xbar_smoke_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random","qual_name":"5.xbar_random.98511423516885889301470840563095234132554263338908494123585915652711366757005","seed":98511423516885889301470840563095234132554263338908494123585915652711366757005,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/5.xbar_random/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/5.xbar_random/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2936507021 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random.2936507021' seed=98511423516885889301470840563095234132554263338908494123585915652711366757005 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=98511423516885889301470840563095234132554263338908494123585915652711366757005 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/5.xbar_random/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_zero_delays","qual_name":"5.xbar_random_zero_delays.79363678026516681926427006243580381990765663149452513600042113392404342866440","seed":79363678026516681926427006243580381990765663149452513600042113392404342866440,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/5.xbar_random_zero_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/5.xbar_random_zero_delays/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=998081032 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_zero_delays.998081032' seed=79363678026516681926427006243580381990765663149452513600042113392404342866440 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=79363678026516681926427006243580381990765663149452513600042113392404342866440 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/5.xbar_random_zero_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_large_delays","qual_name":"5.xbar_random_large_delays.43705918920469396183439066101857502799387371134391403559844418281274821025807","seed":43705918920469396183439066101857502799387371134391403559844418281274821025807,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/5.xbar_random_large_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/5.xbar_random_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3120013327 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_large_delays.3120013327' seed=43705918920469396183439066101857502799387371134391403559844418281274821025807 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=43705918920469396183439066101857502799387371134391403559844418281274821025807 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/5.xbar_random_large_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_slow_rsp","qual_name":"5.xbar_random_slow_rsp.71120290125239271809424866696068513704812147565000591186778273219455122032446","seed":71120290125239271809424866696068513704812147565000591186778273219455122032446,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/5.xbar_random_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/5.xbar_random_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4251862846 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_slow_rsp.4251862846' seed=71120290125239271809424866696068513704812147565000591186778273219455122032446 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=71120290125239271809424866696068513704812147565000591186778273219455122032446 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/5.xbar_random_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device","qual_name":"5.xbar_access_same_device.6434586009373837415895837287966474203816955084400795858722088662057536586694","seed":6434586009373837415895837287966474203816955084400795858722088662057536586694,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/5.xbar_access_same_device/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/5.xbar_access_same_device/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2748187590 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device.2748187590' seed=6434586009373837415895837287966474203816955084400795858722088662057536586694 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=6434586009373837415895837287966474203816955084400795858722088662057536586694 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/5.xbar_access_same_device/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"5.xbar_access_same_device_slow_rsp.99349583625170889803440379550876371434099122066226418190412170795399485653970","seed":99349583625170889803440379550876371434099122066226418190412170795399485653970,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/5.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/5.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2639070162 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device_slow_rsp.2639070162' seed=99349583625170889803440379550876371434099122066226418190412170795399485653970 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=99349583625170889803440379550876371434099122066226418190412170795399485653970 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/5.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_same_source","qual_name":"5.xbar_same_source.99727062781530616637128089324025330745605516066578027358357346865521879004538","seed":99727062781530616637128089324025330745605516066578027358357346865521879004538,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/5.xbar_same_source/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/5.xbar_same_source/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3315709306 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_same_source.3315709306' seed=99727062781530616637128089324025330745605516066578027358357346865521879004538 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=99727062781530616637128089324025330745605516066578027358357346865521879004538 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/5.xbar_same_source/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_same_source_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_random","qual_name":"5.xbar_error_random.32856530963763452166064016692864858433776573502875880439725902040207618451143","seed":32856530963763452166064016692864858433776573502875880439725902040207618451143,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/5.xbar_error_random/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/5.xbar_error_random/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3737888455 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_error_random.3737888455' seed=32856530963763452166064016692864858433776573502875880439725902040207618451143 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=32856530963763452166064016692864858433776573502875880439725902040207618451143 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/5.xbar_error_random/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_unmapped_addr","qual_name":"5.xbar_unmapped_addr.108670864727749549401547372587448872586627726303811193932115593924701338752938","seed":108670864727749549401547372587448872586627726303811193932115593924701338752938,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/5.xbar_unmapped_addr/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/5.xbar_unmapped_addr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1208768426 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_unmapped_addr.1208768426' seed=108670864727749549401547372587448872586627726303811193932115593924701338752938 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=108670864727749549401547372587448872586627726303811193932115593924701338752938 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/5.xbar_unmapped_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_and_unmapped_addr","qual_name":"5.xbar_error_and_unmapped_addr.3355266063701534570028187402355589014482348527447002966156905937730650042712","seed":3355266063701534570028187402355589014482348527447002966156905937730650042712,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/5.xbar_error_and_unmapped_addr/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/5.xbar_error_and_unmapped_addr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=448065880 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_error_and_unmapped_addr.448065880' seed=3355266063701534570028187402355589014482348527447002966156905937730650042712 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=3355266063701534570028187402355589014482348527447002966156905937730650042712 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/5.xbar_error_and_unmapped_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all","qual_name":"5.xbar_stress_all.45566251978032193253405221933722829641759873129418941406852570219585313808478","seed":45566251978032193253405221933722829641759873129418941406852570219585313808478,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/5.xbar_stress_all/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/5.xbar_stress_all/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=438935646 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all.438935646' seed=45566251978032193253405221933722829641759873129418941406852570219585313808478 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=45566251978032193253405221933722829641759873129418941406852570219585313808478 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/5.xbar_stress_all/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_rand_reset","qual_name":"5.xbar_stress_all_with_rand_reset.68868507403082866946895419558710560395724764064112937825200109418083641206334","seed":68868507403082866946895419558710560395724764064112937825200109418083641206334,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/5.xbar_stress_all_with_rand_reset/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/5.xbar_stress_all_with_rand_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3627034174 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_rand_reset.3627034174' seed=68868507403082866946895419558710560395724764064112937825200109418083641206334 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=68868507403082866946895419558710560395724764064112937825200109418083641206334 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/5.xbar_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"5.xbar_stress_all_with_error.101684285889133494305975261075151755781625439156873804803946298392033932543594","seed":101684285889133494305975261075151755781625439156873804803946298392033932543594,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/5.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/5.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4257416810 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_error.4257416810' seed=101684285889133494305975261075151755781625439156873804803946298392033932543594 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=101684285889133494305975261075151755781625439156873804803946298392033932543594 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/5.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"5.xbar_stress_all_with_reset_error.43789550836992799686943295665448319834031520623778787667825050721511312979975","seed":43789550836992799686943295665448319834031520623778787667825050721511312979975,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/5.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/5.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1600911367 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_reset_error.1600911367' seed=43789550836992799686943295665448319834031520623778787667825050721511312979975 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=43789550836992799686943295665448319834031520623778787667825050721511312979975 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/5.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke","qual_name":"6.xbar_smoke.114434526021287952235213014411386800350533454821391177501308295258365885867581","seed":114434526021287952235213014411386800350533454821391177501308295258365885867581,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/6.xbar_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/6.xbar_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1543956029 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke.1543956029' seed=114434526021287952235213014411386800350533454821391177501308295258365885867581 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=114434526021287952235213014411386800350533454821391177501308295258365885867581 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/6.xbar_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_zero_delays","qual_name":"6.xbar_smoke_zero_delays.7339908768464138962742826175218301938713044900742779796580349464485102539379","seed":7339908768464138962742826175218301938713044900742779796580349464485102539379,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/6.xbar_smoke_zero_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/6.xbar_smoke_zero_delays/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3543585395 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_zero_delays.3543585395' seed=7339908768464138962742826175218301938713044900742779796580349464485102539379 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=7339908768464138962742826175218301938713044900742779796580349464485102539379 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/6.xbar_smoke_zero_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_large_delays","qual_name":"6.xbar_smoke_large_delays.71510050044528275154931949756847853993616431319301752313491645041277841590976","seed":71510050044528275154931949756847853993616431319301752313491645041277841590976,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/6.xbar_smoke_large_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/6.xbar_smoke_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2644658880 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_large_delays.2644658880' seed=71510050044528275154931949756847853993616431319301752313491645041277841590976 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=71510050044528275154931949756847853993616431319301752313491645041277841590976 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/6.xbar_smoke_large_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_slow_rsp","qual_name":"6.xbar_smoke_slow_rsp.81452913011645788056911042748965261123341409776550775968050869575357151747777","seed":81452913011645788056911042748965261123341409776550775968050869575357151747777,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/6.xbar_smoke_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/6.xbar_smoke_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1912512193 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_slow_rsp.1912512193' seed=81452913011645788056911042748965261123341409776550775968050869575357151747777 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=81452913011645788056911042748965261123341409776550775968050869575357151747777 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/6.xbar_smoke_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random","qual_name":"6.xbar_random.34700429842841001409961853000692157568939795231382844787822348096384674984756","seed":34700429842841001409961853000692157568939795231382844787822348096384674984756,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/6.xbar_random/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/6.xbar_random/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3911086900 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random.3911086900' seed=34700429842841001409961853000692157568939795231382844787822348096384674984756 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=34700429842841001409961853000692157568939795231382844787822348096384674984756 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/6.xbar_random/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_zero_delays","qual_name":"6.xbar_random_zero_delays.61221572625189195131106107251816819641438043724914224815045574933289397551185","seed":61221572625189195131106107251816819641438043724914224815045574933289397551185,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/6.xbar_random_zero_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/6.xbar_random_zero_delays/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=805994577 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_zero_delays.805994577' seed=61221572625189195131106107251816819641438043724914224815045574933289397551185 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=61221572625189195131106107251816819641438043724914224815045574933289397551185 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/6.xbar_random_zero_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_large_delays","qual_name":"6.xbar_random_large_delays.83682708193106559196666853066744962111826702559220315074215786250907022358658","seed":83682708193106559196666853066744962111826702559220315074215786250907022358658,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/6.xbar_random_large_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/6.xbar_random_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3953227906 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_large_delays.3953227906' seed=83682708193106559196666853066744962111826702559220315074215786250907022358658 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=83682708193106559196666853066744962111826702559220315074215786250907022358658 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/6.xbar_random_large_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_slow_rsp","qual_name":"6.xbar_random_slow_rsp.34193567924576797595678970129157067956011420458844294814516762777604510306770","seed":34193567924576797595678970129157067956011420458844294814516762777604510306770,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/6.xbar_random_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/6.xbar_random_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=734384594 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_slow_rsp.734384594' seed=34193567924576797595678970129157067956011420458844294814516762777604510306770 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=34193567924576797595678970129157067956011420458844294814516762777604510306770 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/6.xbar_random_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device","qual_name":"6.xbar_access_same_device.29474500198796591126973887532898671572470804422188738731394781655559234785990","seed":29474500198796591126973887532898671572470804422188738731394781655559234785990,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/6.xbar_access_same_device/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/6.xbar_access_same_device/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1303253702 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device.1303253702' seed=29474500198796591126973887532898671572470804422188738731394781655559234785990 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=29474500198796591126973887532898671572470804422188738731394781655559234785990 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/6.xbar_access_same_device/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"6.xbar_access_same_device_slow_rsp.50722088319391223613004770606346139229756029149839392620703958383105455051652","seed":50722088319391223613004770606346139229756029149839392620703958383105455051652,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/6.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/6.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1182684036 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device_slow_rsp.1182684036' seed=50722088319391223613004770606346139229756029149839392620703958383105455051652 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=50722088319391223613004770606346139229756029149839392620703958383105455051652 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/6.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_same_source","qual_name":"6.xbar_same_source.108504015930752326355367024884324646096893361320083003002528248890809978721559","seed":108504015930752326355367024884324646096893361320083003002528248890809978721559,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/6.xbar_same_source/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/6.xbar_same_source/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2468615447 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_same_source.2468615447' seed=108504015930752326355367024884324646096893361320083003002528248890809978721559 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=108504015930752326355367024884324646096893361320083003002528248890809978721559 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/6.xbar_same_source/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_same_source_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_random","qual_name":"6.xbar_error_random.87150541296426160343475590136659826811345362422132980457112673209345448706957","seed":87150541296426160343475590136659826811345362422132980457112673209345448706957,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/6.xbar_error_random/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/6.xbar_error_random/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1381073805 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_error_random.1381073805' seed=87150541296426160343475590136659826811345362422132980457112673209345448706957 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=87150541296426160343475590136659826811345362422132980457112673209345448706957 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/6.xbar_error_random/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_unmapped_addr","qual_name":"6.xbar_unmapped_addr.65367525120005966438400089737469831238443681122030687514136822044906226845771","seed":65367525120005966438400089737469831238443681122030687514136822044906226845771,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/6.xbar_unmapped_addr/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/6.xbar_unmapped_addr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1248987211 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_unmapped_addr.1248987211' seed=65367525120005966438400089737469831238443681122030687514136822044906226845771 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=65367525120005966438400089737469831238443681122030687514136822044906226845771 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/6.xbar_unmapped_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_and_unmapped_addr","qual_name":"6.xbar_error_and_unmapped_addr.76023450768029675918267060444993778882870890634013311364678597019303521929968","seed":76023450768029675918267060444993778882870890634013311364678597019303521929968,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/6.xbar_error_and_unmapped_addr/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/6.xbar_error_and_unmapped_addr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1943128816 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_error_and_unmapped_addr.1943128816' seed=76023450768029675918267060444993778882870890634013311364678597019303521929968 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=76023450768029675918267060444993778882870890634013311364678597019303521929968 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/6.xbar_error_and_unmapped_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all","qual_name":"6.xbar_stress_all.52671630782127556212511920856133232706881712508584497130786469812543781499689","seed":52671630782127556212511920856133232706881712508584497130786469812543781499689,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/6.xbar_stress_all/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/6.xbar_stress_all/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3328602921 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all.3328602921' seed=52671630782127556212511920856133232706881712508584497130786469812543781499689 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=52671630782127556212511920856133232706881712508584497130786469812543781499689 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/6.xbar_stress_all/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_rand_reset","qual_name":"6.xbar_stress_all_with_rand_reset.69700816114531579875021202747419913805512176685914106413899306234411780200784","seed":69700816114531579875021202747419913805512176685914106413899306234411780200784,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/6.xbar_stress_all_with_rand_reset/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/6.xbar_stress_all_with_rand_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1786042704 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_rand_reset.1786042704' seed=69700816114531579875021202747419913805512176685914106413899306234411780200784 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=69700816114531579875021202747419913805512176685914106413899306234411780200784 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/6.xbar_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"6.xbar_stress_all_with_error.45380452345266918035152159051674478817014850571652306568038437660854700973317","seed":45380452345266918035152159051674478817014850571652306568038437660854700973317,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/6.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/6.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1583586565 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_error.1583586565' seed=45380452345266918035152159051674478817014850571652306568038437660854700973317 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=45380452345266918035152159051674478817014850571652306568038437660854700973317 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/6.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"6.xbar_stress_all_with_reset_error.79002138557217681028464670631487251643317623462504535152994191187042740273605","seed":79002138557217681028464670631487251643317623462504535152994191187042740273605,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/6.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/6.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=276365765 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_reset_error.276365765' seed=79002138557217681028464670631487251643317623462504535152994191187042740273605 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=79002138557217681028464670631487251643317623462504535152994191187042740273605 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/6.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke","qual_name":"7.xbar_smoke.12265006144111857689217907020598282330842997338432285948367950234797554512456","seed":12265006144111857689217907020598282330842997338432285948367950234797554512456,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/7.xbar_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/7.xbar_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=659534408 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke.659534408' seed=12265006144111857689217907020598282330842997338432285948367950234797554512456 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=12265006144111857689217907020598282330842997338432285948367950234797554512456 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/7.xbar_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_zero_delays","qual_name":"7.xbar_smoke_zero_delays.19894641436440371273586080001310281956594094337841753112639704500632055416966","seed":19894641436440371273586080001310281956594094337841753112639704500632055416966,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/7.xbar_smoke_zero_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/7.xbar_smoke_zero_delays/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3478096006 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_zero_delays.3478096006' seed=19894641436440371273586080001310281956594094337841753112639704500632055416966 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=19894641436440371273586080001310281956594094337841753112639704500632055416966 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/7.xbar_smoke_zero_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_large_delays","qual_name":"7.xbar_smoke_large_delays.5937270296009627310174046197516427946604817969205689250542058726824144220791","seed":5937270296009627310174046197516427946604817969205689250542058726824144220791,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/7.xbar_smoke_large_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/7.xbar_smoke_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1793012343 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_large_delays.1793012343' seed=5937270296009627310174046197516427946604817969205689250542058726824144220791 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=5937270296009627310174046197516427946604817969205689250542058726824144220791 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/7.xbar_smoke_large_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_slow_rsp","qual_name":"7.xbar_smoke_slow_rsp.32490601372113475449267231185377590349129246306699441450111980756714014560054","seed":32490601372113475449267231185377590349129246306699441450111980756714014560054,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/7.xbar_smoke_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/7.xbar_smoke_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=948358966 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_slow_rsp.948358966' seed=32490601372113475449267231185377590349129246306699441450111980756714014560054 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=32490601372113475449267231185377590349129246306699441450111980756714014560054 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/7.xbar_smoke_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random","qual_name":"7.xbar_random.52642976179387368599847883840694936824625646847369206826968922664044078454767","seed":52642976179387368599847883840694936824625646847369206826968922664044078454767,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/7.xbar_random/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/7.xbar_random/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=984766447 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random.984766447' seed=52642976179387368599847883840694936824625646847369206826968922664044078454767 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=52642976179387368599847883840694936824625646847369206826968922664044078454767 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/7.xbar_random/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_zero_delays","qual_name":"7.xbar_random_zero_delays.90714320836087037238678423983560473841725291915156865182983050787192549581009","seed":90714320836087037238678423983560473841725291915156865182983050787192549581009,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/7.xbar_random_zero_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/7.xbar_random_zero_delays/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3804930257 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_zero_delays.3804930257' seed=90714320836087037238678423983560473841725291915156865182983050787192549581009 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=90714320836087037238678423983560473841725291915156865182983050787192549581009 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/7.xbar_random_zero_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_large_delays","qual_name":"7.xbar_random_large_delays.76382064944396220210659203026857557237659029645475511749713174046470118263304","seed":76382064944396220210659203026857557237659029645475511749713174046470118263304,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/7.xbar_random_large_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/7.xbar_random_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1349732872 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_large_delays.1349732872' seed=76382064944396220210659203026857557237659029645475511749713174046470118263304 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=76382064944396220210659203026857557237659029645475511749713174046470118263304 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/7.xbar_random_large_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_slow_rsp","qual_name":"7.xbar_random_slow_rsp.64696942296407696534464911580105964349631318712447670095318588370536680357576","seed":64696942296407696534464911580105964349631318712447670095318588370536680357576,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/7.xbar_random_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/7.xbar_random_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3300622024 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_slow_rsp.3300622024' seed=64696942296407696534464911580105964349631318712447670095318588370536680357576 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=64696942296407696534464911580105964349631318712447670095318588370536680357576 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/7.xbar_random_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device","qual_name":"7.xbar_access_same_device.107933554215227903656156425031422843094892067205618506486459134020644266033973","seed":107933554215227903656156425031422843094892067205618506486459134020644266033973,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/7.xbar_access_same_device/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/7.xbar_access_same_device/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=739754805 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device.739754805' seed=107933554215227903656156425031422843094892067205618506486459134020644266033973 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=107933554215227903656156425031422843094892067205618506486459134020644266033973 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/7.xbar_access_same_device/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"7.xbar_access_same_device_slow_rsp.36610141966487836563361069551027879089813781800783581122945741846156200640874","seed":36610141966487836563361069551027879089813781800783581122945741846156200640874,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/7.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/7.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=129499498 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device_slow_rsp.129499498' seed=36610141966487836563361069551027879089813781800783581122945741846156200640874 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=36610141966487836563361069551027879089813781800783581122945741846156200640874 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/7.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_same_source","qual_name":"7.xbar_same_source.94490891080663855645347716877083749526021734912263774932594959701550205864659","seed":94490891080663855645347716877083749526021734912263774932594959701550205864659,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/7.xbar_same_source/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/7.xbar_same_source/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2834402003 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_same_source.2834402003' seed=94490891080663855645347716877083749526021734912263774932594959701550205864659 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=94490891080663855645347716877083749526021734912263774932594959701550205864659 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/7.xbar_same_source/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_same_source_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_random","qual_name":"7.xbar_error_random.159692411959900262262308276073972170502693954035475723133772941882530572181","seed":159692411959900262262308276073972170502693954035475723133772941882530572181,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/7.xbar_error_random/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/7.xbar_error_random/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2887100309 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_error_random.2887100309' seed=159692411959900262262308276073972170502693954035475723133772941882530572181 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=159692411959900262262308276073972170502693954035475723133772941882530572181 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/7.xbar_error_random/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_unmapped_addr","qual_name":"7.xbar_unmapped_addr.11515419524196565845773507974857779858772393825669578927150526526141931227081","seed":11515419524196565845773507974857779858772393825669578927150526526141931227081,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/7.xbar_unmapped_addr/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/7.xbar_unmapped_addr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3401353161 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_unmapped_addr.3401353161' seed=11515419524196565845773507974857779858772393825669578927150526526141931227081 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=11515419524196565845773507974857779858772393825669578927150526526141931227081 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/7.xbar_unmapped_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_and_unmapped_addr","qual_name":"7.xbar_error_and_unmapped_addr.5223079370270536933812643220757855579059660977743551697463027181644836499505","seed":5223079370270536933812643220757855579059660977743551697463027181644836499505,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/7.xbar_error_and_unmapped_addr/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/7.xbar_error_and_unmapped_addr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3680497713 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_error_and_unmapped_addr.3680497713' seed=5223079370270536933812643220757855579059660977743551697463027181644836499505 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=5223079370270536933812643220757855579059660977743551697463027181644836499505 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/7.xbar_error_and_unmapped_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all","qual_name":"7.xbar_stress_all.21090406155173109423511867573360719765951240908986315838438268559031015715105","seed":21090406155173109423511867573360719765951240908986315838438268559031015715105,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/7.xbar_stress_all/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/7.xbar_stress_all/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3703714081 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all.3703714081' seed=21090406155173109423511867573360719765951240908986315838438268559031015715105 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=21090406155173109423511867573360719765951240908986315838438268559031015715105 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/7.xbar_stress_all/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_rand_reset","qual_name":"7.xbar_stress_all_with_rand_reset.95191592378812579267327896014220863552402919698921788360005410993196815572077","seed":95191592378812579267327896014220863552402919698921788360005410993196815572077,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/7.xbar_stress_all_with_rand_reset/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/7.xbar_stress_all_with_rand_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2671729773 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_rand_reset.2671729773' seed=95191592378812579267327896014220863552402919698921788360005410993196815572077 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=95191592378812579267327896014220863552402919698921788360005410993196815572077 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/7.xbar_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"7.xbar_stress_all_with_error.11956247711350750594978354754431166241596030455736141866167235335754542229092","seed":11956247711350750594978354754431166241596030455736141866167235335754542229092,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/7.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/7.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3974899300 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_error.3974899300' seed=11956247711350750594978354754431166241596030455736141866167235335754542229092 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=11956247711350750594978354754431166241596030455736141866167235335754542229092 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/7.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"7.xbar_stress_all_with_reset_error.9418971320819118021276250667612358062592564365281388720039233652590275924071","seed":9418971320819118021276250667612358062592564365281388720039233652590275924071,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/7.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/7.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2323320935 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_reset_error.2323320935' seed=9418971320819118021276250667612358062592564365281388720039233652590275924071 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=9418971320819118021276250667612358062592564365281388720039233652590275924071 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/7.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke","qual_name":"8.xbar_smoke.102324706682571374784927090185403380116947020413926944517411311269347473924122","seed":102324706682571374784927090185403380116947020413926944517411311269347473924122,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/8.xbar_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/8.xbar_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4233273370 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke.4233273370' seed=102324706682571374784927090185403380116947020413926944517411311269347473924122 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=102324706682571374784927090185403380116947020413926944517411311269347473924122 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/8.xbar_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_zero_delays","qual_name":"8.xbar_smoke_zero_delays.105968587705929562598600325543169848854391911126334444845237048168928987436435","seed":105968587705929562598600325543169848854391911126334444845237048168928987436435,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/8.xbar_smoke_zero_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/8.xbar_smoke_zero_delays/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4147500435 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_zero_delays.4147500435' seed=105968587705929562598600325543169848854391911126334444845237048168928987436435 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=105968587705929562598600325543169848854391911126334444845237048168928987436435 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/8.xbar_smoke_zero_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_large_delays","qual_name":"8.xbar_smoke_large_delays.1666558028876697663761603273484708413482809435006458516511078964961182248147","seed":1666558028876697663761603273484708413482809435006458516511078964961182248147,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/8.xbar_smoke_large_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/8.xbar_smoke_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3524553939 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_large_delays.3524553939' seed=1666558028876697663761603273484708413482809435006458516511078964961182248147 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=1666558028876697663761603273484708413482809435006458516511078964961182248147 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/8.xbar_smoke_large_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_slow_rsp","qual_name":"8.xbar_smoke_slow_rsp.75828424782396950816927907630231709955727285226452639242086126309098122920087","seed":75828424782396950816927907630231709955727285226452639242086126309098122920087,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/8.xbar_smoke_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/8.xbar_smoke_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1264337047 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_slow_rsp.1264337047' seed=75828424782396950816927907630231709955727285226452639242086126309098122920087 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=75828424782396950816927907630231709955727285226452639242086126309098122920087 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/8.xbar_smoke_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random","qual_name":"8.xbar_random.67188971214175932659159247273204494837181571236913125195000963687454317466574","seed":67188971214175932659159247273204494837181571236913125195000963687454317466574,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/8.xbar_random/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/8.xbar_random/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3724006350 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random.3724006350' seed=67188971214175932659159247273204494837181571236913125195000963687454317466574 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=67188971214175932659159247273204494837181571236913125195000963687454317466574 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/8.xbar_random/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_zero_delays","qual_name":"8.xbar_random_zero_delays.102671276913596316719160926828998949335007145115330093680701564474962248880164","seed":102671276913596316719160926828998949335007145115330093680701564474962248880164,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/8.xbar_random_zero_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/8.xbar_random_zero_delays/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3427160100 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_zero_delays.3427160100' seed=102671276913596316719160926828998949335007145115330093680701564474962248880164 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=102671276913596316719160926828998949335007145115330093680701564474962248880164 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/8.xbar_random_zero_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_large_delays","qual_name":"8.xbar_random_large_delays.13560088792804154468505968509184899541977085187715067717973881537487354637150","seed":13560088792804154468505968509184899541977085187715067717973881537487354637150,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/8.xbar_random_large_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/8.xbar_random_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=774548318 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_large_delays.774548318' seed=13560088792804154468505968509184899541977085187715067717973881537487354637150 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=13560088792804154468505968509184899541977085187715067717973881537487354637150 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/8.xbar_random_large_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_slow_rsp","qual_name":"8.xbar_random_slow_rsp.4426407495655910665811270350070238804144160037338911914975623270558950476172","seed":4426407495655910665811270350070238804144160037338911914975623270558950476172,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/8.xbar_random_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/8.xbar_random_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1162856844 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_slow_rsp.1162856844' seed=4426407495655910665811270350070238804144160037338911914975623270558950476172 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=4426407495655910665811270350070238804144160037338911914975623270558950476172 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/8.xbar_random_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device","qual_name":"8.xbar_access_same_device.49671824209570015687938920809714640527114267973709876842545975061518499067887","seed":49671824209570015687938920809714640527114267973709876842545975061518499067887,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/8.xbar_access_same_device/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/8.xbar_access_same_device/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1047410671 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device.1047410671' seed=49671824209570015687938920809714640527114267973709876842545975061518499067887 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=49671824209570015687938920809714640527114267973709876842545975061518499067887 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/8.xbar_access_same_device/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"8.xbar_access_same_device_slow_rsp.101969962824848870968861628767540040306970139283038739316444095907273886891714","seed":101969962824848870968861628767540040306970139283038739316444095907273886891714,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/8.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/8.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1633124034 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device_slow_rsp.1633124034' seed=101969962824848870968861628767540040306970139283038739316444095907273886891714 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=101969962824848870968861628767540040306970139283038739316444095907273886891714 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/8.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_same_source","qual_name":"8.xbar_same_source.29145354519251211872966015131890650259416891178384849298295512174758863931534","seed":29145354519251211872966015131890650259416891178384849298295512174758863931534,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/8.xbar_same_source/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/8.xbar_same_source/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1081968782 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_same_source.1081968782' seed=29145354519251211872966015131890650259416891178384849298295512174758863931534 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=29145354519251211872966015131890650259416891178384849298295512174758863931534 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/8.xbar_same_source/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_same_source_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_random","qual_name":"8.xbar_error_random.31576163258438401113817892908158358420834346119149801580179071894580950697904","seed":31576163258438401113817892908158358420834346119149801580179071894580950697904,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/8.xbar_error_random/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/8.xbar_error_random/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2235795376 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_error_random.2235795376' seed=31576163258438401113817892908158358420834346119149801580179071894580950697904 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=31576163258438401113817892908158358420834346119149801580179071894580950697904 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/8.xbar_error_random/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_unmapped_addr","qual_name":"8.xbar_unmapped_addr.112073452088169979899305916479954034829860066244701794705166920593406702827497","seed":112073452088169979899305916479954034829860066244701794705166920593406702827497,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/8.xbar_unmapped_addr/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/8.xbar_unmapped_addr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2962143209 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_unmapped_addr.2962143209' seed=112073452088169979899305916479954034829860066244701794705166920593406702827497 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=112073452088169979899305916479954034829860066244701794705166920593406702827497 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/8.xbar_unmapped_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_and_unmapped_addr","qual_name":"8.xbar_error_and_unmapped_addr.80334761893204718411350251792818086761318918347383147344437471539202967692692","seed":80334761893204718411350251792818086761318918347383147344437471539202967692692,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/8.xbar_error_and_unmapped_addr/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/8.xbar_error_and_unmapped_addr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1380148628 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_error_and_unmapped_addr.1380148628' seed=80334761893204718411350251792818086761318918347383147344437471539202967692692 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=80334761893204718411350251792818086761318918347383147344437471539202967692692 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/8.xbar_error_and_unmapped_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all","qual_name":"8.xbar_stress_all.22801209310440477529966684660778594056365716868202960448507115102719933005930","seed":22801209310440477529966684660778594056365716868202960448507115102719933005930,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/8.xbar_stress_all/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/8.xbar_stress_all/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1230356586 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all.1230356586' seed=22801209310440477529966684660778594056365716868202960448507115102719933005930 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=22801209310440477529966684660778594056365716868202960448507115102719933005930 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/8.xbar_stress_all/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_rand_reset","qual_name":"8.xbar_stress_all_with_rand_reset.11670405853714372901115336076789110987597897553597722471868648686968673765515","seed":11670405853714372901115336076789110987597897553597722471868648686968673765515,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/8.xbar_stress_all_with_rand_reset/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/8.xbar_stress_all_with_rand_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4087974027 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_rand_reset.4087974027' seed=11670405853714372901115336076789110987597897553597722471868648686968673765515 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=11670405853714372901115336076789110987597897553597722471868648686968673765515 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/8.xbar_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"8.xbar_stress_all_with_error.102261031940053149312639286015294194638592307928009496360772953530410580658055","seed":102261031940053149312639286015294194638592307928009496360772953530410580658055,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/8.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/8.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=801195911 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_error.801195911' seed=102261031940053149312639286015294194638592307928009496360772953530410580658055 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=102261031940053149312639286015294194638592307928009496360772953530410580658055 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/8.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"8.xbar_stress_all_with_reset_error.12777311568095311010709959484640345725225495062444993555231160238496740198827","seed":12777311568095311010709959484640345725225495062444993555231160238496740198827,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/8.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/8.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1722206635 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_reset_error.1722206635' seed=12777311568095311010709959484640345725225495062444993555231160238496740198827 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=12777311568095311010709959484640345725225495062444993555231160238496740198827 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/8.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke","qual_name":"9.xbar_smoke.59187234338843432421876942812417107505476997207436552165463169960734771504959","seed":59187234338843432421876942812417107505476997207436552165463169960734771504959,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/9.xbar_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/9.xbar_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2295195455 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke.2295195455' seed=59187234338843432421876942812417107505476997207436552165463169960734771504959 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=59187234338843432421876942812417107505476997207436552165463169960734771504959 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/9.xbar_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_zero_delays","qual_name":"9.xbar_smoke_zero_delays.58251439845327856191650772791864968493459607283276136941513103835723787189965","seed":58251439845327856191650772791864968493459607283276136941513103835723787189965,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/9.xbar_smoke_zero_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/9.xbar_smoke_zero_delays/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2430123725 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_zero_delays.2430123725' seed=58251439845327856191650772791864968493459607283276136941513103835723787189965 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=58251439845327856191650772791864968493459607283276136941513103835723787189965 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/9.xbar_smoke_zero_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_large_delays","qual_name":"9.xbar_smoke_large_delays.91576081151847862692081411489255396713529009634576855875456281127775986341798","seed":91576081151847862692081411489255396713529009634576855875456281127775986341798,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/9.xbar_smoke_large_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/9.xbar_smoke_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1445549990 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_large_delays.1445549990' seed=91576081151847862692081411489255396713529009634576855875456281127775986341798 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=91576081151847862692081411489255396713529009634576855875456281127775986341798 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/9.xbar_smoke_large_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_slow_rsp","qual_name":"9.xbar_smoke_slow_rsp.64549228739520601958361687978016007621094822146740457514322088159964265631300","seed":64549228739520601958361687978016007621094822146740457514322088159964265631300,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/9.xbar_smoke_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/9.xbar_smoke_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1266601540 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_slow_rsp.1266601540' seed=64549228739520601958361687978016007621094822146740457514322088159964265631300 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=64549228739520601958361687978016007621094822146740457514322088159964265631300 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/9.xbar_smoke_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random","qual_name":"9.xbar_random.80035953614130699705468872026532090311186119337951773513704330992855340734226","seed":80035953614130699705468872026532090311186119337951773513704330992855340734226,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/9.xbar_random/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/9.xbar_random/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1013372690 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random.1013372690' seed=80035953614130699705468872026532090311186119337951773513704330992855340734226 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=80035953614130699705468872026532090311186119337951773513704330992855340734226 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/9.xbar_random/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_zero_delays","qual_name":"9.xbar_random_zero_delays.95148277537833171498738577708581755207073582344454705964899031703576212611271","seed":95148277537833171498738577708581755207073582344454705964899031703576212611271,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/9.xbar_random_zero_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/9.xbar_random_zero_delays/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=99557575 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_zero_delays.99557575' seed=95148277537833171498738577708581755207073582344454705964899031703576212611271 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=95148277537833171498738577708581755207073582344454705964899031703576212611271 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/9.xbar_random_zero_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_large_delays","qual_name":"9.xbar_random_large_delays.19940766583098235379437282247868804979587648940532761042319445525767415430614","seed":19940766583098235379437282247868804979587648940532761042319445525767415430614,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/9.xbar_random_large_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/9.xbar_random_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=99646934 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_large_delays.99646934' seed=19940766583098235379437282247868804979587648940532761042319445525767415430614 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=19940766583098235379437282247868804979587648940532761042319445525767415430614 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/9.xbar_random_large_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_slow_rsp","qual_name":"9.xbar_random_slow_rsp.1090272598718031976134737121115968159408428933812334735085482027372892357828","seed":1090272598718031976134737121115968159408428933812334735085482027372892357828,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/9.xbar_random_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/9.xbar_random_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1826063556 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_slow_rsp.1826063556' seed=1090272598718031976134737121115968159408428933812334735085482027372892357828 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=1090272598718031976134737121115968159408428933812334735085482027372892357828 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/9.xbar_random_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device","qual_name":"9.xbar_access_same_device.31358632864078097451962801393871381395357886099819526373015695427108824822337","seed":31358632864078097451962801393871381395357886099819526373015695427108824822337,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/9.xbar_access_same_device/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/9.xbar_access_same_device/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1353331265 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device.1353331265' seed=31358632864078097451962801393871381395357886099819526373015695427108824822337 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=31358632864078097451962801393871381395357886099819526373015695427108824822337 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/9.xbar_access_same_device/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"9.xbar_access_same_device_slow_rsp.88243176301924342995412523315081563792321119304908267593114891199483366011068","seed":88243176301924342995412523315081563792321119304908267593114891199483366011068,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/9.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/9.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1546842300 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device_slow_rsp.1546842300' seed=88243176301924342995412523315081563792321119304908267593114891199483366011068 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=88243176301924342995412523315081563792321119304908267593114891199483366011068 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/9.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_same_source","qual_name":"9.xbar_same_source.84037387677850373753732840677088795376679210653828925682349663149782390353430","seed":84037387677850373753732840677088795376679210653828925682349663149782390353430,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/9.xbar_same_source/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/9.xbar_same_source/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1389702678 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_same_source.1389702678' seed=84037387677850373753732840677088795376679210653828925682349663149782390353430 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=84037387677850373753732840677088795376679210653828925682349663149782390353430 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/9.xbar_same_source/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_same_source_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_random","qual_name":"9.xbar_error_random.31974868170630999700053156878039664053579747575103158952102718588745165771553","seed":31974868170630999700053156878039664053579747575103158952102718588745165771553,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/9.xbar_error_random/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/9.xbar_error_random/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=436933409 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_error_random.436933409' seed=31974868170630999700053156878039664053579747575103158952102718588745165771553 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=31974868170630999700053156878039664053579747575103158952102718588745165771553 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/9.xbar_error_random/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_unmapped_addr","qual_name":"9.xbar_unmapped_addr.16360913526704451879963071951628261667716633360208117208970294266617782922896","seed":16360913526704451879963071951628261667716633360208117208970294266617782922896,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/9.xbar_unmapped_addr/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/9.xbar_unmapped_addr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1042083472 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_unmapped_addr.1042083472' seed=16360913526704451879963071951628261667716633360208117208970294266617782922896 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=16360913526704451879963071951628261667716633360208117208970294266617782922896 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/9.xbar_unmapped_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_and_unmapped_addr","qual_name":"9.xbar_error_and_unmapped_addr.74674599936423900138312526219924050970311562856470003998036994570749780037015","seed":74674599936423900138312526219924050970311562856470003998036994570749780037015,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/9.xbar_error_and_unmapped_addr/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/9.xbar_error_and_unmapped_addr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=359796119 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_error_and_unmapped_addr.359796119' seed=74674599936423900138312526219924050970311562856470003998036994570749780037015 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=74674599936423900138312526219924050970311562856470003998036994570749780037015 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/9.xbar_error_and_unmapped_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all","qual_name":"9.xbar_stress_all.6573199466338349099326265293473302984285594528113593399018644381208588597560","seed":6573199466338349099326265293473302984285594528113593399018644381208588597560,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/9.xbar_stress_all/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/9.xbar_stress_all/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2806266168 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all.2806266168' seed=6573199466338349099326265293473302984285594528113593399018644381208588597560 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=6573199466338349099326265293473302984285594528113593399018644381208588597560 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/9.xbar_stress_all/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_rand_reset","qual_name":"9.xbar_stress_all_with_rand_reset.91235125627012695706688788709549755882703940352272455900520401955766574208310","seed":91235125627012695706688788709549755882703940352272455900520401955766574208310,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/9.xbar_stress_all_with_rand_reset/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/9.xbar_stress_all_with_rand_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=783504694 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_rand_reset.783504694' seed=91235125627012695706688788709549755882703940352272455900520401955766574208310 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=91235125627012695706688788709549755882703940352272455900520401955766574208310 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/9.xbar_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"9.xbar_stress_all_with_error.41308693986136302432046711569756843673133856757685845120411587783017649873753","seed":41308693986136302432046711569756843673133856757685845120411587783017649873753,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/9.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/9.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3784516441 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_error.3784516441' seed=41308693986136302432046711569756843673133856757685845120411587783017649873753 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=41308693986136302432046711569756843673133856757685845120411587783017649873753 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/9.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"9.xbar_stress_all_with_reset_error.99065648951070323283655718685204355142391006243332365428014457836390179566605","seed":99065648951070323283655718685204355142391006243332365428014457836390179566605,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/9.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/9.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4057887757 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_reset_error.4057887757' seed=99065648951070323283655718685204355142391006243332365428014457836390179566605 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=99065648951070323283655718685204355142391006243332365428014457836390179566605 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/9.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke","qual_name":"10.xbar_smoke.18445318766071625257957605516378982470416726741291085354676830293447105010893","seed":18445318766071625257957605516378982470416726741291085354676830293447105010893,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/10.xbar_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/10.xbar_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=5725389 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke.5725389' seed=18445318766071625257957605516378982470416726741291085354676830293447105010893 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=18445318766071625257957605516378982470416726741291085354676830293447105010893 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/10.xbar_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_zero_delays","qual_name":"10.xbar_smoke_zero_delays.22182615389395128045426248528988827372325642456339207708942946132070943133550","seed":22182615389395128045426248528988827372325642456339207708942946132070943133550,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/10.xbar_smoke_zero_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/10.xbar_smoke_zero_delays/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=446926702 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_zero_delays.446926702' seed=22182615389395128045426248528988827372325642456339207708942946132070943133550 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=22182615389395128045426248528988827372325642456339207708942946132070943133550 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/10.xbar_smoke_zero_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_large_delays","qual_name":"10.xbar_smoke_large_delays.16969414255201999391682785245614000347064663644637751563854939225155461551312","seed":16969414255201999391682785245614000347064663644637751563854939225155461551312,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/10.xbar_smoke_large_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/10.xbar_smoke_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=333288656 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_large_delays.333288656' seed=16969414255201999391682785245614000347064663644637751563854939225155461551312 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=16969414255201999391682785245614000347064663644637751563854939225155461551312 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/10.xbar_smoke_large_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_slow_rsp","qual_name":"10.xbar_smoke_slow_rsp.35594137533601085723590298336088356039076612063303759458361160096919502082229","seed":35594137533601085723590298336088356039076612063303759458361160096919502082229,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/10.xbar_smoke_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/10.xbar_smoke_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3587330229 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_slow_rsp.3587330229' seed=35594137533601085723590298336088356039076612063303759458361160096919502082229 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=35594137533601085723590298336088356039076612063303759458361160096919502082229 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/10.xbar_smoke_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random","qual_name":"10.xbar_random.1079772094492665225318982604865191530560578097407434515630338626288448789929","seed":1079772094492665225318982604865191530560578097407434515630338626288448789929,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/10.xbar_random/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/10.xbar_random/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2291228073 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random.2291228073' seed=1079772094492665225318982604865191530560578097407434515630338626288448789929 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=1079772094492665225318982604865191530560578097407434515630338626288448789929 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/10.xbar_random/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_zero_delays","qual_name":"10.xbar_random_zero_delays.77002667837255343762314333542275301094809749569239558615823709169581358991525","seed":77002667837255343762314333542275301094809749569239558615823709169581358991525,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/10.xbar_random_zero_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/10.xbar_random_zero_delays/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3511044261 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_zero_delays.3511044261' seed=77002667837255343762314333542275301094809749569239558615823709169581358991525 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=77002667837255343762314333542275301094809749569239558615823709169581358991525 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/10.xbar_random_zero_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_large_delays","qual_name":"10.xbar_random_large_delays.70017465954608518371357341326436176703582686236726743012564519123631085893629","seed":70017465954608518371357341326436176703582686236726743012564519123631085893629,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/10.xbar_random_large_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/10.xbar_random_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2553460733 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_large_delays.2553460733' seed=70017465954608518371357341326436176703582686236726743012564519123631085893629 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=70017465954608518371357341326436176703582686236726743012564519123631085893629 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/10.xbar_random_large_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_slow_rsp","qual_name":"10.xbar_random_slow_rsp.109032679045272134230554763585521629310439600638567666364511076287364461092108","seed":109032679045272134230554763585521629310439600638567666364511076287364461092108,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/10.xbar_random_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/10.xbar_random_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=162127116 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_slow_rsp.162127116' seed=109032679045272134230554763585521629310439600638567666364511076287364461092108 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=109032679045272134230554763585521629310439600638567666364511076287364461092108 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/10.xbar_random_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device","qual_name":"10.xbar_access_same_device.101291020127929641398356002221804993824060503044499995518341937095762004782793","seed":101291020127929641398356002221804993824060503044499995518341937095762004782793,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/10.xbar_access_same_device/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/10.xbar_access_same_device/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3653611209 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device.3653611209' seed=101291020127929641398356002221804993824060503044499995518341937095762004782793 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=101291020127929641398356002221804993824060503044499995518341937095762004782793 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/10.xbar_access_same_device/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"10.xbar_access_same_device_slow_rsp.16868982198926873544977158550855723591922983982744265106732544523982597887806","seed":16868982198926873544977158550855723591922983982744265106732544523982597887806,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/10.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/10.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2476578622 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device_slow_rsp.2476578622' seed=16868982198926873544977158550855723591922983982744265106732544523982597887806 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=16868982198926873544977158550855723591922983982744265106732544523982597887806 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/10.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_same_source","qual_name":"10.xbar_same_source.10036435312956708612329662768905710342740789099141457553780947281127210985391","seed":10036435312956708612329662768905710342740789099141457553780947281127210985391,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/10.xbar_same_source/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/10.xbar_same_source/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1864869807 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_same_source.1864869807' seed=10036435312956708612329662768905710342740789099141457553780947281127210985391 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=10036435312956708612329662768905710342740789099141457553780947281127210985391 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/10.xbar_same_source/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_same_source_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_random","qual_name":"10.xbar_error_random.95618408565675691384119653622648512420544576523245091322746037426175467008378","seed":95618408565675691384119653622648512420544576523245091322746037426175467008378,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/10.xbar_error_random/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/10.xbar_error_random/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1470837114 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_error_random.1470837114' seed=95618408565675691384119653622648512420544576523245091322746037426175467008378 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=95618408565675691384119653622648512420544576523245091322746037426175467008378 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/10.xbar_error_random/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_unmapped_addr","qual_name":"10.xbar_unmapped_addr.20690559201056983237618187985477443373444139066162881047917966748288864229562","seed":20690559201056983237618187985477443373444139066162881047917966748288864229562,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/10.xbar_unmapped_addr/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/10.xbar_unmapped_addr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=848042170 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_unmapped_addr.848042170' seed=20690559201056983237618187985477443373444139066162881047917966748288864229562 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=20690559201056983237618187985477443373444139066162881047917966748288864229562 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/10.xbar_unmapped_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_and_unmapped_addr","qual_name":"10.xbar_error_and_unmapped_addr.62075699399380433275169603982976110280685208662182508540975318002571920437193","seed":62075699399380433275169603982976110280685208662182508540975318002571920437193,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/10.xbar_error_and_unmapped_addr/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/10.xbar_error_and_unmapped_addr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2354474953 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_error_and_unmapped_addr.2354474953' seed=62075699399380433275169603982976110280685208662182508540975318002571920437193 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=62075699399380433275169603982976110280685208662182508540975318002571920437193 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/10.xbar_error_and_unmapped_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all","qual_name":"10.xbar_stress_all.66777264259250635652463120092162028278505781067847684919983525400308863944468","seed":66777264259250635652463120092162028278505781067847684919983525400308863944468,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/10.xbar_stress_all/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/10.xbar_stress_all/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2350073620 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all.2350073620' seed=66777264259250635652463120092162028278505781067847684919983525400308863944468 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=66777264259250635652463120092162028278505781067847684919983525400308863944468 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/10.xbar_stress_all/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_rand_reset","qual_name":"10.xbar_stress_all_with_rand_reset.32885755707256436299915719938343244622175975134431855387846657410047954907977","seed":32885755707256436299915719938343244622175975134431855387846657410047954907977,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/10.xbar_stress_all_with_rand_reset/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/10.xbar_stress_all_with_rand_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=595063625 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_rand_reset.595063625' seed=32885755707256436299915719938343244622175975134431855387846657410047954907977 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=32885755707256436299915719938343244622175975134431855387846657410047954907977 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/10.xbar_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"10.xbar_stress_all_with_error.80507263596181437024595377763931220369532957178561498987318994446222958772545","seed":80507263596181437024595377763931220369532957178561498987318994446222958772545,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/10.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/10.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2261238081 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_error.2261238081' seed=80507263596181437024595377763931220369532957178561498987318994446222958772545 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=80507263596181437024595377763931220369532957178561498987318994446222958772545 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/10.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"10.xbar_stress_all_with_reset_error.111183337113727551734964581256330481285652690745365100870440179594960544465189","seed":111183337113727551734964581256330481285652690745365100870440179594960544465189,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/10.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/10.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1985216805 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_reset_error.1985216805' seed=111183337113727551734964581256330481285652690745365100870440179594960544465189 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=111183337113727551734964581256330481285652690745365100870440179594960544465189 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/10.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke","qual_name":"11.xbar_smoke.109289988034110007140671460718240965631444032726754906261128540461189528697394","seed":109289988034110007140671460718240965631444032726754906261128540461189528697394,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/11.xbar_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/11.xbar_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3856546354 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke.3856546354' seed=109289988034110007140671460718240965631444032726754906261128540461189528697394 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=109289988034110007140671460718240965631444032726754906261128540461189528697394 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/11.xbar_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_zero_delays","qual_name":"11.xbar_smoke_zero_delays.5585221010199478572117696332418254452665177480435891784787954043900948381835","seed":5585221010199478572117696332418254452665177480435891784787954043900948381835,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/11.xbar_smoke_zero_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/11.xbar_smoke_zero_delays/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2106851467 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_zero_delays.2106851467' seed=5585221010199478572117696332418254452665177480435891784787954043900948381835 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=5585221010199478572117696332418254452665177480435891784787954043900948381835 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/11.xbar_smoke_zero_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_large_delays","qual_name":"11.xbar_smoke_large_delays.57873177715143480027294839026867071314443899851501499326166242884621012237422","seed":57873177715143480027294839026867071314443899851501499326166242884621012237422,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/11.xbar_smoke_large_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/11.xbar_smoke_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1248787566 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_large_delays.1248787566' seed=57873177715143480027294839026867071314443899851501499326166242884621012237422 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=57873177715143480027294839026867071314443899851501499326166242884621012237422 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/11.xbar_smoke_large_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_slow_rsp","qual_name":"11.xbar_smoke_slow_rsp.57156654325608134921831377591277507719674805828555889290678343429267869515962","seed":57156654325608134921831377591277507719674805828555889290678343429267869515962,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/11.xbar_smoke_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/11.xbar_smoke_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=300794042 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_slow_rsp.300794042' seed=57156654325608134921831377591277507719674805828555889290678343429267869515962 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=57156654325608134921831377591277507719674805828555889290678343429267869515962 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/11.xbar_smoke_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random","qual_name":"11.xbar_random.4470982477075848212376522263469783112634234566675104119962355690906796334964","seed":4470982477075848212376522263469783112634234566675104119962355690906796334964,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/11.xbar_random/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/11.xbar_random/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3885408116 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random.3885408116' seed=4470982477075848212376522263469783112634234566675104119962355690906796334964 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=4470982477075848212376522263469783112634234566675104119962355690906796334964 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/11.xbar_random/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_zero_delays","qual_name":"11.xbar_random_zero_delays.61857917652630892177943117250973369499849895503854231161721279287991728046429","seed":61857917652630892177943117250973369499849895503854231161721279287991728046429,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/11.xbar_random_zero_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/11.xbar_random_zero_delays/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1262453085 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_zero_delays.1262453085' seed=61857917652630892177943117250973369499849895503854231161721279287991728046429 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=61857917652630892177943117250973369499849895503854231161721279287991728046429 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/11.xbar_random_zero_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_large_delays","qual_name":"11.xbar_random_large_delays.56919097228999440368316558278574062222313356205694973099554249758939919563965","seed":56919097228999440368316558278574062222313356205694973099554249758939919563965,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/11.xbar_random_large_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/11.xbar_random_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=816463037 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_large_delays.816463037' seed=56919097228999440368316558278574062222313356205694973099554249758939919563965 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=56919097228999440368316558278574062222313356205694973099554249758939919563965 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/11.xbar_random_large_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_slow_rsp","qual_name":"11.xbar_random_slow_rsp.33526974159391968057277252765965509135643128614072115839319881379742034966133","seed":33526974159391968057277252765965509135643128614072115839319881379742034966133,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/11.xbar_random_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/11.xbar_random_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3946067573 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_slow_rsp.3946067573' seed=33526974159391968057277252765965509135643128614072115839319881379742034966133 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=33526974159391968057277252765965509135643128614072115839319881379742034966133 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/11.xbar_random_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device","qual_name":"11.xbar_access_same_device.34098611430748635026305182268542365167341044700001656837762854459329796221152","seed":34098611430748635026305182268542365167341044700001656837762854459329796221152,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/11.xbar_access_same_device/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/11.xbar_access_same_device/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1414375648 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device.1414375648' seed=34098611430748635026305182268542365167341044700001656837762854459329796221152 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=34098611430748635026305182268542365167341044700001656837762854459329796221152 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/11.xbar_access_same_device/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"11.xbar_access_same_device_slow_rsp.103488944239765943062701146429682363617708001495922985690862183010690040427201","seed":103488944239765943062701146429682363617708001495922985690862183010690040427201,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/11.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/11.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=955085505 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device_slow_rsp.955085505' seed=103488944239765943062701146429682363617708001495922985690862183010690040427201 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=103488944239765943062701146429682363617708001495922985690862183010690040427201 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/11.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_same_source","qual_name":"11.xbar_same_source.44127096801146333902770092771447263531517729032001043585152191647996565831627","seed":44127096801146333902770092771447263531517729032001043585152191647996565831627,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/11.xbar_same_source/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/11.xbar_same_source/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2000207819 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_same_source.2000207819' seed=44127096801146333902770092771447263531517729032001043585152191647996565831627 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=44127096801146333902770092771447263531517729032001043585152191647996565831627 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/11.xbar_same_source/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_same_source_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_random","qual_name":"11.xbar_error_random.95102619940353863266541405303138205730419520682045556030008727148435642465257","seed":95102619940353863266541405303138205730419520682045556030008727148435642465257,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/11.xbar_error_random/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/11.xbar_error_random/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2471705577 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_error_random.2471705577' seed=95102619940353863266541405303138205730419520682045556030008727148435642465257 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=95102619940353863266541405303138205730419520682045556030008727148435642465257 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/11.xbar_error_random/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_unmapped_addr","qual_name":"11.xbar_unmapped_addr.83093756716545221633077006070690032525899869769104516841601070733327689568651","seed":83093756716545221633077006070690032525899869769104516841601070733327689568651,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/11.xbar_unmapped_addr/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/11.xbar_unmapped_addr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2417742219 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_unmapped_addr.2417742219' seed=83093756716545221633077006070690032525899869769104516841601070733327689568651 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=83093756716545221633077006070690032525899869769104516841601070733327689568651 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/11.xbar_unmapped_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_and_unmapped_addr","qual_name":"11.xbar_error_and_unmapped_addr.27679214241606513384524848251218256863355823361893568674287880183632101535648","seed":27679214241606513384524848251218256863355823361893568674287880183632101535648,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/11.xbar_error_and_unmapped_addr/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/11.xbar_error_and_unmapped_addr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=585265056 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_error_and_unmapped_addr.585265056' seed=27679214241606513384524848251218256863355823361893568674287880183632101535648 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=27679214241606513384524848251218256863355823361893568674287880183632101535648 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/11.xbar_error_and_unmapped_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all","qual_name":"11.xbar_stress_all.103209420060484690809395929140763094451059391280513577262960687748482244731017","seed":103209420060484690809395929140763094451059391280513577262960687748482244731017,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/11.xbar_stress_all/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/11.xbar_stress_all/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=583196809 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all.583196809' seed=103209420060484690809395929140763094451059391280513577262960687748482244731017 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=103209420060484690809395929140763094451059391280513577262960687748482244731017 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/11.xbar_stress_all/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_rand_reset","qual_name":"11.xbar_stress_all_with_rand_reset.93631632996211191485063336056085433546533926798536817350903709865463344013174","seed":93631632996211191485063336056085433546533926798536817350903709865463344013174,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/11.xbar_stress_all_with_rand_reset/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/11.xbar_stress_all_with_rand_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2657886070 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_rand_reset.2657886070' seed=93631632996211191485063336056085433546533926798536817350903709865463344013174 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=93631632996211191485063336056085433546533926798536817350903709865463344013174 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/11.xbar_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"11.xbar_stress_all_with_error.19989545102170608786381185587093930641293234950472262300233850705949441006690","seed":19989545102170608786381185587093930641293234950472262300233850705949441006690,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/11.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/11.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=138550370 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_error.138550370' seed=19989545102170608786381185587093930641293234950472262300233850705949441006690 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=19989545102170608786381185587093930641293234950472262300233850705949441006690 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/11.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"11.xbar_stress_all_with_reset_error.99840041950748906816574166716629887964668376092855646527314156081615244672726","seed":99840041950748906816574166716629887964668376092855646527314156081615244672726,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/11.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/11.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2863185622 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_reset_error.2863185622' seed=99840041950748906816574166716629887964668376092855646527314156081615244672726 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=99840041950748906816574166716629887964668376092855646527314156081615244672726 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/11.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke","qual_name":"12.xbar_smoke.25317511696650955655193292739132872170983910194631146702968838376261040548498","seed":25317511696650955655193292739132872170983910194631146702968838376261040548498,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/12.xbar_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/12.xbar_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=307309202 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke.307309202' seed=25317511696650955655193292739132872170983910194631146702968838376261040548498 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=25317511696650955655193292739132872170983910194631146702968838376261040548498 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/12.xbar_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_zero_delays","qual_name":"12.xbar_smoke_zero_delays.8165582998050443505275742887767790185770679783655007843746145368549837571457","seed":8165582998050443505275742887767790185770679783655007843746145368549837571457,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/12.xbar_smoke_zero_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/12.xbar_smoke_zero_delays/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2816279937 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_zero_delays.2816279937' seed=8165582998050443505275742887767790185770679783655007843746145368549837571457 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=8165582998050443505275742887767790185770679783655007843746145368549837571457 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/12.xbar_smoke_zero_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_large_delays","qual_name":"12.xbar_smoke_large_delays.63481405300974933388917136015411429586197797533329520451798178311198339138381","seed":63481405300974933388917136015411429586197797533329520451798178311198339138381,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/12.xbar_smoke_large_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/12.xbar_smoke_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2182251341 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_large_delays.2182251341' seed=63481405300974933388917136015411429586197797533329520451798178311198339138381 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=63481405300974933388917136015411429586197797533329520451798178311198339138381 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/12.xbar_smoke_large_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_slow_rsp","qual_name":"12.xbar_smoke_slow_rsp.52107780784770930315636298390540444558273298084983701997580591301871107101443","seed":52107780784770930315636298390540444558273298084983701997580591301871107101443,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/12.xbar_smoke_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/12.xbar_smoke_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=923587331 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_slow_rsp.923587331' seed=52107780784770930315636298390540444558273298084983701997580591301871107101443 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=52107780784770930315636298390540444558273298084983701997580591301871107101443 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/12.xbar_smoke_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random","qual_name":"12.xbar_random.66657269988898078040948974670969426680918062709904386779520974155165636962096","seed":66657269988898078040948974670969426680918062709904386779520974155165636962096,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/12.xbar_random/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/12.xbar_random/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4058457904 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random.4058457904' seed=66657269988898078040948974670969426680918062709904386779520974155165636962096 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=66657269988898078040948974670969426680918062709904386779520974155165636962096 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/12.xbar_random/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_zero_delays","qual_name":"12.xbar_random_zero_delays.59570327996337168136926997144531963079176850599051096287266238030043542638453","seed":59570327996337168136926997144531963079176850599051096287266238030043542638453,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/12.xbar_random_zero_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/12.xbar_random_zero_delays/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=444780405 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_zero_delays.444780405' seed=59570327996337168136926997144531963079176850599051096287266238030043542638453 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=59570327996337168136926997144531963079176850599051096287266238030043542638453 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/12.xbar_random_zero_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_large_delays","qual_name":"12.xbar_random_large_delays.111622901750336684034702134941673156880194110977247959458583302651680276213847","seed":111622901750336684034702134941673156880194110977247959458583302651680276213847,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/12.xbar_random_large_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/12.xbar_random_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=998633559 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_large_delays.998633559' seed=111622901750336684034702134941673156880194110977247959458583302651680276213847 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=111622901750336684034702134941673156880194110977247959458583302651680276213847 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/12.xbar_random_large_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_slow_rsp","qual_name":"12.xbar_random_slow_rsp.60169600811663999155053478960102481140783254801705928144922995192544909401508","seed":60169600811663999155053478960102481140783254801705928144922995192544909401508,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/12.xbar_random_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/12.xbar_random_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2862161316 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_slow_rsp.2862161316' seed=60169600811663999155053478960102481140783254801705928144922995192544909401508 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=60169600811663999155053478960102481140783254801705928144922995192544909401508 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/12.xbar_random_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device","qual_name":"12.xbar_access_same_device.82303749290750647882360193595319620372737664886109634422677368547761804430312","seed":82303749290750647882360193595319620372737664886109634422677368547761804430312,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/12.xbar_access_same_device/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/12.xbar_access_same_device/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1112689640 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device.1112689640' seed=82303749290750647882360193595319620372737664886109634422677368547761804430312 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=82303749290750647882360193595319620372737664886109634422677368547761804430312 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/12.xbar_access_same_device/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"12.xbar_access_same_device_slow_rsp.23710081864969851983510379265169562154652191606416137717647716435182681348564","seed":23710081864969851983510379265169562154652191606416137717647716435182681348564,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/12.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/12.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4113324500 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device_slow_rsp.4113324500' seed=23710081864969851983510379265169562154652191606416137717647716435182681348564 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=23710081864969851983510379265169562154652191606416137717647716435182681348564 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/12.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_same_source","qual_name":"12.xbar_same_source.65005896345097309200910867414241331036021192574184739547644932293070360029436","seed":65005896345097309200910867414241331036021192574184739547644932293070360029436,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/12.xbar_same_source/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/12.xbar_same_source/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1875781884 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_same_source.1875781884' seed=65005896345097309200910867414241331036021192574184739547644932293070360029436 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=65005896345097309200910867414241331036021192574184739547644932293070360029436 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/12.xbar_same_source/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_same_source_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_random","qual_name":"12.xbar_error_random.3732097481496833068674042028991544525047237086386058042356952920121344025077","seed":3732097481496833068674042028991544525047237086386058042356952920121344025077,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/12.xbar_error_random/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/12.xbar_error_random/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1264083445 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_error_random.1264083445' seed=3732097481496833068674042028991544525047237086386058042356952920121344025077 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=3732097481496833068674042028991544525047237086386058042356952920121344025077 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/12.xbar_error_random/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_unmapped_addr","qual_name":"12.xbar_unmapped_addr.38034571245399549010240125917424449110784797367928882573564626785528317623482","seed":38034571245399549010240125917424449110784797367928882573564626785528317623482,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/12.xbar_unmapped_addr/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/12.xbar_unmapped_addr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2217360570 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_unmapped_addr.2217360570' seed=38034571245399549010240125917424449110784797367928882573564626785528317623482 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=38034571245399549010240125917424449110784797367928882573564626785528317623482 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/12.xbar_unmapped_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_and_unmapped_addr","qual_name":"12.xbar_error_and_unmapped_addr.20568180964235085909311523310238374778037053765936344441965095257158591586550","seed":20568180964235085909311523310238374778037053765936344441965095257158591586550,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/12.xbar_error_and_unmapped_addr/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/12.xbar_error_and_unmapped_addr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3787333878 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_error_and_unmapped_addr.3787333878' seed=20568180964235085909311523310238374778037053765936344441965095257158591586550 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=20568180964235085909311523310238374778037053765936344441965095257158591586550 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/12.xbar_error_and_unmapped_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all","qual_name":"12.xbar_stress_all.19808912617671964974870801415102540666286296421244283164015377536225700084696","seed":19808912617671964974870801415102540666286296421244283164015377536225700084696,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/12.xbar_stress_all/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/12.xbar_stress_all/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=923663320 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all.923663320' seed=19808912617671964974870801415102540666286296421244283164015377536225700084696 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=19808912617671964974870801415102540666286296421244283164015377536225700084696 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/12.xbar_stress_all/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_rand_reset","qual_name":"12.xbar_stress_all_with_rand_reset.27129857065731849968605312045373535897509794827624634270543772190619405947416","seed":27129857065731849968605312045373535897509794827624634270543772190619405947416,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/12.xbar_stress_all_with_rand_reset/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/12.xbar_stress_all_with_rand_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3295711768 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_rand_reset.3295711768' seed=27129857065731849968605312045373535897509794827624634270543772190619405947416 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=27129857065731849968605312045373535897509794827624634270543772190619405947416 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/12.xbar_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"12.xbar_stress_all_with_error.1393459792983860208475671756385808532912481227590433574939951449043060917441","seed":1393459792983860208475671756385808532912481227590433574939951449043060917441,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/12.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/12.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=18089153 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_error.18089153' seed=1393459792983860208475671756385808532912481227590433574939951449043060917441 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=1393459792983860208475671756385808532912481227590433574939951449043060917441 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/12.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"12.xbar_stress_all_with_reset_error.45028117855646861779118935958062520985209156079405059356106208406198032955564","seed":45028117855646861779118935958062520985209156079405059356106208406198032955564,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/12.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/12.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=61241516 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_reset_error.61241516' seed=45028117855646861779118935958062520985209156079405059356106208406198032955564 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=45028117855646861779118935958062520985209156079405059356106208406198032955564 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/12.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke","qual_name":"13.xbar_smoke.14861252440454508645835997634635069864281691339519328409921308461677679319380","seed":14861252440454508645835997634635069864281691339519328409921308461677679319380,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/13.xbar_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/13.xbar_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=961124692 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke.961124692' seed=14861252440454508645835997634635069864281691339519328409921308461677679319380 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=14861252440454508645835997634635069864281691339519328409921308461677679319380 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/13.xbar_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_zero_delays","qual_name":"13.xbar_smoke_zero_delays.75332901858875709713997149743249344233222646092022758471018019896597535129355","seed":75332901858875709713997149743249344233222646092022758471018019896597535129355,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/13.xbar_smoke_zero_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/13.xbar_smoke_zero_delays/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2679766795 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_zero_delays.2679766795' seed=75332901858875709713997149743249344233222646092022758471018019896597535129355 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=75332901858875709713997149743249344233222646092022758471018019896597535129355 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/13.xbar_smoke_zero_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_large_delays","qual_name":"13.xbar_smoke_large_delays.30876955695556231361153659946350780998204132831879994652371980879309334395458","seed":30876955695556231361153659946350780998204132831879994652371980879309334395458,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/13.xbar_smoke_large_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/13.xbar_smoke_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4292098626 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_large_delays.4292098626' seed=30876955695556231361153659946350780998204132831879994652371980879309334395458 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=30876955695556231361153659946350780998204132831879994652371980879309334395458 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/13.xbar_smoke_large_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_slow_rsp","qual_name":"13.xbar_smoke_slow_rsp.98764317797971722765244358947838581646966935169841485220578852378453569840065","seed":98764317797971722765244358947838581646966935169841485220578852378453569840065,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/13.xbar_smoke_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/13.xbar_smoke_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2843878337 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_slow_rsp.2843878337' seed=98764317797971722765244358947838581646966935169841485220578852378453569840065 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=98764317797971722765244358947838581646966935169841485220578852378453569840065 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/13.xbar_smoke_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random","qual_name":"13.xbar_random.12108016736932825512747286053499827488761599404450491426883295297886388734425","seed":12108016736932825512747286053499827488761599404450491426883295297886388734425,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/13.xbar_random/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/13.xbar_random/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1682688473 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random.1682688473' seed=12108016736932825512747286053499827488761599404450491426883295297886388734425 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=12108016736932825512747286053499827488761599404450491426883295297886388734425 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/13.xbar_random/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_zero_delays","qual_name":"13.xbar_random_zero_delays.88199986632353843796849684046867148478476155334909352418201915467735394967327","seed":88199986632353843796849684046867148478476155334909352418201915467735394967327,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/13.xbar_random_zero_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/13.xbar_random_zero_delays/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2857393951 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_zero_delays.2857393951' seed=88199986632353843796849684046867148478476155334909352418201915467735394967327 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=88199986632353843796849684046867148478476155334909352418201915467735394967327 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/13.xbar_random_zero_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_large_delays","qual_name":"13.xbar_random_large_delays.99552837399822259570363998474898901314243499680895144659881578259522507679334","seed":99552837399822259570363998474898901314243499680895144659881578259522507679334,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/13.xbar_random_large_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/13.xbar_random_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2685576806 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_large_delays.2685576806' seed=99552837399822259570363998474898901314243499680895144659881578259522507679334 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=99552837399822259570363998474898901314243499680895144659881578259522507679334 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/13.xbar_random_large_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_slow_rsp","qual_name":"13.xbar_random_slow_rsp.51603518998098668514656250755047115436705681568064579782306356060965747876739","seed":51603518998098668514656250755047115436705681568064579782306356060965747876739,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/13.xbar_random_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/13.xbar_random_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=454091651 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_slow_rsp.454091651' seed=51603518998098668514656250755047115436705681568064579782306356060965747876739 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=51603518998098668514656250755047115436705681568064579782306356060965747876739 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/13.xbar_random_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device","qual_name":"13.xbar_access_same_device.15634941486106846435923078405181066027602367565274714419924109829024407722808","seed":15634941486106846435923078405181066027602367565274714419924109829024407722808,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/13.xbar_access_same_device/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/13.xbar_access_same_device/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2561252152 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device.2561252152' seed=15634941486106846435923078405181066027602367565274714419924109829024407722808 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=15634941486106846435923078405181066027602367565274714419924109829024407722808 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/13.xbar_access_same_device/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"13.xbar_access_same_device_slow_rsp.937085584856842827988989609937554444100936216201372324946780419198905574639","seed":937085584856842827988989609937554444100936216201372324946780419198905574639,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/13.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/13.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3568395503 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device_slow_rsp.3568395503' seed=937085584856842827988989609937554444100936216201372324946780419198905574639 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=937085584856842827988989609937554444100936216201372324946780419198905574639 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/13.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_same_source","qual_name":"13.xbar_same_source.77472047456546285543049681356533914398069762067828713941770078315399281374718","seed":77472047456546285543049681356533914398069762067828713941770078315399281374718,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/13.xbar_same_source/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/13.xbar_same_source/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=679736830 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_same_source.679736830' seed=77472047456546285543049681356533914398069762067828713941770078315399281374718 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=77472047456546285543049681356533914398069762067828713941770078315399281374718 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/13.xbar_same_source/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_same_source_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_random","qual_name":"13.xbar_error_random.55231385280445346202492504139926275148681264343524682704900253070969494543091","seed":55231385280445346202492504139926275148681264343524682704900253070969494543091,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/13.xbar_error_random/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/13.xbar_error_random/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4114586355 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_error_random.4114586355' seed=55231385280445346202492504139926275148681264343524682704900253070969494543091 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=55231385280445346202492504139926275148681264343524682704900253070969494543091 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/13.xbar_error_random/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_unmapped_addr","qual_name":"13.xbar_unmapped_addr.109913758779943088028928076941216295196168417356948679820868352089179222827726","seed":109913758779943088028928076941216295196168417356948679820868352089179222827726,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/13.xbar_unmapped_addr/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/13.xbar_unmapped_addr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=124117710 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_unmapped_addr.124117710' seed=109913758779943088028928076941216295196168417356948679820868352089179222827726 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=109913758779943088028928076941216295196168417356948679820868352089179222827726 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/13.xbar_unmapped_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_and_unmapped_addr","qual_name":"13.xbar_error_and_unmapped_addr.2169801177911204455229041233691299650498664003531638343637581444126103044456","seed":2169801177911204455229041233691299650498664003531638343637581444126103044456,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/13.xbar_error_and_unmapped_addr/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/13.xbar_error_and_unmapped_addr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=592445800 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_error_and_unmapped_addr.592445800' seed=2169801177911204455229041233691299650498664003531638343637581444126103044456 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=2169801177911204455229041233691299650498664003531638343637581444126103044456 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/13.xbar_error_and_unmapped_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all","qual_name":"13.xbar_stress_all.37752990464888772511275505883452331655260425937407927953711853586761596182954","seed":37752990464888772511275505883452331655260425937407927953711853586761596182954,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/13.xbar_stress_all/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/13.xbar_stress_all/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3712393642 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all.3712393642' seed=37752990464888772511275505883452331655260425937407927953711853586761596182954 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=37752990464888772511275505883452331655260425937407927953711853586761596182954 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/13.xbar_stress_all/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_rand_reset","qual_name":"13.xbar_stress_all_with_rand_reset.36355186672783826045034506545610843128155494521109513647868130508237578675435","seed":36355186672783826045034506545610843128155494521109513647868130508237578675435,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/13.xbar_stress_all_with_rand_reset/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/13.xbar_stress_all_with_rand_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3549668587 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_rand_reset.3549668587' seed=36355186672783826045034506545610843128155494521109513647868130508237578675435 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=36355186672783826045034506545610843128155494521109513647868130508237578675435 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/13.xbar_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"13.xbar_stress_all_with_error.30420933483361806081724411969581358154539867997301274154734766327159462204478","seed":30420933483361806081724411969581358154539867997301274154734766327159462204478,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/13.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/13.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=7509054 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_error.7509054' seed=30420933483361806081724411969581358154539867997301274154734766327159462204478 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=30420933483361806081724411969581358154539867997301274154734766327159462204478 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/13.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"13.xbar_stress_all_with_reset_error.15507091973633507934954561374594997313382560805029839863223100557599141916627","seed":15507091973633507934954561374594997313382560805029839863223100557599141916627,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/13.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/13.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=80605139 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_reset_error.80605139' seed=15507091973633507934954561374594997313382560805029839863223100557599141916627 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=15507091973633507934954561374594997313382560805029839863223100557599141916627 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/13.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke","qual_name":"14.xbar_smoke.66598617829257228224838837997983077996962844958506703626742785473134716052915","seed":66598617829257228224838837997983077996962844958506703626742785473134716052915,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/14.xbar_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/14.xbar_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1165288883 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke.1165288883' seed=66598617829257228224838837997983077996962844958506703626742785473134716052915 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=66598617829257228224838837997983077996962844958506703626742785473134716052915 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/14.xbar_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_zero_delays","qual_name":"14.xbar_smoke_zero_delays.103707987620175894497973896033935342712904956230496423500398992346303040986156","seed":103707987620175894497973896033935342712904956230496423500398992346303040986156,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/14.xbar_smoke_zero_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/14.xbar_smoke_zero_delays/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2347113516 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_zero_delays.2347113516' seed=103707987620175894497973896033935342712904956230496423500398992346303040986156 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=103707987620175894497973896033935342712904956230496423500398992346303040986156 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/14.xbar_smoke_zero_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_large_delays","qual_name":"14.xbar_smoke_large_delays.17679742317373497854463855822127843982947509266239377234898651219198744770122","seed":17679742317373497854463855822127843982947509266239377234898651219198744770122,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/14.xbar_smoke_large_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/14.xbar_smoke_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=270579274 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_large_delays.270579274' seed=17679742317373497854463855822127843982947509266239377234898651219198744770122 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=17679742317373497854463855822127843982947509266239377234898651219198744770122 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/14.xbar_smoke_large_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_slow_rsp","qual_name":"14.xbar_smoke_slow_rsp.87725595073867709520798471115937235217740037882967845858149163206610401723501","seed":87725595073867709520798471115937235217740037882967845858149163206610401723501,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/14.xbar_smoke_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/14.xbar_smoke_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4235297901 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_slow_rsp.4235297901' seed=87725595073867709520798471115937235217740037882967845858149163206610401723501 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=87725595073867709520798471115937235217740037882967845858149163206610401723501 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/14.xbar_smoke_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random","qual_name":"14.xbar_random.41369942880823054348871208862542765588203213668125613929613997972916998487152","seed":41369942880823054348871208862542765588203213668125613929613997972916998487152,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/14.xbar_random/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/14.xbar_random/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=524008560 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random.524008560' seed=41369942880823054348871208862542765588203213668125613929613997972916998487152 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=41369942880823054348871208862542765588203213668125613929613997972916998487152 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/14.xbar_random/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_zero_delays","qual_name":"14.xbar_random_zero_delays.92326474882585875227340910649693441685832244999603270498100945235165633703617","seed":92326474882585875227340910649693441685832244999603270498100945235165633703617,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/14.xbar_random_zero_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/14.xbar_random_zero_delays/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2166222529 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_zero_delays.2166222529' seed=92326474882585875227340910649693441685832244999603270498100945235165633703617 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=92326474882585875227340910649693441685832244999603270498100945235165633703617 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/14.xbar_random_zero_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_large_delays","qual_name":"14.xbar_random_large_delays.102312295199917612563375574142817702247240678472202546712260315200783871528798","seed":102312295199917612563375574142817702247240678472202546712260315200783871528798,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/14.xbar_random_large_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/14.xbar_random_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=69619550 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_large_delays.69619550' seed=102312295199917612563375574142817702247240678472202546712260315200783871528798 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=102312295199917612563375574142817702247240678472202546712260315200783871528798 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/14.xbar_random_large_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_slow_rsp","qual_name":"14.xbar_random_slow_rsp.49102811952896152608039573492146841620832569784515851243708949951796031317189","seed":49102811952896152608039573492146841620832569784515851243708949951796031317189,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/14.xbar_random_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/14.xbar_random_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1235281093 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_slow_rsp.1235281093' seed=49102811952896152608039573492146841620832569784515851243708949951796031317189 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=49102811952896152608039573492146841620832569784515851243708949951796031317189 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/14.xbar_random_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device","qual_name":"14.xbar_access_same_device.31900925799150804177423396278213597137451410062728012268847129969379821024217","seed":31900925799150804177423396278213597137451410062728012268847129969379821024217,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/14.xbar_access_same_device/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/14.xbar_access_same_device/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=189068249 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device.189068249' seed=31900925799150804177423396278213597137451410062728012268847129969379821024217 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=31900925799150804177423396278213597137451410062728012268847129969379821024217 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/14.xbar_access_same_device/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"14.xbar_access_same_device_slow_rsp.62143832738228350476075853691566643698626662556744475772891849047784320344473","seed":62143832738228350476075853691566643698626662556744475772891849047784320344473,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/14.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/14.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=206250393 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device_slow_rsp.206250393' seed=62143832738228350476075853691566643698626662556744475772891849047784320344473 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=62143832738228350476075853691566643698626662556744475772891849047784320344473 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/14.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_same_source","qual_name":"14.xbar_same_source.6125309138247981645053222515111186084011183693278329632199388443787369838323","seed":6125309138247981645053222515111186084011183693278329632199388443787369838323,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/14.xbar_same_source/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/14.xbar_same_source/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3693016819 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_same_source.3693016819' seed=6125309138247981645053222515111186084011183693278329632199388443787369838323 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=6125309138247981645053222515111186084011183693278329632199388443787369838323 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/14.xbar_same_source/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_same_source_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_random","qual_name":"14.xbar_error_random.79596989209577299353057994620398085655872536926456396040524152748386819084076","seed":79596989209577299353057994620398085655872536926456396040524152748386819084076,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/14.xbar_error_random/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/14.xbar_error_random/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1846382380 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_error_random.1846382380' seed=79596989209577299353057994620398085655872536926456396040524152748386819084076 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=79596989209577299353057994620398085655872536926456396040524152748386819084076 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/14.xbar_error_random/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_unmapped_addr","qual_name":"14.xbar_unmapped_addr.96167909977439406943237017538685662040848368045231359898884887414947520027511","seed":96167909977439406943237017538685662040848368045231359898884887414947520027511,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/14.xbar_unmapped_addr/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/14.xbar_unmapped_addr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3168639863 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_unmapped_addr.3168639863' seed=96167909977439406943237017538685662040848368045231359898884887414947520027511 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=96167909977439406943237017538685662040848368045231359898884887414947520027511 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/14.xbar_unmapped_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_and_unmapped_addr","qual_name":"14.xbar_error_and_unmapped_addr.64421511682503310509348501530722171859657696947197866866953185935199888495852","seed":64421511682503310509348501530722171859657696947197866866953185935199888495852,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/14.xbar_error_and_unmapped_addr/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/14.xbar_error_and_unmapped_addr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1797018860 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_error_and_unmapped_addr.1797018860' seed=64421511682503310509348501530722171859657696947197866866953185935199888495852 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=64421511682503310509348501530722171859657696947197866866953185935199888495852 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/14.xbar_error_and_unmapped_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all","qual_name":"14.xbar_stress_all.81802581442940202644489122309345044788867500367092962327583606027938648020129","seed":81802581442940202644489122309345044788867500367092962327583606027938648020129,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/14.xbar_stress_all/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/14.xbar_stress_all/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3157251233 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all.3157251233' seed=81802581442940202644489122309345044788867500367092962327583606027938648020129 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=81802581442940202644489122309345044788867500367092962327583606027938648020129 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/14.xbar_stress_all/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_rand_reset","qual_name":"14.xbar_stress_all_with_rand_reset.7950332317846379482163935848889413575455807107327087265662477574156923374042","seed":7950332317846379482163935848889413575455807107327087265662477574156923374042,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/14.xbar_stress_all_with_rand_reset/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/14.xbar_stress_all_with_rand_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2022377946 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_rand_reset.2022377946' seed=7950332317846379482163935848889413575455807107327087265662477574156923374042 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=7950332317846379482163935848889413575455807107327087265662477574156923374042 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/14.xbar_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"14.xbar_stress_all_with_error.98259107170745575055696173965068054727312095081595244927234477350735396985227","seed":98259107170745575055696173965068054727312095081595244927234477350735396985227,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/14.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/14.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=191093131 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_error.191093131' seed=98259107170745575055696173965068054727312095081595244927234477350735396985227 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=98259107170745575055696173965068054727312095081595244927234477350735396985227 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/14.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"14.xbar_stress_all_with_reset_error.86218291533616474190054559690974435113219104682776714577531010752419067182601","seed":86218291533616474190054559690974435113219104682776714577531010752419067182601,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/14.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/14.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1812315657 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_reset_error.1812315657' seed=86218291533616474190054559690974435113219104682776714577531010752419067182601 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=86218291533616474190054559690974435113219104682776714577531010752419067182601 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/14.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke","qual_name":"15.xbar_smoke.105087653366126070466697967236613906279162149311210231598594241800986548354582","seed":105087653366126070466697967236613906279162149311210231598594241800986548354582,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/15.xbar_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/15.xbar_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=475381270 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke.475381270' seed=105087653366126070466697967236613906279162149311210231598594241800986548354582 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=105087653366126070466697967236613906279162149311210231598594241800986548354582 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/15.xbar_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_zero_delays","qual_name":"15.xbar_smoke_zero_delays.38684929295887283834121410311763989869157518510511876974859075919647324458680","seed":38684929295887283834121410311763989869157518510511876974859075919647324458680,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/15.xbar_smoke_zero_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/15.xbar_smoke_zero_delays/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2408271544 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_zero_delays.2408271544' seed=38684929295887283834121410311763989869157518510511876974859075919647324458680 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=38684929295887283834121410311763989869157518510511876974859075919647324458680 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/15.xbar_smoke_zero_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_large_delays","qual_name":"15.xbar_smoke_large_delays.76987766622424694574756099692704009024930751452604217231910145598496279340090","seed":76987766622424694574756099692704009024930751452604217231910145598496279340090,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/15.xbar_smoke_large_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/15.xbar_smoke_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1533518906 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_large_delays.1533518906' seed=76987766622424694574756099692704009024930751452604217231910145598496279340090 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=76987766622424694574756099692704009024930751452604217231910145598496279340090 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/15.xbar_smoke_large_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_slow_rsp","qual_name":"15.xbar_smoke_slow_rsp.22757632623625546715130335989597802852047294055294516400386850925294427005390","seed":22757632623625546715130335989597802852047294055294516400386850925294427005390,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/15.xbar_smoke_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/15.xbar_smoke_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4085211598 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_slow_rsp.4085211598' seed=22757632623625546715130335989597802852047294055294516400386850925294427005390 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=22757632623625546715130335989597802852047294055294516400386850925294427005390 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/15.xbar_smoke_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random","qual_name":"15.xbar_random.67948912510123458813588165145252372155183665972431861146629647551986287971037","seed":67948912510123458813588165145252372155183665972431861146629647551986287971037,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/15.xbar_random/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/15.xbar_random/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=423561949 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random.423561949' seed=67948912510123458813588165145252372155183665972431861146629647551986287971037 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=67948912510123458813588165145252372155183665972431861146629647551986287971037 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/15.xbar_random/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_zero_delays","qual_name":"15.xbar_random_zero_delays.76420074041441564497584189106081741475080565197717081773652332545714785217951","seed":76420074041441564497584189106081741475080565197717081773652332545714785217951,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/15.xbar_random_zero_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/15.xbar_random_zero_delays/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1445588383 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_zero_delays.1445588383' seed=76420074041441564497584189106081741475080565197717081773652332545714785217951 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=76420074041441564497584189106081741475080565197717081773652332545714785217951 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/15.xbar_random_zero_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_large_delays","qual_name":"15.xbar_random_large_delays.3042823441996278364641742472234500424797045744475662228584713336157844293994","seed":3042823441996278364641742472234500424797045744475662228584713336157844293994,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/15.xbar_random_large_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/15.xbar_random_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3059763562 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_large_delays.3059763562' seed=3042823441996278364641742472234500424797045744475662228584713336157844293994 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=3042823441996278364641742472234500424797045744475662228584713336157844293994 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/15.xbar_random_large_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_slow_rsp","qual_name":"15.xbar_random_slow_rsp.12030567333802247104503657439603301879007615137744565594000610212274307110711","seed":12030567333802247104503657439603301879007615137744565594000610212274307110711,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/15.xbar_random_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/15.xbar_random_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4226324279 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_slow_rsp.4226324279' seed=12030567333802247104503657439603301879007615137744565594000610212274307110711 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=12030567333802247104503657439603301879007615137744565594000610212274307110711 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/15.xbar_random_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device","qual_name":"15.xbar_access_same_device.76789093294853122340597528480683377942552921196795784112702207572394055648355","seed":76789093294853122340597528480683377942552921196795784112702207572394055648355,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/15.xbar_access_same_device/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/15.xbar_access_same_device/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=253052003 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device.253052003' seed=76789093294853122340597528480683377942552921196795784112702207572394055648355 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=76789093294853122340597528480683377942552921196795784112702207572394055648355 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/15.xbar_access_same_device/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"15.xbar_access_same_device_slow_rsp.114274969237234931290738041070793498190421983440513476898726655713165913121788","seed":114274969237234931290738041070793498190421983440513476898726655713165913121788,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/15.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/15.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1604609020 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device_slow_rsp.1604609020' seed=114274969237234931290738041070793498190421983440513476898726655713165913121788 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=114274969237234931290738041070793498190421983440513476898726655713165913121788 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/15.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_same_source","qual_name":"15.xbar_same_source.103541910288005442950744362382839107235927203249340080858985158481906420766472","seed":103541910288005442950744362382839107235927203249340080858985158481906420766472,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/15.xbar_same_source/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/15.xbar_same_source/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=730683144 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_same_source.730683144' seed=103541910288005442950744362382839107235927203249340080858985158481906420766472 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=103541910288005442950744362382839107235927203249340080858985158481906420766472 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/15.xbar_same_source/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_same_source_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_random","qual_name":"15.xbar_error_random.96432329589328102640001577829549531783053948124559967903311500795049015131983","seed":96432329589328102640001577829549531783053948124559967903311500795049015131983,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/15.xbar_error_random/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/15.xbar_error_random/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4188946255 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_error_random.4188946255' seed=96432329589328102640001577829549531783053948124559967903311500795049015131983 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=96432329589328102640001577829549531783053948124559967903311500795049015131983 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/15.xbar_error_random/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_unmapped_addr","qual_name":"15.xbar_unmapped_addr.71506128184051650261551963315545100506737122468518263911495993056393234181613","seed":71506128184051650261551963315545100506737122468518263911495993056393234181613,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/15.xbar_unmapped_addr/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/15.xbar_unmapped_addr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4116934125 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_unmapped_addr.4116934125' seed=71506128184051650261551963315545100506737122468518263911495993056393234181613 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=71506128184051650261551963315545100506737122468518263911495993056393234181613 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/15.xbar_unmapped_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_and_unmapped_addr","qual_name":"15.xbar_error_and_unmapped_addr.100003049250654925749754509179338308801330690731514102300913394770322971405819","seed":100003049250654925749754509179338308801330690731514102300913394770322971405819,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/15.xbar_error_and_unmapped_addr/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/15.xbar_error_and_unmapped_addr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4189564411 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_error_and_unmapped_addr.4189564411' seed=100003049250654925749754509179338308801330690731514102300913394770322971405819 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=100003049250654925749754509179338308801330690731514102300913394770322971405819 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/15.xbar_error_and_unmapped_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all","qual_name":"15.xbar_stress_all.43772430348734949330156261108109599178576416029298956400599994527642524453262","seed":43772430348734949330156261108109599178576416029298956400599994527642524453262,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/15.xbar_stress_all/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/15.xbar_stress_all/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=888539534 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all.888539534' seed=43772430348734949330156261108109599178576416029298956400599994527642524453262 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=43772430348734949330156261108109599178576416029298956400599994527642524453262 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/15.xbar_stress_all/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_rand_reset","qual_name":"15.xbar_stress_all_with_rand_reset.53964058732886485710997447890721406666886601239196383163457847613334158316246","seed":53964058732886485710997447890721406666886601239196383163457847613334158316246,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/15.xbar_stress_all_with_rand_reset/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/15.xbar_stress_all_with_rand_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4190638806 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_rand_reset.4190638806' seed=53964058732886485710997447890721406666886601239196383163457847613334158316246 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=53964058732886485710997447890721406666886601239196383163457847613334158316246 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/15.xbar_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"15.xbar_stress_all_with_error.85829757691388949652696592464084280283322423972025298016652621897914329045836","seed":85829757691388949652696592464084280283322423972025298016652621897914329045836,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/15.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/15.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4241726284 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_error.4241726284' seed=85829757691388949652696592464084280283322423972025298016652621897914329045836 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=85829757691388949652696592464084280283322423972025298016652621897914329045836 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/15.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"15.xbar_stress_all_with_reset_error.29657933220332953142537307504100485436800090149686115458009353391170129769491","seed":29657933220332953142537307504100485436800090149686115458009353391170129769491,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/15.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/15.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=169620499 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_reset_error.169620499' seed=29657933220332953142537307504100485436800090149686115458009353391170129769491 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=29657933220332953142537307504100485436800090149686115458009353391170129769491 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/15.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke","qual_name":"16.xbar_smoke.89341998155893111680393697038515156455092971626697655594024437750645823149471","seed":89341998155893111680393697038515156455092971626697655594024437750645823149471,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/16.xbar_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/16.xbar_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4162622879 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke.4162622879' seed=89341998155893111680393697038515156455092971626697655594024437750645823149471 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=89341998155893111680393697038515156455092971626697655594024437750645823149471 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/16.xbar_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_zero_delays","qual_name":"16.xbar_smoke_zero_delays.28200313873566052034944559282186715631454389007303233981432085276224235499096","seed":28200313873566052034944559282186715631454389007303233981432085276224235499096,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/16.xbar_smoke_zero_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/16.xbar_smoke_zero_delays/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2721574488 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_zero_delays.2721574488' seed=28200313873566052034944559282186715631454389007303233981432085276224235499096 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=28200313873566052034944559282186715631454389007303233981432085276224235499096 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/16.xbar_smoke_zero_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_large_delays","qual_name":"16.xbar_smoke_large_delays.107472316660212260730910413895515746530213224939555027143416098847973198896191","seed":107472316660212260730910413895515746530213224939555027143416098847973198896191,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/16.xbar_smoke_large_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/16.xbar_smoke_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1244240959 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_large_delays.1244240959' seed=107472316660212260730910413895515746530213224939555027143416098847973198896191 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=107472316660212260730910413895515746530213224939555027143416098847973198896191 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/16.xbar_smoke_large_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_slow_rsp","qual_name":"16.xbar_smoke_slow_rsp.95532592916896307987847810277108943129769270037525106657684367173177171821233","seed":95532592916896307987847810277108943129769270037525106657684367173177171821233,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/16.xbar_smoke_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/16.xbar_smoke_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1982907057 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_slow_rsp.1982907057' seed=95532592916896307987847810277108943129769270037525106657684367173177171821233 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=95532592916896307987847810277108943129769270037525106657684367173177171821233 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/16.xbar_smoke_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random","qual_name":"16.xbar_random.2251067608388079113894661577709359471888707733584720607911406342854184399992","seed":2251067608388079113894661577709359471888707733584720607911406342854184399992,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/16.xbar_random/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/16.xbar_random/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=585757816 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random.585757816' seed=2251067608388079113894661577709359471888707733584720607911406342854184399992 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=2251067608388079113894661577709359471888707733584720607911406342854184399992 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/16.xbar_random/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_zero_delays","qual_name":"16.xbar_random_zero_delays.87531117825548984888040766832948393624588224066136685330849647064640270741309","seed":87531117825548984888040766832948393624588224066136685330849647064640270741309,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/16.xbar_random_zero_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/16.xbar_random_zero_delays/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1475456829 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_zero_delays.1475456829' seed=87531117825548984888040766832948393624588224066136685330849647064640270741309 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=87531117825548984888040766832948393624588224066136685330849647064640270741309 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/16.xbar_random_zero_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_large_delays","qual_name":"16.xbar_random_large_delays.15908342719389266809543986232648137902870771359362022491098048636318642758401","seed":15908342719389266809543986232648137902870771359362022491098048636318642758401,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/16.xbar_random_large_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/16.xbar_random_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=386556673 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_large_delays.386556673' seed=15908342719389266809543986232648137902870771359362022491098048636318642758401 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=15908342719389266809543986232648137902870771359362022491098048636318642758401 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/16.xbar_random_large_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_slow_rsp","qual_name":"16.xbar_random_slow_rsp.115135517125803023885353368423816257800935603513018424488930466236277899169086","seed":115135517125803023885353368423816257800935603513018424488930466236277899169086,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/16.xbar_random_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/16.xbar_random_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1608289598 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_slow_rsp.1608289598' seed=115135517125803023885353368423816257800935603513018424488930466236277899169086 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=115135517125803023885353368423816257800935603513018424488930466236277899169086 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/16.xbar_random_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device","qual_name":"16.xbar_access_same_device.21166733808061858685130307526003090587297326617650360372858359285497991533542","seed":21166733808061858685130307526003090587297326617650360372858359285497991533542,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/16.xbar_access_same_device/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/16.xbar_access_same_device/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4267971558 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device.4267971558' seed=21166733808061858685130307526003090587297326617650360372858359285497991533542 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=21166733808061858685130307526003090587297326617650360372858359285497991533542 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/16.xbar_access_same_device/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"16.xbar_access_same_device_slow_rsp.22156855923943295335271054946015433663307272090548279880523221954843530616960","seed":22156855923943295335271054946015433663307272090548279880523221954843530616960,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/16.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/16.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3944603776 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device_slow_rsp.3944603776' seed=22156855923943295335271054946015433663307272090548279880523221954843530616960 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=22156855923943295335271054946015433663307272090548279880523221954843530616960 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/16.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_same_source","qual_name":"16.xbar_same_source.34623541185365253996822264248598558978199005835147801856828949960656886536427","seed":34623541185365253996822264248598558978199005835147801856828949960656886536427,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/16.xbar_same_source/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/16.xbar_same_source/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3082918123 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_same_source.3082918123' seed=34623541185365253996822264248598558978199005835147801856828949960656886536427 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=34623541185365253996822264248598558978199005835147801856828949960656886536427 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/16.xbar_same_source/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_same_source_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_random","qual_name":"16.xbar_error_random.26114837703217172622767767727490310156787503758352921706473538523899780128110","seed":26114837703217172622767767727490310156787503758352921706473538523899780128110,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/16.xbar_error_random/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/16.xbar_error_random/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=729275758 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_error_random.729275758' seed=26114837703217172622767767727490310156787503758352921706473538523899780128110 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=26114837703217172622767767727490310156787503758352921706473538523899780128110 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/16.xbar_error_random/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_unmapped_addr","qual_name":"16.xbar_unmapped_addr.113818208619777461873823705624824989624711483225836279646883974724555653429219","seed":113818208619777461873823705624824989624711483225836279646883974724555653429219,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/16.xbar_unmapped_addr/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/16.xbar_unmapped_addr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=708753379 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_unmapped_addr.708753379' seed=113818208619777461873823705624824989624711483225836279646883974724555653429219 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=113818208619777461873823705624824989624711483225836279646883974724555653429219 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/16.xbar_unmapped_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_and_unmapped_addr","qual_name":"16.xbar_error_and_unmapped_addr.25958167163448643414929736940109927994099243033991278174778023696930284661706","seed":25958167163448643414929736940109927994099243033991278174778023696930284661706,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/16.xbar_error_and_unmapped_addr/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/16.xbar_error_and_unmapped_addr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3163188170 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_error_and_unmapped_addr.3163188170' seed=25958167163448643414929736940109927994099243033991278174778023696930284661706 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=25958167163448643414929736940109927994099243033991278174778023696930284661706 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/16.xbar_error_and_unmapped_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all","qual_name":"16.xbar_stress_all.41207174731772055035436351510657194379807035292625255102941719517747699298847","seed":41207174731772055035436351510657194379807035292625255102941719517747699298847,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/16.xbar_stress_all/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/16.xbar_stress_all/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=378057247 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all.378057247' seed=41207174731772055035436351510657194379807035292625255102941719517747699298847 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=41207174731772055035436351510657194379807035292625255102941719517747699298847 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/16.xbar_stress_all/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_rand_reset","qual_name":"16.xbar_stress_all_with_rand_reset.41893918885256927637809164328428490666386342851917124128146418240007277204508","seed":41893918885256927637809164328428490666386342851917124128146418240007277204508,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/16.xbar_stress_all_with_rand_reset/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/16.xbar_stress_all_with_rand_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2745521180 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_rand_reset.2745521180' seed=41893918885256927637809164328428490666386342851917124128146418240007277204508 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=41893918885256927637809164328428490666386342851917124128146418240007277204508 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/16.xbar_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"16.xbar_stress_all_with_error.14118356428227425396682634510816307213697103037482050686276928659587548681761","seed":14118356428227425396682634510816307213697103037482050686276928659587548681761,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/16.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/16.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=195663393 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_error.195663393' seed=14118356428227425396682634510816307213697103037482050686276928659587548681761 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=14118356428227425396682634510816307213697103037482050686276928659587548681761 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/16.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"16.xbar_stress_all_with_reset_error.11103691547830548116255077645976830342491463659200491056740040355040211608039","seed":11103691547830548116255077645976830342491463659200491056740040355040211608039,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/16.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/16.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1472569831 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_reset_error.1472569831' seed=11103691547830548116255077645976830342491463659200491056740040355040211608039 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=11103691547830548116255077645976830342491463659200491056740040355040211608039 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/16.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke","qual_name":"17.xbar_smoke.114411128978655545755954835359150033893280021138813963934850605253778974971813","seed":114411128978655545755954835359150033893280021138813963934850605253778974971813,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/17.xbar_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/17.xbar_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3750500261 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke.3750500261' seed=114411128978655545755954835359150033893280021138813963934850605253778974971813 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=114411128978655545755954835359150033893280021138813963934850605253778974971813 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/17.xbar_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_zero_delays","qual_name":"17.xbar_smoke_zero_delays.90426827557777183599572799719172249797785801680810311199041290656359423546880","seed":90426827557777183599572799719172249797785801680810311199041290656359423546880,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/17.xbar_smoke_zero_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/17.xbar_smoke_zero_delays/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3280606720 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_zero_delays.3280606720' seed=90426827557777183599572799719172249797785801680810311199041290656359423546880 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=90426827557777183599572799719172249797785801680810311199041290656359423546880 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/17.xbar_smoke_zero_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_large_delays","qual_name":"17.xbar_smoke_large_delays.82098855085877437956536099634210880424169114977236901009250113811561348988286","seed":82098855085877437956536099634210880424169114977236901009250113811561348988286,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/17.xbar_smoke_large_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/17.xbar_smoke_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=634518910 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_large_delays.634518910' seed=82098855085877437956536099634210880424169114977236901009250113811561348988286 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=82098855085877437956536099634210880424169114977236901009250113811561348988286 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/17.xbar_smoke_large_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_slow_rsp","qual_name":"17.xbar_smoke_slow_rsp.69107077355827512887908993990676348366516747276438942047753084439643506419609","seed":69107077355827512887908993990676348366516747276438942047753084439643506419609,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/17.xbar_smoke_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/17.xbar_smoke_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=648882073 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_slow_rsp.648882073' seed=69107077355827512887908993990676348366516747276438942047753084439643506419609 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=69107077355827512887908993990676348366516747276438942047753084439643506419609 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/17.xbar_smoke_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random","qual_name":"17.xbar_random.83619596931068044422810973032147554477323073085926878866974715533812845923234","seed":83619596931068044422810973032147554477323073085926878866974715533812845923234,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/17.xbar_random/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/17.xbar_random/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3375254434 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random.3375254434' seed=83619596931068044422810973032147554477323073085926878866974715533812845923234 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=83619596931068044422810973032147554477323073085926878866974715533812845923234 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/17.xbar_random/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_zero_delays","qual_name":"17.xbar_random_zero_delays.37194264728566264094139121870986973201750923060168509517395702149475255332808","seed":37194264728566264094139121870986973201750923060168509517395702149475255332808,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/17.xbar_random_zero_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/17.xbar_random_zero_delays/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2168336328 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_zero_delays.2168336328' seed=37194264728566264094139121870986973201750923060168509517395702149475255332808 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=37194264728566264094139121870986973201750923060168509517395702149475255332808 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/17.xbar_random_zero_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_large_delays","qual_name":"17.xbar_random_large_delays.45098039391347027527709304387404910545070163732730754209126017464148042644396","seed":45098039391347027527709304387404910545070163732730754209126017464148042644396,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/17.xbar_random_large_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/17.xbar_random_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3124427692 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_large_delays.3124427692' seed=45098039391347027527709304387404910545070163732730754209126017464148042644396 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=45098039391347027527709304387404910545070163732730754209126017464148042644396 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/17.xbar_random_large_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_slow_rsp","qual_name":"17.xbar_random_slow_rsp.85854574956323361772373619593984124189897954781622435880582653642799302435782","seed":85854574956323361772373619593984124189897954781622435880582653642799302435782,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/17.xbar_random_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/17.xbar_random_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=79815622 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_slow_rsp.79815622' seed=85854574956323361772373619593984124189897954781622435880582653642799302435782 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=85854574956323361772373619593984124189897954781622435880582653642799302435782 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/17.xbar_random_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device","qual_name":"17.xbar_access_same_device.41723908901225700253725365833572534695325594047910588076940257764639141975060","seed":41723908901225700253725365833572534695325594047910588076940257764639141975060,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/17.xbar_access_same_device/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/17.xbar_access_same_device/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3462845460 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device.3462845460' seed=41723908901225700253725365833572534695325594047910588076940257764639141975060 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=41723908901225700253725365833572534695325594047910588076940257764639141975060 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/17.xbar_access_same_device/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"17.xbar_access_same_device_slow_rsp.93742842087594224390404576439572540238204104995827770823528467402723438575298","seed":93742842087594224390404576439572540238204104995827770823528467402723438575298,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/17.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/17.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1580940994 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device_slow_rsp.1580940994' seed=93742842087594224390404576439572540238204104995827770823528467402723438575298 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=93742842087594224390404576439572540238204104995827770823528467402723438575298 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/17.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_same_source","qual_name":"17.xbar_same_source.69046034330118081941688204697019439710281707684453345733572793707359568420996","seed":69046034330118081941688204697019439710281707684453345733572793707359568420996,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/17.xbar_same_source/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/17.xbar_same_source/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1530945668 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_same_source.1530945668' seed=69046034330118081941688204697019439710281707684453345733572793707359568420996 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=69046034330118081941688204697019439710281707684453345733572793707359568420996 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/17.xbar_same_source/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_same_source_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_random","qual_name":"17.xbar_error_random.48035054489864746297720750715480248840432089768903404102819741301975656458100","seed":48035054489864746297720750715480248840432089768903404102819741301975656458100,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/17.xbar_error_random/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/17.xbar_error_random/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3338168180 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_error_random.3338168180' seed=48035054489864746297720750715480248840432089768903404102819741301975656458100 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=48035054489864746297720750715480248840432089768903404102819741301975656458100 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/17.xbar_error_random/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_unmapped_addr","qual_name":"17.xbar_unmapped_addr.89675246710447479992949462370309590652935931482202342649182683154754304039029","seed":89675246710447479992949462370309590652935931482202342649182683154754304039029,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/17.xbar_unmapped_addr/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/17.xbar_unmapped_addr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=866211957 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_unmapped_addr.866211957' seed=89675246710447479992949462370309590652935931482202342649182683154754304039029 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=89675246710447479992949462370309590652935931482202342649182683154754304039029 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/17.xbar_unmapped_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_and_unmapped_addr","qual_name":"17.xbar_error_and_unmapped_addr.107417131965938793892717579142664805275780891064286462007483793053583748074735","seed":107417131965938793892717579142664805275780891064286462007483793053583748074735,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/17.xbar_error_and_unmapped_addr/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/17.xbar_error_and_unmapped_addr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=20155631 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_error_and_unmapped_addr.20155631' seed=107417131965938793892717579142664805275780891064286462007483793053583748074735 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=107417131965938793892717579142664805275780891064286462007483793053583748074735 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/17.xbar_error_and_unmapped_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all","qual_name":"17.xbar_stress_all.49350023721115909316352203524032207498997402988027027053412036113164093937926","seed":49350023721115909316352203524032207498997402988027027053412036113164093937926,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/17.xbar_stress_all/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/17.xbar_stress_all/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=748214534 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all.748214534' seed=49350023721115909316352203524032207498997402988027027053412036113164093937926 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=49350023721115909316352203524032207498997402988027027053412036113164093937926 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/17.xbar_stress_all/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_rand_reset","qual_name":"17.xbar_stress_all_with_rand_reset.47977411866157174582958554100395135076542926338629654111952241174152603436347","seed":47977411866157174582958554100395135076542926338629654111952241174152603436347,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/17.xbar_stress_all_with_rand_reset/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/17.xbar_stress_all_with_rand_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=137299259 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_rand_reset.137299259' seed=47977411866157174582958554100395135076542926338629654111952241174152603436347 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=47977411866157174582958554100395135076542926338629654111952241174152603436347 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/17.xbar_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"17.xbar_stress_all_with_error.107734297129652323723337564773584166113352754165553462241813055175501968623558","seed":107734297129652323723337564773584166113352754165553462241813055175501968623558,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/17.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/17.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3327707078 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_error.3327707078' seed=107734297129652323723337564773584166113352754165553462241813055175501968623558 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=107734297129652323723337564773584166113352754165553462241813055175501968623558 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/17.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"17.xbar_stress_all_with_reset_error.87026421972261591727569348224277177116058994244997620198626549571288678855727","seed":87026421972261591727569348224277177116058994244997620198626549571288678855727,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/17.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/17.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3602707503 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_reset_error.3602707503' seed=87026421972261591727569348224277177116058994244997620198626549571288678855727 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=87026421972261591727569348224277177116058994244997620198626549571288678855727 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/17.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke","qual_name":"18.xbar_smoke.115091936110114923101789900063006522890321169237345276711620958843782810816122","seed":115091936110114923101789900063006522890321169237345276711620958843782810816122,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/18.xbar_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/18.xbar_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1310183034 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke.1310183034' seed=115091936110114923101789900063006522890321169237345276711620958843782810816122 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=115091936110114923101789900063006522890321169237345276711620958843782810816122 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/18.xbar_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_zero_delays","qual_name":"18.xbar_smoke_zero_delays.73058719960160217425211019260939738263371142411212510674570464429184604311786","seed":73058719960160217425211019260939738263371142411212510674570464429184604311786,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/18.xbar_smoke_zero_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/18.xbar_smoke_zero_delays/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1871843562 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_zero_delays.1871843562' seed=73058719960160217425211019260939738263371142411212510674570464429184604311786 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=73058719960160217425211019260939738263371142411212510674570464429184604311786 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/18.xbar_smoke_zero_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_large_delays","qual_name":"18.xbar_smoke_large_delays.13513049595344064620979176466837073934581808929055398748537503229292668538368","seed":13513049595344064620979176466837073934581808929055398748537503229292668538368,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/18.xbar_smoke_large_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/18.xbar_smoke_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=542658048 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_large_delays.542658048' seed=13513049595344064620979176466837073934581808929055398748537503229292668538368 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=13513049595344064620979176466837073934581808929055398748537503229292668538368 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/18.xbar_smoke_large_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_slow_rsp","qual_name":"18.xbar_smoke_slow_rsp.64164791517923695910734927704854646886325921706524748750538513218953285092311","seed":64164791517923695910734927704854646886325921706524748750538513218953285092311,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/18.xbar_smoke_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/18.xbar_smoke_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=125191127 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_slow_rsp.125191127' seed=64164791517923695910734927704854646886325921706524748750538513218953285092311 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=64164791517923695910734927704854646886325921706524748750538513218953285092311 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/18.xbar_smoke_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random","qual_name":"18.xbar_random.21313067038755831042497740536477951970220337572064803293939731677202904321180","seed":21313067038755831042497740536477951970220337572064803293939731677202904321180,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/18.xbar_random/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/18.xbar_random/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3846769820 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random.3846769820' seed=21313067038755831042497740536477951970220337572064803293939731677202904321180 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=21313067038755831042497740536477951970220337572064803293939731677202904321180 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/18.xbar_random/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_zero_delays","qual_name":"18.xbar_random_zero_delays.20472893100285450580772265874717768720698515852217358399075440394847625353120","seed":20472893100285450580772265874717768720698515852217358399075440394847625353120,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/18.xbar_random_zero_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/18.xbar_random_zero_delays/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2840270752 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_zero_delays.2840270752' seed=20472893100285450580772265874717768720698515852217358399075440394847625353120 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=20472893100285450580772265874717768720698515852217358399075440394847625353120 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/18.xbar_random_zero_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_large_delays","qual_name":"18.xbar_random_large_delays.90115247887906217070815543536199752481338822368361989359698136122317439053880","seed":90115247887906217070815543536199752481338822368361989359698136122317439053880,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/18.xbar_random_large_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/18.xbar_random_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2264739896 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_large_delays.2264739896' seed=90115247887906217070815543536199752481338822368361989359698136122317439053880 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=90115247887906217070815543536199752481338822368361989359698136122317439053880 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/18.xbar_random_large_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_slow_rsp","qual_name":"18.xbar_random_slow_rsp.40105381730122547843685807608952808541770742440928710310166984881661292862593","seed":40105381730122547843685807608952808541770742440928710310166984881661292862593,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/18.xbar_random_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/18.xbar_random_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3317718145 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_slow_rsp.3317718145' seed=40105381730122547843685807608952808541770742440928710310166984881661292862593 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=40105381730122547843685807608952808541770742440928710310166984881661292862593 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/18.xbar_random_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device","qual_name":"18.xbar_access_same_device.104005389251655773493339388880461445865980049529926480878523866336627322779015","seed":104005389251655773493339388880461445865980049529926480878523866336627322779015,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/18.xbar_access_same_device/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/18.xbar_access_same_device/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1636300167 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device.1636300167' seed=104005389251655773493339388880461445865980049529926480878523866336627322779015 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=104005389251655773493339388880461445865980049529926480878523866336627322779015 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/18.xbar_access_same_device/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"18.xbar_access_same_device_slow_rsp.105782830671873941287391411533676719308230204943583768922113896897780494457796","seed":105782830671873941287391411533676719308230204943583768922113896897780494457796,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/18.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/18.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1301896132 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device_slow_rsp.1301896132' seed=105782830671873941287391411533676719308230204943583768922113896897780494457796 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=105782830671873941287391411533676719308230204943583768922113896897780494457796 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/18.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_same_source","qual_name":"18.xbar_same_source.24971140647129114756925487839439014135633579160566649464070109997027000703822","seed":24971140647129114756925487839439014135633579160566649464070109997027000703822,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/18.xbar_same_source/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/18.xbar_same_source/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4178697038 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_same_source.4178697038' seed=24971140647129114756925487839439014135633579160566649464070109997027000703822 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=24971140647129114756925487839439014135633579160566649464070109997027000703822 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/18.xbar_same_source/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_same_source_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_random","qual_name":"18.xbar_error_random.93390927145005399738425527785882281830418241116382341795888805888805927032045","seed":93390927145005399738425527785882281830418241116382341795888805888805927032045,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/18.xbar_error_random/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/18.xbar_error_random/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=142513389 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_error_random.142513389' seed=93390927145005399738425527785882281830418241116382341795888805888805927032045 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=93390927145005399738425527785882281830418241116382341795888805888805927032045 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/18.xbar_error_random/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_unmapped_addr","qual_name":"18.xbar_unmapped_addr.70121678973114794669851804180579178168292893471411822474107928665747475223984","seed":70121678973114794669851804180579178168292893471411822474107928665747475223984,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/18.xbar_unmapped_addr/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/18.xbar_unmapped_addr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=308368816 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_unmapped_addr.308368816' seed=70121678973114794669851804180579178168292893471411822474107928665747475223984 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=70121678973114794669851804180579178168292893471411822474107928665747475223984 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/18.xbar_unmapped_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_and_unmapped_addr","qual_name":"18.xbar_error_and_unmapped_addr.94550637384399400676691306982174631601533954567120489219938810795215541272592","seed":94550637384399400676691306982174631601533954567120489219938810795215541272592,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/18.xbar_error_and_unmapped_addr/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/18.xbar_error_and_unmapped_addr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3090448400 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_error_and_unmapped_addr.3090448400' seed=94550637384399400676691306982174631601533954567120489219938810795215541272592 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=94550637384399400676691306982174631601533954567120489219938810795215541272592 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/18.xbar_error_and_unmapped_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all","qual_name":"18.xbar_stress_all.35201837707641273155648021331717554062322727814058968341689979532868650124731","seed":35201837707641273155648021331717554062322727814058968341689979532868650124731,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/18.xbar_stress_all/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/18.xbar_stress_all/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=821675451 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all.821675451' seed=35201837707641273155648021331717554062322727814058968341689979532868650124731 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=35201837707641273155648021331717554062322727814058968341689979532868650124731 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/18.xbar_stress_all/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_rand_reset","qual_name":"18.xbar_stress_all_with_rand_reset.16872829268140818274425400357345503555343089516501190300055135178475497376837","seed":16872829268140818274425400357345503555343089516501190300055135178475497376837,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/18.xbar_stress_all_with_rand_reset/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/18.xbar_stress_all_with_rand_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3578317893 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_rand_reset.3578317893' seed=16872829268140818274425400357345503555343089516501190300055135178475497376837 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=16872829268140818274425400357345503555343089516501190300055135178475497376837 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/18.xbar_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"18.xbar_stress_all_with_error.11284700542038593710969418935948288124812540429420177463096308519535648844836","seed":11284700542038593710969418935948288124812540429420177463096308519535648844836,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/18.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/18.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2860395556 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_error.2860395556' seed=11284700542038593710969418935948288124812540429420177463096308519535648844836 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=11284700542038593710969418935948288124812540429420177463096308519535648844836 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/18.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"18.xbar_stress_all_with_reset_error.50449049221163300173912233193090343788763396065856606059024539636219773846767","seed":50449049221163300173912233193090343788763396065856606059024539636219773846767,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/18.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/18.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2177762543 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_reset_error.2177762543' seed=50449049221163300173912233193090343788763396065856606059024539636219773846767 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=50449049221163300173912233193090343788763396065856606059024539636219773846767 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/18.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke","qual_name":"19.xbar_smoke.52517445806963794421341490112512615627971631228738052216120094983087733695255","seed":52517445806963794421341490112512615627971631228738052216120094983087733695255,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/19.xbar_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/19.xbar_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1172923159 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke.1172923159' seed=52517445806963794421341490112512615627971631228738052216120094983087733695255 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=52517445806963794421341490112512615627971631228738052216120094983087733695255 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/19.xbar_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_zero_delays","qual_name":"19.xbar_smoke_zero_delays.14466480877134215595143710933038887972479894583221485649699392780882421626402","seed":14466480877134215595143710933038887972479894583221485649699392780882421626402,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/19.xbar_smoke_zero_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/19.xbar_smoke_zero_delays/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=704263714 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_zero_delays.704263714' seed=14466480877134215595143710933038887972479894583221485649699392780882421626402 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=14466480877134215595143710933038887972479894583221485649699392780882421626402 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/19.xbar_smoke_zero_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_large_delays","qual_name":"19.xbar_smoke_large_delays.102349078120643708792405826097124542665871385941218234509179768224374841841785","seed":102349078120643708792405826097124542665871385941218234509179768224374841841785,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/19.xbar_smoke_large_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/19.xbar_smoke_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1397397625 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_large_delays.1397397625' seed=102349078120643708792405826097124542665871385941218234509179768224374841841785 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=102349078120643708792405826097124542665871385941218234509179768224374841841785 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/19.xbar_smoke_large_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_slow_rsp","qual_name":"19.xbar_smoke_slow_rsp.10448039903134947606655354810256779924482596367677617543992032002644117462736","seed":10448039903134947606655354810256779924482596367677617543992032002644117462736,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/19.xbar_smoke_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/19.xbar_smoke_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1683922640 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_slow_rsp.1683922640' seed=10448039903134947606655354810256779924482596367677617543992032002644117462736 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=10448039903134947606655354810256779924482596367677617543992032002644117462736 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/19.xbar_smoke_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random","qual_name":"19.xbar_random.78242007283878335478927372246057450729302046585731855735963154386817802602069","seed":78242007283878335478927372246057450729302046585731855735963154386817802602069,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/19.xbar_random/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/19.xbar_random/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1923909205 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random.1923909205' seed=78242007283878335478927372246057450729302046585731855735963154386817802602069 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=78242007283878335478927372246057450729302046585731855735963154386817802602069 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/19.xbar_random/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_zero_delays","qual_name":"19.xbar_random_zero_delays.65789555893918106545096656290423580816264800756154035696043949116147140594493","seed":65789555893918106545096656290423580816264800756154035696043949116147140594493,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/19.xbar_random_zero_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/19.xbar_random_zero_delays/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1689455421 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_zero_delays.1689455421' seed=65789555893918106545096656290423580816264800756154035696043949116147140594493 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=65789555893918106545096656290423580816264800756154035696043949116147140594493 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/19.xbar_random_zero_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_large_delays","qual_name":"19.xbar_random_large_delays.99804781740383937058029564049757399845930315461889554761043586150052012343224","seed":99804781740383937058029564049757399845930315461889554761043586150052012343224,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/19.xbar_random_large_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/19.xbar_random_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=481411000 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_large_delays.481411000' seed=99804781740383937058029564049757399845930315461889554761043586150052012343224 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=99804781740383937058029564049757399845930315461889554761043586150052012343224 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/19.xbar_random_large_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_slow_rsp","qual_name":"19.xbar_random_slow_rsp.38796579865793028715505906491509519195494852689273047262926853498441810327942","seed":38796579865793028715505906491509519195494852689273047262926853498441810327942,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/19.xbar_random_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/19.xbar_random_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=451688838 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_slow_rsp.451688838' seed=38796579865793028715505906491509519195494852689273047262926853498441810327942 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=38796579865793028715505906491509519195494852689273047262926853498441810327942 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/19.xbar_random_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device","qual_name":"19.xbar_access_same_device.53729648034624671068168604762687238879994057663789486236009013734621091598295","seed":53729648034624671068168604762687238879994057663789486236009013734621091598295,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/19.xbar_access_same_device/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/19.xbar_access_same_device/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=927862743 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device.927862743' seed=53729648034624671068168604762687238879994057663789486236009013734621091598295 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=53729648034624671068168604762687238879994057663789486236009013734621091598295 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/19.xbar_access_same_device/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"19.xbar_access_same_device_slow_rsp.49548831258783316120145792377627843544938234456414226824602297664824361053268","seed":49548831258783316120145792377627843544938234456414226824602297664824361053268,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/19.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/19.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=743664724 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device_slow_rsp.743664724' seed=49548831258783316120145792377627843544938234456414226824602297664824361053268 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=49548831258783316120145792377627843544938234456414226824602297664824361053268 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/19.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_same_source","qual_name":"19.xbar_same_source.64627185847938683396188421558467403411674702328211777491221165769161110041824","seed":64627185847938683396188421558467403411674702328211777491221165769161110041824,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/19.xbar_same_source/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/19.xbar_same_source/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3655447776 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_same_source.3655447776' seed=64627185847938683396188421558467403411674702328211777491221165769161110041824 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=64627185847938683396188421558467403411674702328211777491221165769161110041824 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/19.xbar_same_source/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_same_source_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_random","qual_name":"19.xbar_error_random.98712186208735789551722163768984757847585631592676258956105701732842817183236","seed":98712186208735789551722163768984757847585631592676258956105701732842817183236,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/19.xbar_error_random/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/19.xbar_error_random/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1591467524 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_error_random.1591467524' seed=98712186208735789551722163768984757847585631592676258956105701732842817183236 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=98712186208735789551722163768984757847585631592676258956105701732842817183236 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/19.xbar_error_random/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_unmapped_addr","qual_name":"19.xbar_unmapped_addr.76642986826898747521784734449177736461892210012616463086062870383700870503056","seed":76642986826898747521784734449177736461892210012616463086062870383700870503056,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/19.xbar_unmapped_addr/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/19.xbar_unmapped_addr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=262478480 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_unmapped_addr.262478480' seed=76642986826898747521784734449177736461892210012616463086062870383700870503056 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=76642986826898747521784734449177736461892210012616463086062870383700870503056 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/19.xbar_unmapped_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_and_unmapped_addr","qual_name":"19.xbar_error_and_unmapped_addr.61344553973670999482103486870830602491992340624510888329178901756059272386896","seed":61344553973670999482103486870830602491992340624510888329178901756059272386896,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/19.xbar_error_and_unmapped_addr/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/19.xbar_error_and_unmapped_addr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3659831632 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_error_and_unmapped_addr.3659831632' seed=61344553973670999482103486870830602491992340624510888329178901756059272386896 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=61344553973670999482103486870830602491992340624510888329178901756059272386896 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/19.xbar_error_and_unmapped_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all","qual_name":"19.xbar_stress_all.86443407442866632677389287545355952342910485201117046590586532228873371254521","seed":86443407442866632677389287545355952342910485201117046590586532228873371254521,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/19.xbar_stress_all/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/19.xbar_stress_all/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2653421305 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all.2653421305' seed=86443407442866632677389287545355952342910485201117046590586532228873371254521 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=86443407442866632677389287545355952342910485201117046590586532228873371254521 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/19.xbar_stress_all/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_rand_reset","qual_name":"19.xbar_stress_all_with_rand_reset.46336621981517120442956643393592631988667498673978887940420556625301993667487","seed":46336621981517120442956643393592631988667498673978887940420556625301993667487,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/19.xbar_stress_all_with_rand_reset/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/19.xbar_stress_all_with_rand_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3504585631 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_rand_reset.3504585631' seed=46336621981517120442956643393592631988667498673978887940420556625301993667487 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=46336621981517120442956643393592631988667498673978887940420556625301993667487 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/19.xbar_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"19.xbar_stress_all_with_error.64102180141288682869755338664634542140526244758924380297975696884324013077310","seed":64102180141288682869755338664634542140526244758924380297975696884324013077310,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/19.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/19.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1607627582 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_error.1607627582' seed=64102180141288682869755338664634542140526244758924380297975696884324013077310 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=64102180141288682869755338664634542140526244758924380297975696884324013077310 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/19.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"19.xbar_stress_all_with_reset_error.47512495909373649505620373634954701800583891935038626916717467304714267154928","seed":47512495909373649505620373634954701800583891935038626916717467304714267154928,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/19.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/19.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2975226352 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_reset_error.2975226352' seed=47512495909373649505620373634954701800583891935038626916717467304714267154928 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=47512495909373649505620373634954701800583891935038626916717467304714267154928 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/19.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"20.xbar_access_same_device_slow_rsp.32245766062080990711810699768669292766631709068757473885460983153445457726830","seed":32245766062080990711810699768669292766631709068757473885460983153445457726830,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/20.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/20.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1812303214 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device_slow_rsp.1812303214' seed=32245766062080990711810699768669292766631709068757473885460983153445457726830 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=32245766062080990711810699768669292766631709068757473885460983153445457726830 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/20.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"20.xbar_stress_all_with_error.98487151549065616492967853958345323046670669004221080582149551877848012268482","seed":98487151549065616492967853958345323046670669004221080582149551877848012268482,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/20.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/20.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3072435138 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_error.3072435138' seed=98487151549065616492967853958345323046670669004221080582149551877848012268482 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=98487151549065616492967853958345323046670669004221080582149551877848012268482 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/20.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"20.xbar_stress_all_with_reset_error.1457445292191131549549738479785950003824912373212629816411965668482115219234","seed":1457445292191131549549738479785950003824912373212629816411965668482115219234,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/20.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/20.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2412818210 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_reset_error.2412818210' seed=1457445292191131549549738479785950003824912373212629816411965668482115219234 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=1457445292191131549549738479785950003824912373212629816411965668482115219234 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/20.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"21.xbar_access_same_device_slow_rsp.71631185864807037662332253864883636267010331630987947281925813472508795090353","seed":71631185864807037662332253864883636267010331630987947281925813472508795090353,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/21.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/21.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2386228657 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device_slow_rsp.2386228657' seed=71631185864807037662332253864883636267010331630987947281925813472508795090353 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=71631185864807037662332253864883636267010331630987947281925813472508795090353 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/21.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"21.xbar_stress_all_with_error.69054908223864222791395370143174712431548261203087028720610490352549536429688","seed":69054908223864222791395370143174712431548261203087028720610490352549536429688,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/21.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/21.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3961222776 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_error.3961222776' seed=69054908223864222791395370143174712431548261203087028720610490352549536429688 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=69054908223864222791395370143174712431548261203087028720610490352549536429688 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/21.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"21.xbar_stress_all_with_reset_error.96051357529560981285786951217049316016440641271653733014690715547549137221511","seed":96051357529560981285786951217049316016440641271653733014690715547549137221511,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/21.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/21.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1266792327 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_reset_error.1266792327' seed=96051357529560981285786951217049316016440641271653733014690715547549137221511 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=96051357529560981285786951217049316016440641271653733014690715547549137221511 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/21.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"22.xbar_access_same_device_slow_rsp.71832589498768372426555429273303307912162322523997416655552570200405691918912","seed":71832589498768372426555429273303307912162322523997416655552570200405691918912,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/22.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/22.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3943492160 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device_slow_rsp.3943492160' seed=71832589498768372426555429273303307912162322523997416655552570200405691918912 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=71832589498768372426555429273303307912162322523997416655552570200405691918912 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/22.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"22.xbar_stress_all_with_error.44457359051455504389859155759164407228471509700221871864726574269716961276777","seed":44457359051455504389859155759164407228471509700221871864726574269716961276777,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/22.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/22.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4116034409 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_error.4116034409' seed=44457359051455504389859155759164407228471509700221871864726574269716961276777 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=44457359051455504389859155759164407228471509700221871864726574269716961276777 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/22.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"22.xbar_stress_all_with_reset_error.12525320666920217350874658595118637478779280863560679568744272293672575506772","seed":12525320666920217350874658595118637478779280863560679568744272293672575506772,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/22.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/22.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3239254356 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_reset_error.3239254356' seed=12525320666920217350874658595118637478779280863560679568744272293672575506772 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=12525320666920217350874658595118637478779280863560679568744272293672575506772 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/22.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"23.xbar_access_same_device_slow_rsp.18515738782920662400298181734819447194095440080887657049357673427123604118932","seed":18515738782920662400298181734819447194095440080887657049357673427123604118932,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/23.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/23.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3097320852 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device_slow_rsp.3097320852' seed=18515738782920662400298181734819447194095440080887657049357673427123604118932 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=18515738782920662400298181734819447194095440080887657049357673427123604118932 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/23.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"23.xbar_stress_all_with_error.71634442945274682038730544709310991634164588734806693072680475938242331036080","seed":71634442945274682038730544709310991634164588734806693072680475938242331036080,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/23.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/23.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1355434416 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_error.1355434416' seed=71634442945274682038730544709310991634164588734806693072680475938242331036080 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=71634442945274682038730544709310991634164588734806693072680475938242331036080 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/23.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"23.xbar_stress_all_with_reset_error.108310066984753775615461754014236012534237134498066775189890873827569547189930","seed":108310066984753775615461754014236012534237134498066775189890873827569547189930,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/23.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/23.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2056625834 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_reset_error.2056625834' seed=108310066984753775615461754014236012534237134498066775189890873827569547189930 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=108310066984753775615461754014236012534237134498066775189890873827569547189930 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/23.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"24.xbar_access_same_device_slow_rsp.84249792104108584716768436656858709808767571062961720203775315413348480161261","seed":84249792104108584716768436656858709808767571062961720203775315413348480161261,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/24.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/24.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1915721197 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device_slow_rsp.1915721197' seed=84249792104108584716768436656858709808767571062961720203775315413348480161261 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=84249792104108584716768436656858709808767571062961720203775315413348480161261 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/24.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"24.xbar_stress_all_with_error.31589823447753274611394143905226788415661312711168270302843254422998857273295","seed":31589823447753274611394143905226788415661312711168270302843254422998857273295,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/24.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/24.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=983551951 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_error.983551951' seed=31589823447753274611394143905226788415661312711168270302843254422998857273295 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=31589823447753274611394143905226788415661312711168270302843254422998857273295 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/24.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"24.xbar_stress_all_with_reset_error.42054624917421864886932432397832616353974978754300266025858565136612940486244","seed":42054624917421864886932432397832616353974978754300266025858565136612940486244,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/24.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/24.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3299513956 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_reset_error.3299513956' seed=42054624917421864886932432397832616353974978754300266025858565136612940486244 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=42054624917421864886932432397832616353974978754300266025858565136612940486244 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/24.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"25.xbar_access_same_device_slow_rsp.21060891001023523804207841995335145440733812646862434035562193933810248321972","seed":21060891001023523804207841995335145440733812646862434035562193933810248321972,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/25.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/25.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1764887476 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device_slow_rsp.1764887476' seed=21060891001023523804207841995335145440733812646862434035562193933810248321972 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=21060891001023523804207841995335145440733812646862434035562193933810248321972 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/25.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"25.xbar_stress_all_with_error.79200351418165600151779737851867108007404185439131295593325765114765331589163","seed":79200351418165600151779737851867108007404185439131295593325765114765331589163,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/25.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/25.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2039670827 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_error.2039670827' seed=79200351418165600151779737851867108007404185439131295593325765114765331589163 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=79200351418165600151779737851867108007404185439131295593325765114765331589163 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/25.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"25.xbar_stress_all_with_reset_error.47384049859045815246357561841484486565859734704016786037848937508664636938401","seed":47384049859045815246357561841484486565859734704016786037848937508664636938401,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/25.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/25.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1273567393 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_reset_error.1273567393' seed=47384049859045815246357561841484486565859734704016786037848937508664636938401 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=47384049859045815246357561841484486565859734704016786037848937508664636938401 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/25.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"26.xbar_access_same_device_slow_rsp.106114224730020371368966980387605645651486917056434421287285748941093473019736","seed":106114224730020371368966980387605645651486917056434421287285748941093473019736,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/26.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/26.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3738888024 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device_slow_rsp.3738888024' seed=106114224730020371368966980387605645651486917056434421287285748941093473019736 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=106114224730020371368966980387605645651486917056434421287285748941093473019736 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/26.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"26.xbar_stress_all_with_error.24121918170585203991620046501005054744711310256107005802092711565688750006069","seed":24121918170585203991620046501005054744711310256107005802092711565688750006069,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/26.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/26.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=108846901 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_error.108846901' seed=24121918170585203991620046501005054744711310256107005802092711565688750006069 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=24121918170585203991620046501005054744711310256107005802092711565688750006069 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/26.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"26.xbar_stress_all_with_reset_error.87470990677649036569875610321365990797745652791867375552366056666460101517998","seed":87470990677649036569875610321365990797745652791867375552366056666460101517998,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/26.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/26.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=167748270 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_reset_error.167748270' seed=87470990677649036569875610321365990797745652791867375552366056666460101517998 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=87470990677649036569875610321365990797745652791867375552366056666460101517998 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/26.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"27.xbar_access_same_device_slow_rsp.10975409088769242608279751886321681954082197723344374933963377553216885763505","seed":10975409088769242608279751886321681954082197723344374933963377553216885763505,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/27.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/27.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1083452849 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device_slow_rsp.1083452849' seed=10975409088769242608279751886321681954082197723344374933963377553216885763505 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=10975409088769242608279751886321681954082197723344374933963377553216885763505 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/27.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"27.xbar_stress_all_with_error.85731255095648617369843711780696885897767288990601771905783618308404411677523","seed":85731255095648617369843711780696885897767288990601771905783618308404411677523,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/27.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/27.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3491019603 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_error.3491019603' seed=85731255095648617369843711780696885897767288990601771905783618308404411677523 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=85731255095648617369843711780696885897767288990601771905783618308404411677523 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/27.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"27.xbar_stress_all_with_reset_error.8109426026606512396278103309619767708752973432468190882432859989163395520115","seed":8109426026606512396278103309619767708752973432468190882432859989163395520115,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/27.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/27.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2363496051 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_reset_error.2363496051' seed=8109426026606512396278103309619767708752973432468190882432859989163395520115 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=8109426026606512396278103309619767708752973432468190882432859989163395520115 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/27.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"28.xbar_access_same_device_slow_rsp.40741021738497714163155049897127050684016542065217893086733981924997840782635","seed":40741021738497714163155049897127050684016542065217893086733981924997840782635,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/28.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/28.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3698607403 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device_slow_rsp.3698607403' seed=40741021738497714163155049897127050684016542065217893086733981924997840782635 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=40741021738497714163155049897127050684016542065217893086733981924997840782635 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/28.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"28.xbar_stress_all_with_error.705170451400784892719919474627010028985681448863557068493904589294960573787","seed":705170451400784892719919474627010028985681448863557068493904589294960573787,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/28.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/28.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2899508571 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_error.2899508571' seed=705170451400784892719919474627010028985681448863557068493904589294960573787 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=705170451400784892719919474627010028985681448863557068493904589294960573787 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/28.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"28.xbar_stress_all_with_reset_error.103352966485744827582365479449103005505049584014792170067607177991814195656937","seed":103352966485744827582365479449103005505049584014792170067607177991814195656937,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/28.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/28.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4262148329 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_reset_error.4262148329' seed=103352966485744827582365479449103005505049584014792170067607177991814195656937 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=103352966485744827582365479449103005505049584014792170067607177991814195656937 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/28.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"29.xbar_access_same_device_slow_rsp.47636040243838020977937235206709710721757675061061592850819574244519628559844","seed":47636040243838020977937235206709710721757675061061592850819574244519628559844,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/29.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/29.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2866337252 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device_slow_rsp.2866337252' seed=47636040243838020977937235206709710721757675061061592850819574244519628559844 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=47636040243838020977937235206709710721757675061061592850819574244519628559844 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/29.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"29.xbar_stress_all_with_error.46232709883132820631119333554708796895971058076716510714750251005397892760086","seed":46232709883132820631119333554708796895971058076716510714750251005397892760086,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/29.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/29.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1230144022 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_error.1230144022' seed=46232709883132820631119333554708796895971058076716510714750251005397892760086 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=46232709883132820631119333554708796895971058076716510714750251005397892760086 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/29.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"29.xbar_stress_all_with_reset_error.20016577235278899577488970937159999197061983406092036116399258526530002639470","seed":20016577235278899577488970937159999197061983406092036116399258526530002639470,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/29.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/29.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2871941742 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_reset_error.2871941742' seed=20016577235278899577488970937159999197061983406092036116399258526530002639470 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=20016577235278899577488970937159999197061983406092036116399258526530002639470 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/29.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"30.xbar_access_same_device_slow_rsp.56307278041977764957406870818277274847514487829630975577343740502260751502671","seed":56307278041977764957406870818277274847514487829630975577343740502260751502671,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/30.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/30.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1813220687 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device_slow_rsp.1813220687' seed=56307278041977764957406870818277274847514487829630975577343740502260751502671 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=56307278041977764957406870818277274847514487829630975577343740502260751502671 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/30.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"30.xbar_stress_all_with_error.28084265787619222148504924767958466449926318834972744112160110258538422757570","seed":28084265787619222148504924767958466449926318834972744112160110258538422757570,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/30.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/30.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3299109058 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_error.3299109058' seed=28084265787619222148504924767958466449926318834972744112160110258538422757570 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=28084265787619222148504924767958466449926318834972744112160110258538422757570 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/30.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"30.xbar_stress_all_with_reset_error.31142173972713629384223726483045401302971024676332225938630792971818317600289","seed":31142173972713629384223726483045401302971024676332225938630792971818317600289,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/30.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/30.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3809433121 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_reset_error.3809433121' seed=31142173972713629384223726483045401302971024676332225938630792971818317600289 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=31142173972713629384223726483045401302971024676332225938630792971818317600289 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/30.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"31.xbar_access_same_device_slow_rsp.91718237683140122670135424647944428405764697933917921503788087929211049544809","seed":91718237683140122670135424647944428405764697933917921503788087929211049544809,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/31.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/31.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4214033513 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device_slow_rsp.4214033513' seed=91718237683140122670135424647944428405764697933917921503788087929211049544809 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=91718237683140122670135424647944428405764697933917921503788087929211049544809 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/31.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"31.xbar_stress_all_with_error.79569030786339825597690559620193138117182805861869933931527800205229502106526","seed":79569030786339825597690559620193138117182805861869933931527800205229502106526,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/31.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/31.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1738410910 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_error.1738410910' seed=79569030786339825597690559620193138117182805861869933931527800205229502106526 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=79569030786339825597690559620193138117182805861869933931527800205229502106526 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/31.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"31.xbar_stress_all_with_reset_error.62703486627216465883211402042601821754707309747465903645311740802439324102201","seed":62703486627216465883211402042601821754707309747465903645311740802439324102201,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/31.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/31.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=390327865 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_reset_error.390327865' seed=62703486627216465883211402042601821754707309747465903645311740802439324102201 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=62703486627216465883211402042601821754707309747465903645311740802439324102201 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/31.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"32.xbar_access_same_device_slow_rsp.113823411121105190359833218967493739807398822008480075217533539843242533837883","seed":113823411121105190359833218967493739807398822008480075217533539843242533837883,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/32.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/32.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=91479099 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device_slow_rsp.91479099' seed=113823411121105190359833218967493739807398822008480075217533539843242533837883 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=113823411121105190359833218967493739807398822008480075217533539843242533837883 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/32.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"32.xbar_stress_all_with_error.15269163002369841517313035031683224062650429834941534760632138628094304246468","seed":15269163002369841517313035031683224062650429834941534760632138628094304246468,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/32.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/32.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3032799940 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_error.3032799940' seed=15269163002369841517313035031683224062650429834941534760632138628094304246468 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=15269163002369841517313035031683224062650429834941534760632138628094304246468 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/32.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"32.xbar_stress_all_with_reset_error.65742045380586596582185259620759823199942610776576820068200000479861231769439","seed":65742045380586596582185259620759823199942610776576820068200000479861231769439,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/32.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/32.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=48420703 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_reset_error.48420703' seed=65742045380586596582185259620759823199942610776576820068200000479861231769439 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=65742045380586596582185259620759823199942610776576820068200000479861231769439 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/32.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"33.xbar_access_same_device_slow_rsp.69632101269742705455108029829966062720679424516470105900590182529956092198969","seed":69632101269742705455108029829966062720679424516470105900590182529956092198969,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/33.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/33.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2511749177 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device_slow_rsp.2511749177' seed=69632101269742705455108029829966062720679424516470105900590182529956092198969 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=69632101269742705455108029829966062720679424516470105900590182529956092198969 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/33.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"33.xbar_stress_all_with_error.102471537996705412673560561209239326503586772197517622822412683053746856062627","seed":102471537996705412673560561209239326503586772197517622822412683053746856062627,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/33.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/33.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3096112803 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_error.3096112803' seed=102471537996705412673560561209239326503586772197517622822412683053746856062627 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=102471537996705412673560561209239326503586772197517622822412683053746856062627 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/33.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"33.xbar_stress_all_with_reset_error.82636566747592983880290318393145614198638272809742865293762709338574014881374","seed":82636566747592983880290318393145614198638272809742865293762709338574014881374,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/33.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/33.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2137759326 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_reset_error.2137759326' seed=82636566747592983880290318393145614198638272809742865293762709338574014881374 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=82636566747592983880290318393145614198638272809742865293762709338574014881374 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/33.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"34.xbar_access_same_device_slow_rsp.54440905114768854751908760809877767598948836947695869447440769170970575345960","seed":54440905114768854751908760809877767598948836947695869447440769170970575345960,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/34.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/34.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3002046760 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device_slow_rsp.3002046760' seed=54440905114768854751908760809877767598948836947695869447440769170970575345960 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=54440905114768854751908760809877767598948836947695869447440769170970575345960 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/34.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"34.xbar_stress_all_with_error.27978582642572421569900799351034365716338509052095756935038870592354671171535","seed":27978582642572421569900799351034365716338509052095756935038870592354671171535,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/34.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/34.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3415250895 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_error.3415250895' seed=27978582642572421569900799351034365716338509052095756935038870592354671171535 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=27978582642572421569900799351034365716338509052095756935038870592354671171535 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/34.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"34.xbar_stress_all_with_reset_error.61151801226690745295444134899926230567086011544781571499935920950418188602720","seed":61151801226690745295444134899926230567086011544781571499935920950418188602720,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/34.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/34.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3606908256 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_reset_error.3606908256' seed=61151801226690745295444134899926230567086011544781571499935920950418188602720 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=61151801226690745295444134899926230567086011544781571499935920950418188602720 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/34.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"35.xbar_access_same_device_slow_rsp.67781066189492787177708618574658288185571566008000903080113677484782851623892","seed":67781066189492787177708618574658288185571566008000903080113677484782851623892,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/35.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/35.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1790872532 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device_slow_rsp.1790872532' seed=67781066189492787177708618574658288185571566008000903080113677484782851623892 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=67781066189492787177708618574658288185571566008000903080113677484782851623892 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/35.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"35.xbar_stress_all_with_error.29358628814336247857570877863729531304610902745645525434354090607326691517049","seed":29358628814336247857570877863729531304610902745645525434354090607326691517049,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/35.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/35.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=168223353 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_error.168223353' seed=29358628814336247857570877863729531304610902745645525434354090607326691517049 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=29358628814336247857570877863729531304610902745645525434354090607326691517049 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/35.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"35.xbar_stress_all_with_reset_error.70716023395110131156032251195970235190674352815622434973315245541163175129199","seed":70716023395110131156032251195970235190674352815622434973315245541163175129199,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/35.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/35.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2432053359 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_reset_error.2432053359' seed=70716023395110131156032251195970235190674352815622434973315245541163175129199 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=70716023395110131156032251195970235190674352815622434973315245541163175129199 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/35.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"36.xbar_access_same_device_slow_rsp.90380787450579450029137639505373011125169841987721179399386184857444415625","seed":90380787450579450029137639505373011125169841987721179399386184857444415625,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/36.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/36.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2774005897 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device_slow_rsp.2774005897' seed=90380787450579450029137639505373011125169841987721179399386184857444415625 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=90380787450579450029137639505373011125169841987721179399386184857444415625 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/36.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"36.xbar_stress_all_with_error.109393864362271104093175610531161191007854615606581939703283412138505659806695","seed":109393864362271104093175610531161191007854615606581939703283412138505659806695,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/36.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/36.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2215179239 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_error.2215179239' seed=109393864362271104093175610531161191007854615606581939703283412138505659806695 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=109393864362271104093175610531161191007854615606581939703283412138505659806695 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/36.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"36.xbar_stress_all_with_reset_error.78847618024369643378760687735032880265790013635802297866050150933244965136208","seed":78847618024369643378760687735032880265790013635802297866050150933244965136208,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/36.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/36.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3065620304 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_reset_error.3065620304' seed=78847618024369643378760687735032880265790013635802297866050150933244965136208 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=78847618024369643378760687735032880265790013635802297866050150933244965136208 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/36.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"37.xbar_access_same_device_slow_rsp.4423420480000624386357102752816875530531263001956006640709711115766650388364","seed":4423420480000624386357102752816875530531263001956006640709711115766650388364,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/37.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/37.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=928268172 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device_slow_rsp.928268172' seed=4423420480000624386357102752816875530531263001956006640709711115766650388364 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=4423420480000624386357102752816875530531263001956006640709711115766650388364 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/37.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"37.xbar_stress_all_with_error.59206102403184142311445043938753179906626104089050620644190095235969407276300","seed":59206102403184142311445043938753179906626104089050620644190095235969407276300,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/37.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/37.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3507770636 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_error.3507770636' seed=59206102403184142311445043938753179906626104089050620644190095235969407276300 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=59206102403184142311445043938753179906626104089050620644190095235969407276300 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/37.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"37.xbar_stress_all_with_reset_error.60349986535705774344073235686912899483577295700244774137156222056019175920676","seed":60349986535705774344073235686912899483577295700244774137156222056019175920676,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/37.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/37.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3922187300 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_reset_error.3922187300' seed=60349986535705774344073235686912899483577295700244774137156222056019175920676 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=60349986535705774344073235686912899483577295700244774137156222056019175920676 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/37.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"38.xbar_access_same_device_slow_rsp.35759660065803736626591955028202858028433094927852667856041238506279907968139","seed":35759660065803736626591955028202858028433094927852667856041238506279907968139,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/38.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/38.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1000424587 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device_slow_rsp.1000424587' seed=35759660065803736626591955028202858028433094927852667856041238506279907968139 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=35759660065803736626591955028202858028433094927852667856041238506279907968139 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/38.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"38.xbar_stress_all_with_error.54113147349732367352915933499847145727971323430242423174021844736432155588148","seed":54113147349732367352915933499847145727971323430242423174021844736432155588148,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/38.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/38.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=443217460 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_error.443217460' seed=54113147349732367352915933499847145727971323430242423174021844736432155588148 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=54113147349732367352915933499847145727971323430242423174021844736432155588148 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/38.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"38.xbar_stress_all_with_reset_error.88130036584912360971201430374179854859960670391755144855940590543488107493462","seed":88130036584912360971201430374179854859960670391755144855940590543488107493462,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/38.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/38.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=614545494 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_reset_error.614545494' seed=88130036584912360971201430374179854859960670391755144855940590543488107493462 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=88130036584912360971201430374179854859960670391755144855940590543488107493462 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/38.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"39.xbar_access_same_device_slow_rsp.45697921882914025767662594865119469547704700040082143675293194929196950487351","seed":45697921882914025767662594865119469547704700040082143675293194929196950487351,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/39.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/39.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=954859831 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device_slow_rsp.954859831' seed=45697921882914025767662594865119469547704700040082143675293194929196950487351 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=45697921882914025767662594865119469547704700040082143675293194929196950487351 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/39.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"39.xbar_stress_all_with_error.111744760783998952275175107499370820888569225376451077078222187125710186879637","seed":111744760783998952275175107499370820888569225376451077078222187125710186879637,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/39.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/39.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2927630997 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_error.2927630997' seed=111744760783998952275175107499370820888569225376451077078222187125710186879637 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=111744760783998952275175107499370820888569225376451077078222187125710186879637 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/39.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"39.xbar_stress_all_with_reset_error.114447493006006521441838723490636651033771230551309830679001662477382106355332","seed":114447493006006521441838723490636651033771230551309830679001662477382106355332,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/39.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/39.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=804394628 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_reset_error.804394628' seed=114447493006006521441838723490636651033771230551309830679001662477382106355332 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=114447493006006521441838723490636651033771230551309830679001662477382106355332 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/39.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"40.xbar_access_same_device_slow_rsp.32018963978843889701227622404677410809923461645941948713610319939770072859508","seed":32018963978843889701227622404677410809923461645941948713610319939770072859508,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/40.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/40.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3164504948 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device_slow_rsp.3164504948' seed=32018963978843889701227622404677410809923461645941948713610319939770072859508 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=32018963978843889701227622404677410809923461645941948713610319939770072859508 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/40.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"40.xbar_stress_all_with_error.29268872815241035672952127963342065230290075436654225602497078305391348895864","seed":29268872815241035672952127963342065230290075436654225602497078305391348895864,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/40.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/40.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1505579128 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_error.1505579128' seed=29268872815241035672952127963342065230290075436654225602497078305391348895864 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=29268872815241035672952127963342065230290075436654225602497078305391348895864 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/40.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"40.xbar_stress_all_with_reset_error.90001904252873019765953378412063784026137521360415468392166796434901003949423","seed":90001904252873019765953378412063784026137521360415468392166796434901003949423,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/40.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/40.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2095601007 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_reset_error.2095601007' seed=90001904252873019765953378412063784026137521360415468392166796434901003949423 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=90001904252873019765953378412063784026137521360415468392166796434901003949423 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/40.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"41.xbar_access_same_device_slow_rsp.105281388587759600677482789140682212412763245904140156513140781538130692989640","seed":105281388587759600677482789140682212412763245904140156513140781538130692989640,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/41.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/41.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2813387464 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device_slow_rsp.2813387464' seed=105281388587759600677482789140682212412763245904140156513140781538130692989640 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=105281388587759600677482789140682212412763245904140156513140781538130692989640 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/41.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"41.xbar_stress_all_with_error.88197402803100279766883089730765757483557011865144165962893965636361667084952","seed":88197402803100279766883089730765757483557011865144165962893965636361667084952,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/41.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/41.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2708603544 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_error.2708603544' seed=88197402803100279766883089730765757483557011865144165962893965636361667084952 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=88197402803100279766883089730765757483557011865144165962893965636361667084952 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/41.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"41.xbar_stress_all_with_reset_error.24892808131178390124816087380946255514192673458891726668979335958327648496517","seed":24892808131178390124816087380946255514192673458891726668979335958327648496517,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/41.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/41.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1170123653 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_reset_error.1170123653' seed=24892808131178390124816087380946255514192673458891726668979335958327648496517 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=24892808131178390124816087380946255514192673458891726668979335958327648496517 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/41.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"42.xbar_access_same_device_slow_rsp.45800691450541840639312407085959270488224533366130411746077298867980893982146","seed":45800691450541840639312407085959270488224533366130411746077298867980893982146,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/42.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/42.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1044417986 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device_slow_rsp.1044417986' seed=45800691450541840639312407085959270488224533366130411746077298867980893982146 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=45800691450541840639312407085959270488224533366130411746077298867980893982146 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/42.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"42.xbar_stress_all_with_error.51680156713794175479465024337202451978539866481655575053208208016485392906394","seed":51680156713794175479465024337202451978539866481655575053208208016485392906394,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/42.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/42.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3198482586 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_error.3198482586' seed=51680156713794175479465024337202451978539866481655575053208208016485392906394 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=51680156713794175479465024337202451978539866481655575053208208016485392906394 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/42.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"42.xbar_stress_all_with_reset_error.99971233279126191983598265238486249654144852656943103488020662864224940469724","seed":99971233279126191983598265238486249654144852656943103488020662864224940469724,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/42.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/42.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4189335004 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_reset_error.4189335004' seed=99971233279126191983598265238486249654144852656943103488020662864224940469724 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=99971233279126191983598265238486249654144852656943103488020662864224940469724 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/42.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"43.xbar_access_same_device_slow_rsp.103072866881731204209957965013770043797623632528329361466158221071376903374771","seed":103072866881731204209957965013770043797623632528329361466158221071376903374771,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/43.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/43.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3125610419 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device_slow_rsp.3125610419' seed=103072866881731204209957965013770043797623632528329361466158221071376903374771 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=103072866881731204209957965013770043797623632528329361466158221071376903374771 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/43.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"43.xbar_stress_all_with_error.92405089030968507286809539560478957049009191910048186138374152729084116775381","seed":92405089030968507286809539560478957049009191910048186138374152729084116775381,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/43.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/43.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2113843669 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_error.2113843669' seed=92405089030968507286809539560478957049009191910048186138374152729084116775381 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=92405089030968507286809539560478957049009191910048186138374152729084116775381 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/43.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"43.xbar_stress_all_with_reset_error.64943424136833673326710720081479332218858655896036546665227874648864920481352","seed":64943424136833673326710720081479332218858655896036546665227874648864920481352,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/43.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/43.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3994332744 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_reset_error.3994332744' seed=64943424136833673326710720081479332218858655896036546665227874648864920481352 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=64943424136833673326710720081479332218858655896036546665227874648864920481352 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/43.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"44.xbar_access_same_device_slow_rsp.64044066674261987301148037487197793414009035562203538877471916645553271542092","seed":64044066674261987301148037487197793414009035562203538877471916645553271542092,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/44.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/44.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2697793868 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device_slow_rsp.2697793868' seed=64044066674261987301148037487197793414009035562203538877471916645553271542092 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=64044066674261987301148037487197793414009035562203538877471916645553271542092 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/44.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"44.xbar_stress_all_with_error.99774612652121539396034318457759399851656846200311062304977987667647179018422","seed":99774612652121539396034318457759399851656846200311062304977987667647179018422,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/44.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/44.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=182735030 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_error.182735030' seed=99774612652121539396034318457759399851656846200311062304977987667647179018422 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=99774612652121539396034318457759399851656846200311062304977987667647179018422 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/44.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"44.xbar_stress_all_with_reset_error.67022455253209568269822499953355829129171517528137186961886965098776476173300","seed":67022455253209568269822499953355829129171517528137186961886965098776476173300,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/44.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/44.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2109654004 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_reset_error.2109654004' seed=67022455253209568269822499953355829129171517528137186961886965098776476173300 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=67022455253209568269822499953355829129171517528137186961886965098776476173300 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/44.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"45.xbar_access_same_device_slow_rsp.56817735314641096413223362835824722538720405440318928510492032507194361219288","seed":56817735314641096413223362835824722538720405440318928510492032507194361219288,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/45.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/45.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=58427608 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device_slow_rsp.58427608' seed=56817735314641096413223362835824722538720405440318928510492032507194361219288 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=56817735314641096413223362835824722538720405440318928510492032507194361219288 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/45.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"45.xbar_stress_all_with_error.70886079849339073541955829683785272778820147649061648124432218409072990691875","seed":70886079849339073541955829683785272778820147649061648124432218409072990691875,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/45.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/45.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1771381283 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_error.1771381283' seed=70886079849339073541955829683785272778820147649061648124432218409072990691875 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=70886079849339073541955829683785272778820147649061648124432218409072990691875 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/45.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"45.xbar_stress_all_with_reset_error.21569809737252742198488546292776805612702841306063111950646610882370992579809","seed":21569809737252742198488546292776805612702841306063111950646610882370992579809,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/45.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/45.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2510791905 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_reset_error.2510791905' seed=21569809737252742198488546292776805612702841306063111950646610882370992579809 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=21569809737252742198488546292776805612702841306063111950646610882370992579809 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/45.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"46.xbar_access_same_device_slow_rsp.7371193410066059076994019872155225074951873288484275218989535706243296193063","seed":7371193410066059076994019872155225074951873288484275218989535706243296193063,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/46.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/46.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1144318503 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device_slow_rsp.1144318503' seed=7371193410066059076994019872155225074951873288484275218989535706243296193063 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=7371193410066059076994019872155225074951873288484275218989535706243296193063 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/46.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"46.xbar_stress_all_with_error.104683229850203416038350067274747629964059634987235827317008989400777970465591","seed":104683229850203416038350067274747629964059634987235827317008989400777970465591,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/46.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/46.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2980887351 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_error.2980887351' seed=104683229850203416038350067274747629964059634987235827317008989400777970465591 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=104683229850203416038350067274747629964059634987235827317008989400777970465591 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/46.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"46.xbar_stress_all_with_reset_error.15935071753353238758679859373449703146695515554864743495962359510936638221323","seed":15935071753353238758679859373449703146695515554864743495962359510936638221323,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/46.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/46.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=190344203 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_reset_error.190344203' seed=15935071753353238758679859373449703146695515554864743495962359510936638221323 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=15935071753353238758679859373449703146695515554864743495962359510936638221323 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/46.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"47.xbar_access_same_device_slow_rsp.93692117175436654195809874417764920522700863687975035754013065868730404754717","seed":93692117175436654195809874417764920522700863687975035754013065868730404754717,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/47.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/47.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1944638749 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device_slow_rsp.1944638749' seed=93692117175436654195809874417764920522700863687975035754013065868730404754717 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=93692117175436654195809874417764920522700863687975035754013065868730404754717 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/47.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"47.xbar_stress_all_with_error.55514614708591934654401887439789950260358775587734640683674396934750725123159","seed":55514614708591934654401887439789950260358775587734640683674396934750725123159,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/47.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/47.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2585963607 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_error.2585963607' seed=55514614708591934654401887439789950260358775587734640683674396934750725123159 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=55514614708591934654401887439789950260358775587734640683674396934750725123159 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/47.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"47.xbar_stress_all_with_reset_error.90411220148096735745784110954069369505542164307770160797015863925976535659485","seed":90411220148096735745784110954069369505542164307770160797015863925976535659485,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/47.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/47.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1184887773 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_reset_error.1184887773' seed=90411220148096735745784110954069369505542164307770160797015863925976535659485 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=90411220148096735745784110954069369505542164307770160797015863925976535659485 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/47.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"48.xbar_access_same_device_slow_rsp.78140643530556362494712770343374503244993023717423323668161727368993464877291","seed":78140643530556362494712770343374503244993023717423323668161727368993464877291,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/48.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/48.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3598680299 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device_slow_rsp.3598680299' seed=78140643530556362494712770343374503244993023717423323668161727368993464877291 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=78140643530556362494712770343374503244993023717423323668161727368993464877291 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/48.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"48.xbar_stress_all_with_error.52628413349051630231765087863497783015857745206486869238115131514735530722124","seed":52628413349051630231765087863497783015857745206486869238115131514735530722124,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/48.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/48.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=632669004 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_error.632669004' seed=52628413349051630231765087863497783015857745206486869238115131514735530722124 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=52628413349051630231765087863497783015857745206486869238115131514735530722124 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/48.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"48.xbar_stress_all_with_reset_error.16775393731432563750065266606534444302376981182885249560336728199323846989050","seed":16775393731432563750065266606534444302376981182885249560336728199323846989050,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/48.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/48.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=433345786 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_reset_error.433345786' seed=16775393731432563750065266606534444302376981182885249560336728199323846989050 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=16775393731432563750065266606534444302376981182885249560336728199323846989050 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/48.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"49.xbar_access_same_device_slow_rsp.53302401032245931767024039920314326356660447951384717833639735194916137256260","seed":53302401032245931767024039920314326356660447951384717833639735194916137256260,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/49.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/49.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1866777924 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device_slow_rsp.1866777924' seed=53302401032245931767024039920314326356660447951384717833639735194916137256260 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=53302401032245931767024039920314326356660447951384717833639735194916137256260 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/49.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"49.xbar_stress_all_with_error.67188404916362552484322698070386641884647036742106477764015262584509724035701","seed":67188404916362552484322698070386641884647036742106477764015262584509724035701,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/49.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/49.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=721095285 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_error.721095285' seed=67188404916362552484322698070386641884647036742106477764015262584509724035701 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=67188404916362552484322698070386641884647036742106477764015262584509724035701 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/49.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"49.xbar_stress_all_with_reset_error.79382807319992786193720768562426055126556910502843349274419348181613470425781","seed":79382807319992786193720768562426055126556910502843349274419348181613470425781,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/49.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/49.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1629889205 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_mbx-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_reset_error.1629889205' seed=79382807319992786193720768562426055126556910502843349274419348181613470425781 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=79382807319992786193720768562426055126556910502843349274419348181613470425781 --run-dir=/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/49.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]}],"Job cancelled because all of its dependencies failed or were killed.":[{"name":"xbar_mbx","qual_name":"cov_merge","seed":null,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/cov_merge/merged.vdb/cov_merge.log","log_context":[]}],"Job cancelled because one of its dependencies failed or was killed.":[{"name":"xbar_mbx","qual_name":"cov_report","seed":null,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_mbx-sim-vcs/cov_report/cov_report.log","log_context":[]}]}},"passed":0,"total":450,"percent":0.0}