{"block":{"name":"xbar_peri","variant":null,"commit":"a0994129303fcb17a56df9a84a3babc5b4069141","commit_short":"a099412","branch":"master","url":"https://github.com/lowRISC/opentitan/tree/a0994129303fcb17a56df9a84a3babc5b4069141","revision_info":"GitHub Revision: [`a099412`](https://github.com/lowrisc/opentitan/tree/a0994129303fcb17a56df9a84a3babc5b4069141)"},"tool":{"name":"vcs","version":"unknown"},"timestamp":"2026-08-28T21:54:34Z","build_seed":null,"testplan_ref":"https://opentitan.org/book/hw/ip/tlul/data/tlul_testplan.html","stages":{"V1":{"testpoints":{"xbar_smoke":{"tests":{"xbar_smoke":{"max_time":1.5407597534358501,"sim_time":0.0,"passed":0,"total":20,"percent":0.0}},"passed":0,"total":20,"percent":0.0}},"passed":0,"total":20,"percent":0.0},"V2":{"testpoints":{"xbar_base_random_sequence":{"tests":{"xbar_random":{"max_time":1.514024437405169,"sim_time":0.0,"passed":0,"total":20,"percent":0.0}},"passed":0,"total":20,"percent":0.0},"xbar_random_delay":{"tests":{"xbar_smoke_zero_delays":{"max_time":0.9099150290712714,"sim_time":0.0,"passed":0,"total":20,"percent":0.0},"xbar_smoke_large_delays":{"max_time":1.5953913871198893,"sim_time":0.0,"passed":0,"total":20,"percent":0.0},"xbar_smoke_slow_rsp":{"max_time":1.5350759252905846,"sim_time":0.0,"passed":0,"total":20,"percent":0.0},"xbar_random_zero_delays":{"max_time":1.5338749457150698,"sim_time":0.0,"passed":0,"total":20,"percent":0.0},"xbar_random_large_delays":{"max_time":1.5379811441525817,"sim_time":0.0,"passed":0,"total":20,"percent":0.0},"xbar_random_slow_rsp":{"max_time":1.5686959102749825,"sim_time":0.0,"passed":0,"total":20,"percent":0.0}},"passed":0,"total":120,"percent":0.0},"xbar_unmapped_address":{"tests":{"xbar_unmapped_addr":{"max_time":1.5299489488825202,"sim_time":0.0,"passed":0,"total":20,"percent":0.0},"xbar_error_and_unmapped_addr":{"max_time":1.5731175374239683,"sim_time":0.0,"passed":0,"total":20,"percent":0.0}},"passed":0,"total":40,"percent":0.0},"xbar_error_cases":{"tests":{"xbar_error_random":{"max_time":2.10216866992414,"sim_time":0.0,"passed":0,"total":20,"percent":0.0},"xbar_error_and_unmapped_addr":{"max_time":1.5731175374239683,"sim_time":0.0,"passed":0,"total":20,"percent":0.0}},"passed":0,"total":40,"percent":0.0},"xbar_all_access_same_device":{"tests":{"xbar_access_same_device":{"max_time":1.4072275273501873,"sim_time":0.0,"passed":0,"total":20,"percent":0.0},"xbar_access_same_device_slow_rsp":{"max_time":2.4425656255334616,"sim_time":0.0,"passed":0,"total":50,"percent":0.0}},"passed":0,"total":70,"percent":0.0},"xbar_all_hosts_use_same_source_id":{"tests":{"xbar_same_source":{"max_time":1.369571396149695,"sim_time":0.0,"passed":0,"total":20,"percent":0.0}},"passed":0,"total":20,"percent":0.0},"xbar_stress_all":{"tests":{"xbar_stress_all":{"max_time":1.534043436869979,"sim_time":0.0,"passed":0,"total":20,"percent":0.0},"xbar_stress_all_with_error":{"max_time":1.7483660718426108,"sim_time":0.0,"passed":0,"total":50,"percent":0.0}},"passed":0,"total":70,"percent":0.0},"xbar_stress_with_reset":{"tests":{"xbar_stress_all_with_rand_reset":{"max_time":2.1404968425631523,"sim_time":0.0,"passed":0,"total":20,"percent":0.0},"xbar_stress_all_with_reset_error":{"max_time":1.5758332358673215,"sim_time":0.0,"passed":0,"total":50,"percent":0.0}},"passed":0,"total":70,"percent":0.0}},"passed":0,"total":430,"percent":0.0}},"coverage":{"code":{"block":null,"line_statement":null,"branch":null,"condition_expression":null,"toggle":null,"fsm":null},"assertion":null,"functional":null},"cov_report_page":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/cov_report/dashboard.html","vplan_report_page":null,"vplan_coverage":null,"failed_jobs":{"buckets":{"Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$']":[{"name":"xbar_smoke","qual_name":"0.xbar_smoke.25845266437675527906999430806679580586693961763639228623442312420062393305819","seed":25845266437675527906999430806679580586693961763639228623442312420062393305819,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/0.xbar_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/0.xbar_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1034980059 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke.1034980059' seed=25845266437675527906999430806679580586693961763639228623442312420062393305819 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=25845266437675527906999430806679580586693961763639228623442312420062393305819 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/0.xbar_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_zero_delays","qual_name":"0.xbar_smoke_zero_delays.99802627436079825029858119455680775731930725757651227535607758899076838625016","seed":99802627436079825029858119455680775731930725757651227535607758899076838625016,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/0.xbar_smoke_zero_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/0.xbar_smoke_zero_delays/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2832371448 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_zero_delays.2832371448' seed=99802627436079825029858119455680775731930725757651227535607758899076838625016 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=99802627436079825029858119455680775731930725757651227535607758899076838625016 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/0.xbar_smoke_zero_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_large_delays","qual_name":"0.xbar_smoke_large_delays.49709646977738158391590323260082614641417938850805560948428511493906799669273","seed":49709646977738158391590323260082614641417938850805560948428511493906799669273,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/0.xbar_smoke_large_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/0.xbar_smoke_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=121778201 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_large_delays.121778201' seed=49709646977738158391590323260082614641417938850805560948428511493906799669273 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=49709646977738158391590323260082614641417938850805560948428511493906799669273 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/0.xbar_smoke_large_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_slow_rsp","qual_name":"0.xbar_smoke_slow_rsp.14162037706993062276316358928408433090351106909372441215357875828797941693024","seed":14162037706993062276316358928408433090351106909372441215357875828797941693024,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/0.xbar_smoke_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/0.xbar_smoke_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3778230880 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_slow_rsp.3778230880' seed=14162037706993062276316358928408433090351106909372441215357875828797941693024 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=14162037706993062276316358928408433090351106909372441215357875828797941693024 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/0.xbar_smoke_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random","qual_name":"0.xbar_random.90122564233005879044897819898960007498994869580010998817201380737759841127424","seed":90122564233005879044897819898960007498994869580010998817201380737759841127424,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/0.xbar_random/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/0.xbar_random/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1342999552 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random.1342999552' seed=90122564233005879044897819898960007498994869580010998817201380737759841127424 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=90122564233005879044897819898960007498994869580010998817201380737759841127424 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/0.xbar_random/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_zero_delays","qual_name":"0.xbar_random_zero_delays.48925922107634702181979889693083292069024072260761314507242950396297880058868","seed":48925922107634702181979889693083292069024072260761314507242950396297880058868,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/0.xbar_random_zero_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/0.xbar_random_zero_delays/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=140819444 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_zero_delays.140819444' seed=48925922107634702181979889693083292069024072260761314507242950396297880058868 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=48925922107634702181979889693083292069024072260761314507242950396297880058868 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/0.xbar_random_zero_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_large_delays","qual_name":"0.xbar_random_large_delays.42672089598313615220839001028019855480745145649508072216780457297421721848432","seed":42672089598313615220839001028019855480745145649508072216780457297421721848432,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/0.xbar_random_large_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/0.xbar_random_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3458124400 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_large_delays.3458124400' seed=42672089598313615220839001028019855480745145649508072216780457297421721848432 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=42672089598313615220839001028019855480745145649508072216780457297421721848432 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/0.xbar_random_large_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_slow_rsp","qual_name":"0.xbar_random_slow_rsp.27553187483554586404662370295020458718825969253386032769379254335085184854424","seed":27553187483554586404662370295020458718825969253386032769379254335085184854424,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/0.xbar_random_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/0.xbar_random_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1443408280 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_slow_rsp.1443408280' seed=27553187483554586404662370295020458718825969253386032769379254335085184854424 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=27553187483554586404662370295020458718825969253386032769379254335085184854424 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/0.xbar_random_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device","qual_name":"0.xbar_access_same_device.89123296005383522531367686352861868430251479192520767628137733762554372479451","seed":89123296005383522531367686352861868430251479192520767628137733762554372479451,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/0.xbar_access_same_device/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/0.xbar_access_same_device/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=652138971 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device.652138971' seed=89123296005383522531367686352861868430251479192520767628137733762554372479451 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=89123296005383522531367686352861868430251479192520767628137733762554372479451 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/0.xbar_access_same_device/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"0.xbar_access_same_device_slow_rsp.62346437611228733321473091373582294657838039374897618783929458600431729232553","seed":62346437611228733321473091373582294657838039374897618783929458600431729232553,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/0.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/0.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=575916713 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device_slow_rsp.575916713' seed=62346437611228733321473091373582294657838039374897618783929458600431729232553 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=62346437611228733321473091373582294657838039374897618783929458600431729232553 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/0.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_same_source","qual_name":"0.xbar_same_source.72125940074079450894399920024199355788948537997693872379098507348270919531331","seed":72125940074079450894399920024199355788948537997693872379098507348270919531331,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/0.xbar_same_source/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/0.xbar_same_source/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3568909123 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_same_source.3568909123' seed=72125940074079450894399920024199355788948537997693872379098507348270919531331 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=72125940074079450894399920024199355788948537997693872379098507348270919531331 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/0.xbar_same_source/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_same_source_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_random","qual_name":"0.xbar_error_random.56780605335694129845929005075098246876639586434134547529312788424978720672000","seed":56780605335694129845929005075098246876639586434134547529312788424978720672000,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/0.xbar_error_random/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/0.xbar_error_random/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1110493440 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_error_random.1110493440' seed=56780605335694129845929005075098246876639586434134547529312788424978720672000 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=56780605335694129845929005075098246876639586434134547529312788424978720672000 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/0.xbar_error_random/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_unmapped_addr","qual_name":"0.xbar_unmapped_addr.107444315127683527182342015841799207160335543841124834343018884208866945882078","seed":107444315127683527182342015841799207160335543841124834343018884208866945882078,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/0.xbar_unmapped_addr/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/0.xbar_unmapped_addr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3438761950 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_unmapped_addr.3438761950' seed=107444315127683527182342015841799207160335543841124834343018884208866945882078 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=107444315127683527182342015841799207160335543841124834343018884208866945882078 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/0.xbar_unmapped_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_and_unmapped_addr","qual_name":"0.xbar_error_and_unmapped_addr.113542641314299286695346350777240127578573043399117124093057617431797523311628","seed":113542641314299286695346350777240127578573043399117124093057617431797523311628,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/0.xbar_error_and_unmapped_addr/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/0.xbar_error_and_unmapped_addr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3184290828 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_error_and_unmapped_addr.3184290828' seed=113542641314299286695346350777240127578573043399117124093057617431797523311628 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=113542641314299286695346350777240127578573043399117124093057617431797523311628 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/0.xbar_error_and_unmapped_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all","qual_name":"0.xbar_stress_all.73005140573377446424393608017817932829220763705328947558383269842211247886837","seed":73005140573377446424393608017817932829220763705328947558383269842211247886837,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/0.xbar_stress_all/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/0.xbar_stress_all/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2100433397 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all.2100433397' seed=73005140573377446424393608017817932829220763705328947558383269842211247886837 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=73005140573377446424393608017817932829220763705328947558383269842211247886837 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/0.xbar_stress_all/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_rand_reset","qual_name":"0.xbar_stress_all_with_rand_reset.10526826253445922968797033598991084829305080568662245512347889398584244430803","seed":10526826253445922968797033598991084829305080568662245512347889398584244430803,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/0.xbar_stress_all_with_rand_reset/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/0.xbar_stress_all_with_rand_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4281067475 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_rand_reset.4281067475' seed=10526826253445922968797033598991084829305080568662245512347889398584244430803 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=10526826253445922968797033598991084829305080568662245512347889398584244430803 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/0.xbar_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"0.xbar_stress_all_with_error.73089280301715291446511742797285115800329952518018947816257870695570508624050","seed":73089280301715291446511742797285115800329952518018947816257870695570508624050,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/0.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/0.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=672149682 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_error.672149682' seed=73089280301715291446511742797285115800329952518018947816257870695570508624050 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=73089280301715291446511742797285115800329952518018947816257870695570508624050 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/0.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"0.xbar_stress_all_with_reset_error.108286958393929342068841569031359242517443237604322232531062629710611580131281","seed":108286958393929342068841569031359242517443237604322232531062629710611580131281,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/0.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/0.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=178198481 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_reset_error.178198481' seed=108286958393929342068841569031359242517443237604322232531062629710611580131281 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=108286958393929342068841569031359242517443237604322232531062629710611580131281 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/0.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke","qual_name":"1.xbar_smoke.66679458521535303140490137511013149174052910860913498335395473722995890272321","seed":66679458521535303140490137511013149174052910860913498335395473722995890272321,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/1.xbar_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/1.xbar_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1084569665 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke.1084569665' seed=66679458521535303140490137511013149174052910860913498335395473722995890272321 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=66679458521535303140490137511013149174052910860913498335395473722995890272321 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/1.xbar_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_zero_delays","qual_name":"1.xbar_smoke_zero_delays.931096252873204573309749688031358516689001210120669005310878117302279567619","seed":931096252873204573309749688031358516689001210120669005310878117302279567619,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/1.xbar_smoke_zero_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/1.xbar_smoke_zero_delays/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3132586243 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_zero_delays.3132586243' seed=931096252873204573309749688031358516689001210120669005310878117302279567619 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=931096252873204573309749688031358516689001210120669005310878117302279567619 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/1.xbar_smoke_zero_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_large_delays","qual_name":"1.xbar_smoke_large_delays.55899685690130040697533023728661384580579975923655729694910253585212825927537","seed":55899685690130040697533023728661384580579975923655729694910253585212825927537,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/1.xbar_smoke_large_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/1.xbar_smoke_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2936012657 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_large_delays.2936012657' seed=55899685690130040697533023728661384580579975923655729694910253585212825927537 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=55899685690130040697533023728661384580579975923655729694910253585212825927537 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/1.xbar_smoke_large_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_slow_rsp","qual_name":"1.xbar_smoke_slow_rsp.86957037934905728131113686522182156613286741275530454149246295727565327452384","seed":86957037934905728131113686522182156613286741275530454149246295727565327452384,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/1.xbar_smoke_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/1.xbar_smoke_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1692027104 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_slow_rsp.1692027104' seed=86957037934905728131113686522182156613286741275530454149246295727565327452384 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=86957037934905728131113686522182156613286741275530454149246295727565327452384 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/1.xbar_smoke_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random","qual_name":"1.xbar_random.70799741012067061404682408551618579614558313094020725571738480798455087155426","seed":70799741012067061404682408551618579614558313094020725571738480798455087155426,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/1.xbar_random/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/1.xbar_random/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1982777570 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random.1982777570' seed=70799741012067061404682408551618579614558313094020725571738480798455087155426 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=70799741012067061404682408551618579614558313094020725571738480798455087155426 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/1.xbar_random/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_zero_delays","qual_name":"1.xbar_random_zero_delays.21383674567024204369917681339156435797396171462943940182517326924688067880548","seed":21383674567024204369917681339156435797396171462943940182517326924688067880548,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/1.xbar_random_zero_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/1.xbar_random_zero_delays/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=592143972 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_zero_delays.592143972' seed=21383674567024204369917681339156435797396171462943940182517326924688067880548 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=21383674567024204369917681339156435797396171462943940182517326924688067880548 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/1.xbar_random_zero_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_large_delays","qual_name":"1.xbar_random_large_delays.10569941435417898903534935499677897280945964201289400604942526194571917219146","seed":10569941435417898903534935499677897280945964201289400604942526194571917219146,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/1.xbar_random_large_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/1.xbar_random_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3377812810 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_large_delays.3377812810' seed=10569941435417898903534935499677897280945964201289400604942526194571917219146 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=10569941435417898903534935499677897280945964201289400604942526194571917219146 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/1.xbar_random_large_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_slow_rsp","qual_name":"1.xbar_random_slow_rsp.58890138514625953213383557249985359353981029352696759344339770782504713152053","seed":58890138514625953213383557249985359353981029352696759344339770782504713152053,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/1.xbar_random_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/1.xbar_random_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2549048885 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_slow_rsp.2549048885' seed=58890138514625953213383557249985359353981029352696759344339770782504713152053 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=58890138514625953213383557249985359353981029352696759344339770782504713152053 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/1.xbar_random_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device","qual_name":"1.xbar_access_same_device.43155468213041022401913410285129798369184967532327362560881285400766085992766","seed":43155468213041022401913410285129798369184967532327362560881285400766085992766,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/1.xbar_access_same_device/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/1.xbar_access_same_device/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=542249278 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device.542249278' seed=43155468213041022401913410285129798369184967532327362560881285400766085992766 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=43155468213041022401913410285129798369184967532327362560881285400766085992766 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/1.xbar_access_same_device/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"1.xbar_access_same_device_slow_rsp.87838290137704465252677641599723917306725119741990000726749138970156745074446","seed":87838290137704465252677641599723917306725119741990000726749138970156745074446,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/1.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/1.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2491393806 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device_slow_rsp.2491393806' seed=87838290137704465252677641599723917306725119741990000726749138970156745074446 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=87838290137704465252677641599723917306725119741990000726749138970156745074446 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/1.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_same_source","qual_name":"1.xbar_same_source.8594070717176412852504936857883683135399923281800417548777386735107663092901","seed":8594070717176412852504936857883683135399923281800417548777386735107663092901,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/1.xbar_same_source/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/1.xbar_same_source/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=678583461 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_same_source.678583461' seed=8594070717176412852504936857883683135399923281800417548777386735107663092901 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=8594070717176412852504936857883683135399923281800417548777386735107663092901 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/1.xbar_same_source/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_same_source_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_random","qual_name":"1.xbar_error_random.27022627244191650766177233942047707971662518847852486475238404095943466742699","seed":27022627244191650766177233942047707971662518847852486475238404095943466742699,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/1.xbar_error_random/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/1.xbar_error_random/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3579507627 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_error_random.3579507627' seed=27022627244191650766177233942047707971662518847852486475238404095943466742699 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=27022627244191650766177233942047707971662518847852486475238404095943466742699 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/1.xbar_error_random/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_unmapped_addr","qual_name":"1.xbar_unmapped_addr.98771615560045371062088925293535871868501849872455585669046911838894777642289","seed":98771615560045371062088925293535871868501849872455585669046911838894777642289,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/1.xbar_unmapped_addr/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/1.xbar_unmapped_addr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3836947761 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_unmapped_addr.3836947761' seed=98771615560045371062088925293535871868501849872455585669046911838894777642289 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=98771615560045371062088925293535871868501849872455585669046911838894777642289 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/1.xbar_unmapped_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_and_unmapped_addr","qual_name":"1.xbar_error_and_unmapped_addr.61472951217951943339581291050250013492472342201754749410173122404915626096823","seed":61472951217951943339581291050250013492472342201754749410173122404915626096823,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/1.xbar_error_and_unmapped_addr/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/1.xbar_error_and_unmapped_addr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2457581751 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_error_and_unmapped_addr.2457581751' seed=61472951217951943339581291050250013492472342201754749410173122404915626096823 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=61472951217951943339581291050250013492472342201754749410173122404915626096823 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/1.xbar_error_and_unmapped_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all","qual_name":"1.xbar_stress_all.9555262995324950054687916096218385580834831720480559979915446494349470050102","seed":9555262995324950054687916096218385580834831720480559979915446494349470050102,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/1.xbar_stress_all/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/1.xbar_stress_all/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4256016182 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all.4256016182' seed=9555262995324950054687916096218385580834831720480559979915446494349470050102 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=9555262995324950054687916096218385580834831720480559979915446494349470050102 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/1.xbar_stress_all/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_rand_reset","qual_name":"1.xbar_stress_all_with_rand_reset.9148260364230587032017461838345953024501744996904367712922273325793408314982","seed":9148260364230587032017461838345953024501744996904367712922273325793408314982,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/1.xbar_stress_all_with_rand_reset/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/1.xbar_stress_all_with_rand_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2184572518 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_rand_reset.2184572518' seed=9148260364230587032017461838345953024501744996904367712922273325793408314982 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=9148260364230587032017461838345953024501744996904367712922273325793408314982 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/1.xbar_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"1.xbar_stress_all_with_error.4624043866665939471249573127049037236067875866504970215610975492870376278717","seed":4624043866665939471249573127049037236067875866504970215610975492870376278717,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/1.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/1.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=39602877 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_error.39602877' seed=4624043866665939471249573127049037236067875866504970215610975492870376278717 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=4624043866665939471249573127049037236067875866504970215610975492870376278717 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/1.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"1.xbar_stress_all_with_reset_error.113700266311691691827089995098930283810463976604507608935827100768528895709678","seed":113700266311691691827089995098930283810463976604507608935827100768528895709678,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/1.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/1.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=600445422 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_reset_error.600445422' seed=113700266311691691827089995098930283810463976604507608935827100768528895709678 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=113700266311691691827089995098930283810463976604507608935827100768528895709678 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/1.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke","qual_name":"2.xbar_smoke.111568329064043100183948113893391628427309153944510820685062868617995588333070","seed":111568329064043100183948113893391628427309153944510820685062868617995588333070,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/2.xbar_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/2.xbar_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=551939598 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke.551939598' seed=111568329064043100183948113893391628427309153944510820685062868617995588333070 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=111568329064043100183948113893391628427309153944510820685062868617995588333070 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/2.xbar_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_zero_delays","qual_name":"2.xbar_smoke_zero_delays.103674201963625835436245426973189723208814247441166707555054737800376029285677","seed":103674201963625835436245426973189723208814247441166707555054737800376029285677,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/2.xbar_smoke_zero_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/2.xbar_smoke_zero_delays/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3076001069 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_zero_delays.3076001069' seed=103674201963625835436245426973189723208814247441166707555054737800376029285677 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=103674201963625835436245426973189723208814247441166707555054737800376029285677 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/2.xbar_smoke_zero_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_large_delays","qual_name":"2.xbar_smoke_large_delays.9165588602478565866940913664012973229810394510806438172347026517095495852924","seed":9165588602478565866940913664012973229810394510806438172347026517095495852924,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/2.xbar_smoke_large_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/2.xbar_smoke_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1200448380 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_large_delays.1200448380' seed=9165588602478565866940913664012973229810394510806438172347026517095495852924 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=9165588602478565866940913664012973229810394510806438172347026517095495852924 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/2.xbar_smoke_large_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_slow_rsp","qual_name":"2.xbar_smoke_slow_rsp.75217754777120584764463636378691334851281968278818152013292237519392601714502","seed":75217754777120584764463636378691334851281968278818152013292237519392601714502,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/2.xbar_smoke_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/2.xbar_smoke_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3011161926 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_slow_rsp.3011161926' seed=75217754777120584764463636378691334851281968278818152013292237519392601714502 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=75217754777120584764463636378691334851281968278818152013292237519392601714502 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/2.xbar_smoke_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random","qual_name":"2.xbar_random.63398443799013029001642041516211556570141181446397965082122483362532565713076","seed":63398443799013029001642041516211556570141181446397965082122483362532565713076,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/2.xbar_random/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/2.xbar_random/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3577217204 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random.3577217204' seed=63398443799013029001642041516211556570141181446397965082122483362532565713076 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=63398443799013029001642041516211556570141181446397965082122483362532565713076 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/2.xbar_random/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_zero_delays","qual_name":"2.xbar_random_zero_delays.23636322263248495341676418491386184420405450610364762979016877108864329038720","seed":23636322263248495341676418491386184420405450610364762979016877108864329038720,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/2.xbar_random_zero_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/2.xbar_random_zero_delays/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3721247616 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_zero_delays.3721247616' seed=23636322263248495341676418491386184420405450610364762979016877108864329038720 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=23636322263248495341676418491386184420405450610364762979016877108864329038720 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/2.xbar_random_zero_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_large_delays","qual_name":"2.xbar_random_large_delays.115767223175181255135842867361340527809153195730860857491304426316478583040571","seed":115767223175181255135842867361340527809153195730860857491304426316478583040571,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/2.xbar_random_large_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/2.xbar_random_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3094768187 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_large_delays.3094768187' seed=115767223175181255135842867361340527809153195730860857491304426316478583040571 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=115767223175181255135842867361340527809153195730860857491304426316478583040571 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/2.xbar_random_large_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_slow_rsp","qual_name":"2.xbar_random_slow_rsp.27009649088679691018208997370468579563284996103899425495273791747411302628319","seed":27009649088679691018208997370468579563284996103899425495273791747411302628319,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/2.xbar_random_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/2.xbar_random_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=478886879 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_slow_rsp.478886879' seed=27009649088679691018208997370468579563284996103899425495273791747411302628319 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=27009649088679691018208997370468579563284996103899425495273791747411302628319 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/2.xbar_random_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device","qual_name":"2.xbar_access_same_device.111348272034508750088548604123193034450826583068946902971365607921522293374861","seed":111348272034508750088548604123193034450826583068946902971365607921522293374861,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/2.xbar_access_same_device/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/2.xbar_access_same_device/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4228939661 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device.4228939661' seed=111348272034508750088548604123193034450826583068946902971365607921522293374861 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=111348272034508750088548604123193034450826583068946902971365607921522293374861 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/2.xbar_access_same_device/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"2.xbar_access_same_device_slow_rsp.25268534954902592865525322885364292472626269935821873674297588552253264775452","seed":25268534954902592865525322885364292472626269935821873674297588552253264775452,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/2.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/2.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=417220892 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device_slow_rsp.417220892' seed=25268534954902592865525322885364292472626269935821873674297588552253264775452 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=25268534954902592865525322885364292472626269935821873674297588552253264775452 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/2.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_same_source","qual_name":"2.xbar_same_source.37950694161908017111496965683888215703306608930374370787123779376513723068598","seed":37950694161908017111496965683888215703306608930374370787123779376513723068598,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/2.xbar_same_source/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/2.xbar_same_source/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1269493942 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_same_source.1269493942' seed=37950694161908017111496965683888215703306608930374370787123779376513723068598 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=37950694161908017111496965683888215703306608930374370787123779376513723068598 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/2.xbar_same_source/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_same_source_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_random","qual_name":"2.xbar_error_random.107462417583426989080104721018589251931010753025355779025032326944805940214494","seed":107462417583426989080104721018589251931010753025355779025032326944805940214494,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/2.xbar_error_random/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/2.xbar_error_random/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=676969182 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_error_random.676969182' seed=107462417583426989080104721018589251931010753025355779025032326944805940214494 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=107462417583426989080104721018589251931010753025355779025032326944805940214494 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/2.xbar_error_random/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_unmapped_addr","qual_name":"2.xbar_unmapped_addr.115434187256686384312565700462496170638394539969490078579709006129874249746459","seed":115434187256686384312565700462496170638394539969490078579709006129874249746459,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/2.xbar_unmapped_addr/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/2.xbar_unmapped_addr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=184584219 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_unmapped_addr.184584219' seed=115434187256686384312565700462496170638394539969490078579709006129874249746459 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=115434187256686384312565700462496170638394539969490078579709006129874249746459 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/2.xbar_unmapped_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_and_unmapped_addr","qual_name":"2.xbar_error_and_unmapped_addr.111763636867111541236149870348799270100212475490050760530899748988533407117623","seed":111763636867111541236149870348799270100212475490050760530899748988533407117623,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/2.xbar_error_and_unmapped_addr/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/2.xbar_error_and_unmapped_addr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3590222135 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_error_and_unmapped_addr.3590222135' seed=111763636867111541236149870348799270100212475490050760530899748988533407117623 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=111763636867111541236149870348799270100212475490050760530899748988533407117623 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/2.xbar_error_and_unmapped_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all","qual_name":"2.xbar_stress_all.14512122750851295297228418538651181875663203474241087868318134501165061396288","seed":14512122750851295297228418538651181875663203474241087868318134501165061396288,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/2.xbar_stress_all/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/2.xbar_stress_all/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=957634368 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all.957634368' seed=14512122750851295297228418538651181875663203474241087868318134501165061396288 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=14512122750851295297228418538651181875663203474241087868318134501165061396288 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/2.xbar_stress_all/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_rand_reset","qual_name":"2.xbar_stress_all_with_rand_reset.7784164730867521626126680956178770725941666115729492870081029755667351718873","seed":7784164730867521626126680956178770725941666115729492870081029755667351718873,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/2.xbar_stress_all_with_rand_reset/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/2.xbar_stress_all_with_rand_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2364656601 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_rand_reset.2364656601' seed=7784164730867521626126680956178770725941666115729492870081029755667351718873 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=7784164730867521626126680956178770725941666115729492870081029755667351718873 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/2.xbar_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"2.xbar_stress_all_with_error.85911261390727766520563462929011592708472031228866102943356428751706974882620","seed":85911261390727766520563462929011592708472031228866102943356428751706974882620,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/2.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/2.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3011808060 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_error.3011808060' seed=85911261390727766520563462929011592708472031228866102943356428751706974882620 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=85911261390727766520563462929011592708472031228866102943356428751706974882620 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/2.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"2.xbar_stress_all_with_reset_error.28929956970504614832409313235068318681573551362230772841956139860485230226202","seed":28929956970504614832409313235068318681573551362230772841956139860485230226202,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/2.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/2.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3042110234 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_reset_error.3042110234' seed=28929956970504614832409313235068318681573551362230772841956139860485230226202 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=28929956970504614832409313235068318681573551362230772841956139860485230226202 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/2.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke","qual_name":"3.xbar_smoke.70400383204818353920071598352284543279742110899582987404544721483175817817982","seed":70400383204818353920071598352284543279742110899582987404544721483175817817982,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/3.xbar_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/3.xbar_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=705343358 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke.705343358' seed=70400383204818353920071598352284543279742110899582987404544721483175817817982 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=70400383204818353920071598352284543279742110899582987404544721483175817817982 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/3.xbar_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_zero_delays","qual_name":"3.xbar_smoke_zero_delays.88282428198489723019338539032516810732907173060650418037363848992361887453334","seed":88282428198489723019338539032516810732907173060650418037363848992361887453334,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/3.xbar_smoke_zero_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/3.xbar_smoke_zero_delays/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2369671318 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_zero_delays.2369671318' seed=88282428198489723019338539032516810732907173060650418037363848992361887453334 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=88282428198489723019338539032516810732907173060650418037363848992361887453334 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/3.xbar_smoke_zero_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_large_delays","qual_name":"3.xbar_smoke_large_delays.10191219592453029400150557086231607347735929106139713796847301805265638669746","seed":10191219592453029400150557086231607347735929106139713796847301805265638669746,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/3.xbar_smoke_large_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/3.xbar_smoke_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=806895026 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_large_delays.806895026' seed=10191219592453029400150557086231607347735929106139713796847301805265638669746 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=10191219592453029400150557086231607347735929106139713796847301805265638669746 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/3.xbar_smoke_large_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_slow_rsp","qual_name":"3.xbar_smoke_slow_rsp.55235581803537692262303794931994074286610298658704792781680294919610833890556","seed":55235581803537692262303794931994074286610298658704792781680294919610833890556,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/3.xbar_smoke_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/3.xbar_smoke_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=952954108 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_slow_rsp.952954108' seed=55235581803537692262303794931994074286610298658704792781680294919610833890556 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=55235581803537692262303794931994074286610298658704792781680294919610833890556 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/3.xbar_smoke_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random","qual_name":"3.xbar_random.510650583620666038376267788824546050987896188163295204705043150522322593031","seed":510650583620666038376267788824546050987896188163295204705043150522322593031,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/3.xbar_random/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/3.xbar_random/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2211259655 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random.2211259655' seed=510650583620666038376267788824546050987896188163295204705043150522322593031 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=510650583620666038376267788824546050987896188163295204705043150522322593031 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/3.xbar_random/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_zero_delays","qual_name":"3.xbar_random_zero_delays.107079302285755720770387326559038184241057917580846199340175014224856514500844","seed":107079302285755720770387326559038184241057917580846199340175014224856514500844,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/3.xbar_random_zero_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/3.xbar_random_zero_delays/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1885542636 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_zero_delays.1885542636' seed=107079302285755720770387326559038184241057917580846199340175014224856514500844 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=107079302285755720770387326559038184241057917580846199340175014224856514500844 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/3.xbar_random_zero_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_large_delays","qual_name":"3.xbar_random_large_delays.112096748406637702396437704092300570538794188902374567478942054370665524209342","seed":112096748406637702396437704092300570538794188902374567478942054370665524209342,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/3.xbar_random_large_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/3.xbar_random_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3028133566 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_large_delays.3028133566' seed=112096748406637702396437704092300570538794188902374567478942054370665524209342 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=112096748406637702396437704092300570538794188902374567478942054370665524209342 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/3.xbar_random_large_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_slow_rsp","qual_name":"3.xbar_random_slow_rsp.15128671871212854496549493992178344885018086923411120405190843995943317366610","seed":15128671871212854496549493992178344885018086923411120405190843995943317366610,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/3.xbar_random_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/3.xbar_random_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3634718546 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_slow_rsp.3634718546' seed=15128671871212854496549493992178344885018086923411120405190843995943317366610 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=15128671871212854496549493992178344885018086923411120405190843995943317366610 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/3.xbar_random_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device","qual_name":"3.xbar_access_same_device.97484264212589698955993549771691473808138442717136592875713675202092054903484","seed":97484264212589698955993549771691473808138442717136592875713675202092054903484,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/3.xbar_access_same_device/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/3.xbar_access_same_device/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2733406908 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device.2733406908' seed=97484264212589698955993549771691473808138442717136592875713675202092054903484 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=97484264212589698955993549771691473808138442717136592875713675202092054903484 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/3.xbar_access_same_device/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"3.xbar_access_same_device_slow_rsp.10403990271401198034969053609989261573839768554116733496528855452620213868985","seed":10403990271401198034969053609989261573839768554116733496528855452620213868985,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/3.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/3.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1598446009 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device_slow_rsp.1598446009' seed=10403990271401198034969053609989261573839768554116733496528855452620213868985 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=10403990271401198034969053609989261573839768554116733496528855452620213868985 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/3.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_same_source","qual_name":"3.xbar_same_source.80465224017133755093938848723064090012223037453503847495073422423127031514786","seed":80465224017133755093938848723064090012223037453503847495073422423127031514786,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/3.xbar_same_source/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/3.xbar_same_source/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2307098274 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_same_source.2307098274' seed=80465224017133755093938848723064090012223037453503847495073422423127031514786 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=80465224017133755093938848723064090012223037453503847495073422423127031514786 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/3.xbar_same_source/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_same_source_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_random","qual_name":"3.xbar_error_random.19496954227811216853811311734453174677170703370644362992935446963858812481630","seed":19496954227811216853811311734453174677170703370644362992935446963858812481630,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/3.xbar_error_random/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/3.xbar_error_random/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3291525214 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_error_random.3291525214' seed=19496954227811216853811311734453174677170703370644362992935446963858812481630 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=19496954227811216853811311734453174677170703370644362992935446963858812481630 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/3.xbar_error_random/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_unmapped_addr","qual_name":"3.xbar_unmapped_addr.18655879359540197433054680010291295701391294122917649362323299130580138127930","seed":18655879359540197433054680010291295701391294122917649362323299130580138127930,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/3.xbar_unmapped_addr/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/3.xbar_unmapped_addr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=889385530 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_unmapped_addr.889385530' seed=18655879359540197433054680010291295701391294122917649362323299130580138127930 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=18655879359540197433054680010291295701391294122917649362323299130580138127930 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/3.xbar_unmapped_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_and_unmapped_addr","qual_name":"3.xbar_error_and_unmapped_addr.114314674573816566418520901088695597359553750625475387110693052419243378994336","seed":114314674573816566418520901088695597359553750625475387110693052419243378994336,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/3.xbar_error_and_unmapped_addr/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/3.xbar_error_and_unmapped_addr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=309587104 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_error_and_unmapped_addr.309587104' seed=114314674573816566418520901088695597359553750625475387110693052419243378994336 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=114314674573816566418520901088695597359553750625475387110693052419243378994336 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/3.xbar_error_and_unmapped_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all","qual_name":"3.xbar_stress_all.65844784092916195880237827825847980649646185325251742699368054334755476229672","seed":65844784092916195880237827825847980649646185325251742699368054334755476229672,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/3.xbar_stress_all/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/3.xbar_stress_all/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4089335336 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all.4089335336' seed=65844784092916195880237827825847980649646185325251742699368054334755476229672 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=65844784092916195880237827825847980649646185325251742699368054334755476229672 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/3.xbar_stress_all/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_rand_reset","qual_name":"3.xbar_stress_all_with_rand_reset.2623761888286499809022871096768403369352903250593938715391791822990484320086","seed":2623761888286499809022871096768403369352903250593938715391791822990484320086,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/3.xbar_stress_all_with_rand_reset/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/3.xbar_stress_all_with_rand_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3446288214 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_rand_reset.3446288214' seed=2623761888286499809022871096768403369352903250593938715391791822990484320086 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=2623761888286499809022871096768403369352903250593938715391791822990484320086 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/3.xbar_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"3.xbar_stress_all_with_error.23767362826757157270025784015181046522550196544539503747328936966051532365992","seed":23767362826757157270025784015181046522550196544539503747328936966051532365992,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/3.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/3.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3224363176 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_error.3224363176' seed=23767362826757157270025784015181046522550196544539503747328936966051532365992 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=23767362826757157270025784015181046522550196544539503747328936966051532365992 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/3.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"3.xbar_stress_all_with_reset_error.58566850874895943299620979086398772612180256889980976912123297038046252996904","seed":58566850874895943299620979086398772612180256889980976912123297038046252996904,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/3.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/3.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=918264104 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_reset_error.918264104' seed=58566850874895943299620979086398772612180256889980976912123297038046252996904 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=58566850874895943299620979086398772612180256889980976912123297038046252996904 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/3.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke","qual_name":"4.xbar_smoke.94602854671617995099413351934443354276801342132591389855203787951196271517402","seed":94602854671617995099413351934443354276801342132591389855203787951196271517402,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/4.xbar_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/4.xbar_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3016203994 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke.3016203994' seed=94602854671617995099413351934443354276801342132591389855203787951196271517402 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=94602854671617995099413351934443354276801342132591389855203787951196271517402 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/4.xbar_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_zero_delays","qual_name":"4.xbar_smoke_zero_delays.28259891471584696418879969508886017742201796865541717584637823662928726451136","seed":28259891471584696418879969508886017742201796865541717584637823662928726451136,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/4.xbar_smoke_zero_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/4.xbar_smoke_zero_delays/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2939806656 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_zero_delays.2939806656' seed=28259891471584696418879969508886017742201796865541717584637823662928726451136 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=28259891471584696418879969508886017742201796865541717584637823662928726451136 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/4.xbar_smoke_zero_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_large_delays","qual_name":"4.xbar_smoke_large_delays.28688308209353771356888384029107375413419660212234717849763651133570231339023","seed":28688308209353771356888384029107375413419660212234717849763651133570231339023,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/4.xbar_smoke_large_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/4.xbar_smoke_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2007271439 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_large_delays.2007271439' seed=28688308209353771356888384029107375413419660212234717849763651133570231339023 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=28688308209353771356888384029107375413419660212234717849763651133570231339023 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/4.xbar_smoke_large_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_slow_rsp","qual_name":"4.xbar_smoke_slow_rsp.45553168059894153514891772673584282577986718680511073270392008736903701311078","seed":45553168059894153514891772673584282577986718680511073270392008736903701311078,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/4.xbar_smoke_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/4.xbar_smoke_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=141405798 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_slow_rsp.141405798' seed=45553168059894153514891772673584282577986718680511073270392008736903701311078 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=45553168059894153514891772673584282577986718680511073270392008736903701311078 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/4.xbar_smoke_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random","qual_name":"4.xbar_random.107677158034976196464001975057066568302827128928276277300823321710885530356602","seed":107677158034976196464001975057066568302827128928276277300823321710885530356602,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/4.xbar_random/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/4.xbar_random/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3882208122 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random.3882208122' seed=107677158034976196464001975057066568302827128928276277300823321710885530356602 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=107677158034976196464001975057066568302827128928276277300823321710885530356602 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/4.xbar_random/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_zero_delays","qual_name":"4.xbar_random_zero_delays.84075700081144555354984812593456208799610995969322455009205152832920527342922","seed":84075700081144555354984812593456208799610995969322455009205152832920527342922,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/4.xbar_random_zero_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/4.xbar_random_zero_delays/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1471712586 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_zero_delays.1471712586' seed=84075700081144555354984812593456208799610995969322455009205152832920527342922 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=84075700081144555354984812593456208799610995969322455009205152832920527342922 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/4.xbar_random_zero_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_large_delays","qual_name":"4.xbar_random_large_delays.19759850327152282297476772221879103618790638407085624124358715629974261506359","seed":19759850327152282297476772221879103618790638407085624124358715629974261506359,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/4.xbar_random_large_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/4.xbar_random_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2849153335 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_large_delays.2849153335' seed=19759850327152282297476772221879103618790638407085624124358715629974261506359 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=19759850327152282297476772221879103618790638407085624124358715629974261506359 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/4.xbar_random_large_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_slow_rsp","qual_name":"4.xbar_random_slow_rsp.97346606616456435819959830232946733558888374366932556015833749944428826522364","seed":97346606616456435819959830232946733558888374366932556015833749944428826522364,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/4.xbar_random_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/4.xbar_random_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2504061692 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_slow_rsp.2504061692' seed=97346606616456435819959830232946733558888374366932556015833749944428826522364 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=97346606616456435819959830232946733558888374366932556015833749944428826522364 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/4.xbar_random_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device","qual_name":"4.xbar_access_same_device.42147399052632648875096925302460497687821404969290222265348830456845219266726","seed":42147399052632648875096925302460497687821404969290222265348830456845219266726,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/4.xbar_access_same_device/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/4.xbar_access_same_device/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2049310886 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device.2049310886' seed=42147399052632648875096925302460497687821404969290222265348830456845219266726 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=42147399052632648875096925302460497687821404969290222265348830456845219266726 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/4.xbar_access_same_device/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"4.xbar_access_same_device_slow_rsp.94920835459514314898089134490655550222378196494806189947400403206212839354696","seed":94920835459514314898089134490655550222378196494806189947400403206212839354696,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/4.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/4.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4070912328 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device_slow_rsp.4070912328' seed=94920835459514314898089134490655550222378196494806189947400403206212839354696 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=94920835459514314898089134490655550222378196494806189947400403206212839354696 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/4.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_same_source","qual_name":"4.xbar_same_source.98967981905251015598942148782724432613851085180333630558685933772293246634818","seed":98967981905251015598942148782724432613851085180333630558685933772293246634818,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/4.xbar_same_source/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/4.xbar_same_source/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=895830850 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_same_source.895830850' seed=98967981905251015598942148782724432613851085180333630558685933772293246634818 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=98967981905251015598942148782724432613851085180333630558685933772293246634818 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/4.xbar_same_source/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_same_source_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_random","qual_name":"4.xbar_error_random.95955127478493507978028556297590743249462016452413981596029429024232310735854","seed":95955127478493507978028556297590743249462016452413981596029429024232310735854,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/4.xbar_error_random/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/4.xbar_error_random/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2797503470 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_error_random.2797503470' seed=95955127478493507978028556297590743249462016452413981596029429024232310735854 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=95955127478493507978028556297590743249462016452413981596029429024232310735854 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/4.xbar_error_random/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_unmapped_addr","qual_name":"4.xbar_unmapped_addr.109148345246202622898626138463684497991917314644893459331360246471909881548977","seed":109148345246202622898626138463684497991917314644893459331360246471909881548977,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/4.xbar_unmapped_addr/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/4.xbar_unmapped_addr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2618953905 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_unmapped_addr.2618953905' seed=109148345246202622898626138463684497991917314644893459331360246471909881548977 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=109148345246202622898626138463684497991917314644893459331360246471909881548977 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/4.xbar_unmapped_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_and_unmapped_addr","qual_name":"4.xbar_error_and_unmapped_addr.11155378848503699367799723894812993288484933003138328199019588098695616865357","seed":11155378848503699367799723894812993288484933003138328199019588098695616865357,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/4.xbar_error_and_unmapped_addr/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/4.xbar_error_and_unmapped_addr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1743332429 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_error_and_unmapped_addr.1743332429' seed=11155378848503699367799723894812993288484933003138328199019588098695616865357 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=11155378848503699367799723894812993288484933003138328199019588098695616865357 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/4.xbar_error_and_unmapped_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all","qual_name":"4.xbar_stress_all.66160984515535054293104226964842623944832847378902688682213413179567009807854","seed":66160984515535054293104226964842623944832847378902688682213413179567009807854,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/4.xbar_stress_all/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/4.xbar_stress_all/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2223357422 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all.2223357422' seed=66160984515535054293104226964842623944832847378902688682213413179567009807854 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=66160984515535054293104226964842623944832847378902688682213413179567009807854 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/4.xbar_stress_all/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_rand_reset","qual_name":"4.xbar_stress_all_with_rand_reset.47320030827703419852890582935065338827875723479659016101419782435306953465083","seed":47320030827703419852890582935065338827875723479659016101419782435306953465083,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/4.xbar_stress_all_with_rand_reset/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/4.xbar_stress_all_with_rand_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4168834299 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_rand_reset.4168834299' seed=47320030827703419852890582935065338827875723479659016101419782435306953465083 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=47320030827703419852890582935065338827875723479659016101419782435306953465083 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/4.xbar_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"4.xbar_stress_all_with_error.41197297448731306963256990546900690713702160466506722935083527865918615221248","seed":41197297448731306963256990546900690713702160466506722935083527865918615221248,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/4.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/4.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=434402304 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_error.434402304' seed=41197297448731306963256990546900690713702160466506722935083527865918615221248 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=41197297448731306963256990546900690713702160466506722935083527865918615221248 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/4.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"4.xbar_stress_all_with_reset_error.49643615987845055357931302736086664858862283823626665547273004357748990717169","seed":49643615987845055357931302736086664858862283823626665547273004357748990717169,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/4.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/4.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4213222641 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_reset_error.4213222641' seed=49643615987845055357931302736086664858862283823626665547273004357748990717169 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=49643615987845055357931302736086664858862283823626665547273004357748990717169 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/4.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke","qual_name":"5.xbar_smoke.28827864883817638129134177760420749012421903698869357177305708537715348210180","seed":28827864883817638129134177760420749012421903698869357177305708537715348210180,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/5.xbar_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/5.xbar_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=957350404 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke.957350404' seed=28827864883817638129134177760420749012421903698869357177305708537715348210180 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=28827864883817638129134177760420749012421903698869357177305708537715348210180 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/5.xbar_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_zero_delays","qual_name":"5.xbar_smoke_zero_delays.82164494506459135835920361430600002975281640353260887509562061092166414881996","seed":82164494506459135835920361430600002975281640353260887509562061092166414881996,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/5.xbar_smoke_zero_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/5.xbar_smoke_zero_delays/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1113576652 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_zero_delays.1113576652' seed=82164494506459135835920361430600002975281640353260887509562061092166414881996 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=82164494506459135835920361430600002975281640353260887509562061092166414881996 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/5.xbar_smoke_zero_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_large_delays","qual_name":"5.xbar_smoke_large_delays.85843438868160897056556544917476550173027667925835952345553906945320370954840","seed":85843438868160897056556544917476550173027667925835952345553906945320370954840,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/5.xbar_smoke_large_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/5.xbar_smoke_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=909912 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_large_delays.909912' seed=85843438868160897056556544917476550173027667925835952345553906945320370954840 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=85843438868160897056556544917476550173027667925835952345553906945320370954840 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/5.xbar_smoke_large_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_slow_rsp","qual_name":"5.xbar_smoke_slow_rsp.111816326646948299726616636040688679619419995457812675391482636488305459257223","seed":111816326646948299726616636040688679619419995457812675391482636488305459257223,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/5.xbar_smoke_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/5.xbar_smoke_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2856247175 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_slow_rsp.2856247175' seed=111816326646948299726616636040688679619419995457812675391482636488305459257223 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=111816326646948299726616636040688679619419995457812675391482636488305459257223 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/5.xbar_smoke_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random","qual_name":"5.xbar_random.82798770080744503617020932992886108398826093386783593974502629929272930196318","seed":82798770080744503617020932992886108398826093386783593974502629929272930196318,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/5.xbar_random/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/5.xbar_random/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1584913246 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random.1584913246' seed=82798770080744503617020932992886108398826093386783593974502629929272930196318 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=82798770080744503617020932992886108398826093386783593974502629929272930196318 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/5.xbar_random/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_zero_delays","qual_name":"5.xbar_random_zero_delays.47325918255673475428475856200192008931224485091938280990193753434761353975552","seed":47325918255673475428475856200192008931224485091938280990193753434761353975552,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/5.xbar_random_zero_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/5.xbar_random_zero_delays/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2031310592 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_zero_delays.2031310592' seed=47325918255673475428475856200192008931224485091938280990193753434761353975552 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=47325918255673475428475856200192008931224485091938280990193753434761353975552 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/5.xbar_random_zero_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_large_delays","qual_name":"5.xbar_random_large_delays.73390180260634561212696455377791393683555300991510715929445207285179245502254","seed":73390180260634561212696455377791393683555300991510715929445207285179245502254,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/5.xbar_random_large_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/5.xbar_random_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=714448686 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_large_delays.714448686' seed=73390180260634561212696455377791393683555300991510715929445207285179245502254 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=73390180260634561212696455377791393683555300991510715929445207285179245502254 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/5.xbar_random_large_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_slow_rsp","qual_name":"5.xbar_random_slow_rsp.48313588136920381003974189309115540553626717240553441841815554938371508007231","seed":48313588136920381003974189309115540553626717240553441841815554938371508007231,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/5.xbar_random_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/5.xbar_random_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4260622655 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_slow_rsp.4260622655' seed=48313588136920381003974189309115540553626717240553441841815554938371508007231 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=48313588136920381003974189309115540553626717240553441841815554938371508007231 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/5.xbar_random_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device","qual_name":"5.xbar_access_same_device.96684563730243997614715963506839927431447801078399301027756529596820635774598","seed":96684563730243997614715963506839927431447801078399301027756529596820635774598,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/5.xbar_access_same_device/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/5.xbar_access_same_device/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3546017414 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device.3546017414' seed=96684563730243997614715963506839927431447801078399301027756529596820635774598 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=96684563730243997614715963506839927431447801078399301027756529596820635774598 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/5.xbar_access_same_device/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"5.xbar_access_same_device_slow_rsp.61125246561331097852424146254505400991985565104965461359565259217295863396703","seed":61125246561331097852424146254505400991985565104965461359565259217295863396703,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/5.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/5.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4003936607 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device_slow_rsp.4003936607' seed=61125246561331097852424146254505400991985565104965461359565259217295863396703 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=61125246561331097852424146254505400991985565104965461359565259217295863396703 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/5.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_same_source","qual_name":"5.xbar_same_source.114470057038615068939993497525280980606694366378877770352533416682814862524798","seed":114470057038615068939993497525280980606694366378877770352533416682814862524798,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/5.xbar_same_source/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/5.xbar_same_source/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=622330238 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_same_source.622330238' seed=114470057038615068939993497525280980606694366378877770352533416682814862524798 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=114470057038615068939993497525280980606694366378877770352533416682814862524798 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/5.xbar_same_source/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_same_source_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_random","qual_name":"5.xbar_error_random.18451070468315364698099545808711493924195412165728561241490559345597974860020","seed":18451070468315364698099545808711493924195412165728561241490559345597974860020,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/5.xbar_error_random/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/5.xbar_error_random/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1694519540 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_error_random.1694519540' seed=18451070468315364698099545808711493924195412165728561241490559345597974860020 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=18451070468315364698099545808711493924195412165728561241490559345597974860020 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/5.xbar_error_random/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_unmapped_addr","qual_name":"5.xbar_unmapped_addr.23031461139779826167957796631981945704401712463680001790966825349698061129558","seed":23031461139779826167957796631981945704401712463680001790966825349698061129558,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/5.xbar_unmapped_addr/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/5.xbar_unmapped_addr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3061897046 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_unmapped_addr.3061897046' seed=23031461139779826167957796631981945704401712463680001790966825349698061129558 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=23031461139779826167957796631981945704401712463680001790966825349698061129558 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/5.xbar_unmapped_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_and_unmapped_addr","qual_name":"5.xbar_error_and_unmapped_addr.72454981722480186850032385824976275943391320743729346668568762346122393097263","seed":72454981722480186850032385824976275943391320743729346668568762346122393097263,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/5.xbar_error_and_unmapped_addr/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/5.xbar_error_and_unmapped_addr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2927825967 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_error_and_unmapped_addr.2927825967' seed=72454981722480186850032385824976275943391320743729346668568762346122393097263 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=72454981722480186850032385824976275943391320743729346668568762346122393097263 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/5.xbar_error_and_unmapped_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all","qual_name":"5.xbar_stress_all.64422990414356039968297077761674378752692994108162437484341888326640396509256","seed":64422990414356039968297077761674378752692994108162437484341888326640396509256,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/5.xbar_stress_all/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/5.xbar_stress_all/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4178419784 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all.4178419784' seed=64422990414356039968297077761674378752692994108162437484341888326640396509256 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=64422990414356039968297077761674378752692994108162437484341888326640396509256 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/5.xbar_stress_all/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_rand_reset","qual_name":"5.xbar_stress_all_with_rand_reset.91998138815928523924809683967818697478613308745185299929202471987444379315868","seed":91998138815928523924809683967818697478613308745185299929202471987444379315868,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/5.xbar_stress_all_with_rand_reset/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/5.xbar_stress_all_with_rand_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1664380572 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_rand_reset.1664380572' seed=91998138815928523924809683967818697478613308745185299929202471987444379315868 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=91998138815928523924809683967818697478613308745185299929202471987444379315868 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/5.xbar_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"5.xbar_stress_all_with_error.72359323508318292305176204483361705873787888093563463463191912738100356270313","seed":72359323508318292305176204483361705873787888093563463463191912738100356270313,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/5.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/5.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2460961001 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_error.2460961001' seed=72359323508318292305176204483361705873787888093563463463191912738100356270313 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=72359323508318292305176204483361705873787888093563463463191912738100356270313 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/5.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"5.xbar_stress_all_with_reset_error.1861330697624220659627616484645383811293058220529300319383157608463429770081","seed":1861330697624220659627616484645383811293058220529300319383157608463429770081,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/5.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/5.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3897531233 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_reset_error.3897531233' seed=1861330697624220659627616484645383811293058220529300319383157608463429770081 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=1861330697624220659627616484645383811293058220529300319383157608463429770081 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/5.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke","qual_name":"6.xbar_smoke.91344969186560757563713668499398287244923949526128767590596367456445242009527","seed":91344969186560757563713668499398287244923949526128767590596367456445242009527,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/6.xbar_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/6.xbar_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1369696183 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke.1369696183' seed=91344969186560757563713668499398287244923949526128767590596367456445242009527 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=91344969186560757563713668499398287244923949526128767590596367456445242009527 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/6.xbar_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_zero_delays","qual_name":"6.xbar_smoke_zero_delays.42404008739566111477225987206086661232555022734061759509962060716422512459562","seed":42404008739566111477225987206086661232555022734061759509962060716422512459562,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/6.xbar_smoke_zero_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/6.xbar_smoke_zero_delays/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2227912490 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_zero_delays.2227912490' seed=42404008739566111477225987206086661232555022734061759509962060716422512459562 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=42404008739566111477225987206086661232555022734061759509962060716422512459562 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/6.xbar_smoke_zero_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_large_delays","qual_name":"6.xbar_smoke_large_delays.49066576166354379780465335498747118496944360072154081488429225653042564924906","seed":49066576166354379780465335498747118496944360072154081488429225653042564924906,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/6.xbar_smoke_large_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/6.xbar_smoke_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2300937706 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_large_delays.2300937706' seed=49066576166354379780465335498747118496944360072154081488429225653042564924906 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=49066576166354379780465335498747118496944360072154081488429225653042564924906 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/6.xbar_smoke_large_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_slow_rsp","qual_name":"6.xbar_smoke_slow_rsp.29853627974211507675814453638559620449517169149886997944840987141647722140722","seed":29853627974211507675814453638559620449517169149886997944840987141647722140722,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/6.xbar_smoke_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/6.xbar_smoke_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2593707058 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_slow_rsp.2593707058' seed=29853627974211507675814453638559620449517169149886997944840987141647722140722 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=29853627974211507675814453638559620449517169149886997944840987141647722140722 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/6.xbar_smoke_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random","qual_name":"6.xbar_random.3613328682227070539162965259423978898469625431796429479005955682913456150079","seed":3613328682227070539162965259423978898469625431796429479005955682913456150079,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/6.xbar_random/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/6.xbar_random/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2647316031 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random.2647316031' seed=3613328682227070539162965259423978898469625431796429479005955682913456150079 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=3613328682227070539162965259423978898469625431796429479005955682913456150079 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/6.xbar_random/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_zero_delays","qual_name":"6.xbar_random_zero_delays.79696370284655542723647586144300285213131865036242836084303903983491500545887","seed":79696370284655542723647586144300285213131865036242836084303903983491500545887,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/6.xbar_random_zero_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/6.xbar_random_zero_delays/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1838225247 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_zero_delays.1838225247' seed=79696370284655542723647586144300285213131865036242836084303903983491500545887 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=79696370284655542723647586144300285213131865036242836084303903983491500545887 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/6.xbar_random_zero_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_large_delays","qual_name":"6.xbar_random_large_delays.37992171220252043150512188377838063274917434596784148299655887082744714189648","seed":37992171220252043150512188377838063274917434596784148299655887082744714189648,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/6.xbar_random_large_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/6.xbar_random_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1322081104 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_large_delays.1322081104' seed=37992171220252043150512188377838063274917434596784148299655887082744714189648 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=37992171220252043150512188377838063274917434596784148299655887082744714189648 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/6.xbar_random_large_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_slow_rsp","qual_name":"6.xbar_random_slow_rsp.51421525971334091219322480931907094943368642029064426640771401069572015452453","seed":51421525971334091219322480931907094943368642029064426640771401069572015452453,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/6.xbar_random_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/6.xbar_random_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1985933605 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_slow_rsp.1985933605' seed=51421525971334091219322480931907094943368642029064426640771401069572015452453 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=51421525971334091219322480931907094943368642029064426640771401069572015452453 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/6.xbar_random_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device","qual_name":"6.xbar_access_same_device.115786045923944575474651252642319661918745248500096835391766406843288035009804","seed":115786045923944575474651252642319661918745248500096835391766406843288035009804,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/6.xbar_access_same_device/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/6.xbar_access_same_device/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2771133708 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device.2771133708' seed=115786045923944575474651252642319661918745248500096835391766406843288035009804 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=115786045923944575474651252642319661918745248500096835391766406843288035009804 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/6.xbar_access_same_device/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"6.xbar_access_same_device_slow_rsp.111609769298814903509476165947050054356356520322017950798336377460171633367570","seed":111609769298814903509476165947050054356356520322017950798336377460171633367570,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/6.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/6.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3205536274 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device_slow_rsp.3205536274' seed=111609769298814903509476165947050054356356520322017950798336377460171633367570 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=111609769298814903509476165947050054356356520322017950798336377460171633367570 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/6.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_same_source","qual_name":"6.xbar_same_source.75954448297721393758794303704272162614452642681160687251461544177324004998207","seed":75954448297721393758794303704272162614452642681160687251461544177324004998207,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/6.xbar_same_source/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/6.xbar_same_source/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2702703679 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_same_source.2702703679' seed=75954448297721393758794303704272162614452642681160687251461544177324004998207 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=75954448297721393758794303704272162614452642681160687251461544177324004998207 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/6.xbar_same_source/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_same_source_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_random","qual_name":"6.xbar_error_random.37889036378148443106113328117559638420715100417054054726422093724615964754782","seed":37889036378148443106113328117559638420715100417054054726422093724615964754782,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/6.xbar_error_random/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/6.xbar_error_random/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=400687966 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_error_random.400687966' seed=37889036378148443106113328117559638420715100417054054726422093724615964754782 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=37889036378148443106113328117559638420715100417054054726422093724615964754782 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/6.xbar_error_random/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_unmapped_addr","qual_name":"6.xbar_unmapped_addr.72334455745620389636404858052729549524574007776454443343105030879183790148010","seed":72334455745620389636404858052729549524574007776454443343105030879183790148010,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/6.xbar_unmapped_addr/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/6.xbar_unmapped_addr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=942148010 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_unmapped_addr.942148010' seed=72334455745620389636404858052729549524574007776454443343105030879183790148010 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=72334455745620389636404858052729549524574007776454443343105030879183790148010 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/6.xbar_unmapped_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_and_unmapped_addr","qual_name":"6.xbar_error_and_unmapped_addr.33071971496751067585081515469717581341843106665522858746463861909501103320055","seed":33071971496751067585081515469717581341843106665522858746463861909501103320055,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/6.xbar_error_and_unmapped_addr/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/6.xbar_error_and_unmapped_addr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1340615671 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_error_and_unmapped_addr.1340615671' seed=33071971496751067585081515469717581341843106665522858746463861909501103320055 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=33071971496751067585081515469717581341843106665522858746463861909501103320055 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/6.xbar_error_and_unmapped_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all","qual_name":"6.xbar_stress_all.54374644468116797121831523743835728468819633932122577498352360022092662067436","seed":54374644468116797121831523743835728468819633932122577498352360022092662067436,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/6.xbar_stress_all/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/6.xbar_stress_all/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1042960620 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all.1042960620' seed=54374644468116797121831523743835728468819633932122577498352360022092662067436 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=54374644468116797121831523743835728468819633932122577498352360022092662067436 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/6.xbar_stress_all/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_rand_reset","qual_name":"6.xbar_stress_all_with_rand_reset.58329264558756694349022444776375090223608934243835291012831049668954911349317","seed":58329264558756694349022444776375090223608934243835291012831049668954911349317,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/6.xbar_stress_all_with_rand_reset/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/6.xbar_stress_all_with_rand_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=100080197 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_rand_reset.100080197' seed=58329264558756694349022444776375090223608934243835291012831049668954911349317 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=58329264558756694349022444776375090223608934243835291012831049668954911349317 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/6.xbar_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"6.xbar_stress_all_with_error.4899039531674917731436685899536663953395757150749714812010226235242652530451","seed":4899039531674917731436685899536663953395757150749714812010226235242652530451,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/6.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/6.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=694318867 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_error.694318867' seed=4899039531674917731436685899536663953395757150749714812010226235242652530451 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=4899039531674917731436685899536663953395757150749714812010226235242652530451 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/6.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"6.xbar_stress_all_with_reset_error.22613259723738605094335070566251815886776008194316937698422034456055654753446","seed":22613259723738605094335070566251815886776008194316937698422034456055654753446,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/6.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/6.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3049366694 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_reset_error.3049366694' seed=22613259723738605094335070566251815886776008194316937698422034456055654753446 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=22613259723738605094335070566251815886776008194316937698422034456055654753446 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/6.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke","qual_name":"7.xbar_smoke.106206352220334181437037386618054132796108309239845662341188946225487163917476","seed":106206352220334181437037386618054132796108309239845662341188946225487163917476,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/7.xbar_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/7.xbar_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2388886692 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke.2388886692' seed=106206352220334181437037386618054132796108309239845662341188946225487163917476 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=106206352220334181437037386618054132796108309239845662341188946225487163917476 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/7.xbar_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_zero_delays","qual_name":"7.xbar_smoke_zero_delays.89983604247236893682580249685741629232304466115510799527498197161174571601067","seed":89983604247236893682580249685741629232304466115510799527498197161174571601067,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/7.xbar_smoke_zero_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/7.xbar_smoke_zero_delays/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2294205611 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_zero_delays.2294205611' seed=89983604247236893682580249685741629232304466115510799527498197161174571601067 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=89983604247236893682580249685741629232304466115510799527498197161174571601067 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/7.xbar_smoke_zero_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_large_delays","qual_name":"7.xbar_smoke_large_delays.35754065727083538639430358247781782917459785641198399760072830627861991193234","seed":35754065727083538639430358247781782917459785641198399760072830627861991193234,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/7.xbar_smoke_large_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/7.xbar_smoke_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1554446994 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_large_delays.1554446994' seed=35754065727083538639430358247781782917459785641198399760072830627861991193234 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=35754065727083538639430358247781782917459785641198399760072830627861991193234 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/7.xbar_smoke_large_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_slow_rsp","qual_name":"7.xbar_smoke_slow_rsp.5462827424269731806620030944749739199244589652095808977828557543694803350369","seed":5462827424269731806620030944749739199244589652095808977828557543694803350369,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/7.xbar_smoke_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/7.xbar_smoke_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2610115425 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_slow_rsp.2610115425' seed=5462827424269731806620030944749739199244589652095808977828557543694803350369 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=5462827424269731806620030944749739199244589652095808977828557543694803350369 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/7.xbar_smoke_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random","qual_name":"7.xbar_random.20483729489762562489288061789927999437365979603151467819695352012972767825305","seed":20483729489762562489288061789927999437365979603151467819695352012972767825305,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/7.xbar_random/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/7.xbar_random/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4219719065 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random.4219719065' seed=20483729489762562489288061789927999437365979603151467819695352012972767825305 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=20483729489762562489288061789927999437365979603151467819695352012972767825305 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/7.xbar_random/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_zero_delays","qual_name":"7.xbar_random_zero_delays.18988911910822563002164125175508716037573069628286718697027693601431633351399","seed":18988911910822563002164125175508716037573069628286718697027693601431633351399,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/7.xbar_random_zero_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/7.xbar_random_zero_delays/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1264669415 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_zero_delays.1264669415' seed=18988911910822563002164125175508716037573069628286718697027693601431633351399 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=18988911910822563002164125175508716037573069628286718697027693601431633351399 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/7.xbar_random_zero_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_large_delays","qual_name":"7.xbar_random_large_delays.65164094392869397496720754520476219538058971267507193335687306796393544427093","seed":65164094392869397496720754520476219538058971267507193335687306796393544427093,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/7.xbar_random_large_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/7.xbar_random_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3914475093 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_large_delays.3914475093' seed=65164094392869397496720754520476219538058971267507193335687306796393544427093 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=65164094392869397496720754520476219538058971267507193335687306796393544427093 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/7.xbar_random_large_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_slow_rsp","qual_name":"7.xbar_random_slow_rsp.29705493221310109260893886972459867061576061202727817158464797510796322823161","seed":29705493221310109260893886972459867061576061202727817158464797510796322823161,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/7.xbar_random_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/7.xbar_random_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4233911289 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_slow_rsp.4233911289' seed=29705493221310109260893886972459867061576061202727817158464797510796322823161 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=29705493221310109260893886972459867061576061202727817158464797510796322823161 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/7.xbar_random_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device","qual_name":"7.xbar_access_same_device.90207965937726639289890590815988079082903719893820746366858616437960993415419","seed":90207965937726639289890590815988079082903719893820746366858616437960993415419,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/7.xbar_access_same_device/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/7.xbar_access_same_device/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=318513403 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device.318513403' seed=90207965937726639289890590815988079082903719893820746366858616437960993415419 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=90207965937726639289890590815988079082903719893820746366858616437960993415419 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/7.xbar_access_same_device/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"7.xbar_access_same_device_slow_rsp.73598185723550587030891623805482187722630446544145660866899780740632450731461","seed":73598185723550587030891623805482187722630446544145660866899780740632450731461,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/7.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/7.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1683787205 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device_slow_rsp.1683787205' seed=73598185723550587030891623805482187722630446544145660866899780740632450731461 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=73598185723550587030891623805482187722630446544145660866899780740632450731461 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/7.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_same_source","qual_name":"7.xbar_same_source.81120218185791110380908437793723064298994586205617321042774046645612708936539","seed":81120218185791110380908437793723064298994586205617321042774046645612708936539,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/7.xbar_same_source/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/7.xbar_same_source/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4017142619 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_same_source.4017142619' seed=81120218185791110380908437793723064298994586205617321042774046645612708936539 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=81120218185791110380908437793723064298994586205617321042774046645612708936539 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/7.xbar_same_source/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_same_source_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_random","qual_name":"7.xbar_error_random.62856596271885986621656501367157500603300641876776282030948624515744387770976","seed":62856596271885986621656501367157500603300641876776282030948624515744387770976,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/7.xbar_error_random/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/7.xbar_error_random/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1273965152 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_error_random.1273965152' seed=62856596271885986621656501367157500603300641876776282030948624515744387770976 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=62856596271885986621656501367157500603300641876776282030948624515744387770976 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/7.xbar_error_random/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_unmapped_addr","qual_name":"7.xbar_unmapped_addr.75665233362779892953154200774546891343877027756344756710416164381741192336932","seed":75665233362779892953154200774546891343877027756344756710416164381741192336932,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/7.xbar_unmapped_addr/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/7.xbar_unmapped_addr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1100240420 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_unmapped_addr.1100240420' seed=75665233362779892953154200774546891343877027756344756710416164381741192336932 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=75665233362779892953154200774546891343877027756344756710416164381741192336932 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/7.xbar_unmapped_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_and_unmapped_addr","qual_name":"7.xbar_error_and_unmapped_addr.99754056110336771799880347522675064999938009303285097714008771123796800018459","seed":99754056110336771799880347522675064999938009303285097714008771123796800018459,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/7.xbar_error_and_unmapped_addr/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/7.xbar_error_and_unmapped_addr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=545101851 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_error_and_unmapped_addr.545101851' seed=99754056110336771799880347522675064999938009303285097714008771123796800018459 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=99754056110336771799880347522675064999938009303285097714008771123796800018459 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/7.xbar_error_and_unmapped_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all","qual_name":"7.xbar_stress_all.82464615085966801373013278943653674641023947416786963860714911639453228045579","seed":82464615085966801373013278943653674641023947416786963860714911639453228045579,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/7.xbar_stress_all/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/7.xbar_stress_all/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1582011659 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all.1582011659' seed=82464615085966801373013278943653674641023947416786963860714911639453228045579 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=82464615085966801373013278943653674641023947416786963860714911639453228045579 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/7.xbar_stress_all/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_rand_reset","qual_name":"7.xbar_stress_all_with_rand_reset.114370162209820081925914240541231439438602314294011087429361988957972745239884","seed":114370162209820081925914240541231439438602314294011087429361988957972745239884,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/7.xbar_stress_all_with_rand_reset/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/7.xbar_stress_all_with_rand_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2758360396 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_rand_reset.2758360396' seed=114370162209820081925914240541231439438602314294011087429361988957972745239884 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=114370162209820081925914240541231439438602314294011087429361988957972745239884 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/7.xbar_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"7.xbar_stress_all_with_error.33342634276575442147476882628255009202183507137101612332852401155581574731326","seed":33342634276575442147476882628255009202183507137101612332852401155581574731326,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/7.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/7.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3216856638 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_error.3216856638' seed=33342634276575442147476882628255009202183507137101612332852401155581574731326 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=33342634276575442147476882628255009202183507137101612332852401155581574731326 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/7.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"7.xbar_stress_all_with_reset_error.20892571146890174738622245885568500051505267038788955025789530141533241366066","seed":20892571146890174738622245885568500051505267038788955025789530141533241366066,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/7.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/7.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1230788146 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_reset_error.1230788146' seed=20892571146890174738622245885568500051505267038788955025789530141533241366066 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=20892571146890174738622245885568500051505267038788955025789530141533241366066 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/7.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke","qual_name":"8.xbar_smoke.103412128157802919586569120678097562992638823641552280903892640532190258959702","seed":103412128157802919586569120678097562992638823641552280903892640532190258959702,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/8.xbar_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/8.xbar_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1114019158 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke.1114019158' seed=103412128157802919586569120678097562992638823641552280903892640532190258959702 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=103412128157802919586569120678097562992638823641552280903892640532190258959702 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/8.xbar_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_zero_delays","qual_name":"8.xbar_smoke_zero_delays.48778891255542861753280655371801090515109860267285612035066261923013118714763","seed":48778891255542861753280655371801090515109860267285612035066261923013118714763,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/8.xbar_smoke_zero_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/8.xbar_smoke_zero_delays/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1058595723 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_zero_delays.1058595723' seed=48778891255542861753280655371801090515109860267285612035066261923013118714763 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=48778891255542861753280655371801090515109860267285612035066261923013118714763 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/8.xbar_smoke_zero_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_large_delays","qual_name":"8.xbar_smoke_large_delays.52641071760244843604594078819522325609614921238944973777494233817866503297522","seed":52641071760244843604594078819522325609614921238944973777494233817866503297522,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/8.xbar_smoke_large_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/8.xbar_smoke_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4272527858 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_large_delays.4272527858' seed=52641071760244843604594078819522325609614921238944973777494233817866503297522 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=52641071760244843604594078819522325609614921238944973777494233817866503297522 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/8.xbar_smoke_large_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_slow_rsp","qual_name":"8.xbar_smoke_slow_rsp.51592764976088532738886040816449323477034572483090318398388778534182074345564","seed":51592764976088532738886040816449323477034572483090318398388778534182074345564,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/8.xbar_smoke_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/8.xbar_smoke_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3596249180 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_slow_rsp.3596249180' seed=51592764976088532738886040816449323477034572483090318398388778534182074345564 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=51592764976088532738886040816449323477034572483090318398388778534182074345564 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/8.xbar_smoke_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random","qual_name":"8.xbar_random.9752799959824634816774360260540609800006729628617779998110420886515271834562","seed":9752799959824634816774360260540609800006729628617779998110420886515271834562,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/8.xbar_random/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/8.xbar_random/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=624925634 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random.624925634' seed=9752799959824634816774360260540609800006729628617779998110420886515271834562 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=9752799959824634816774360260540609800006729628617779998110420886515271834562 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/8.xbar_random/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_zero_delays","qual_name":"8.xbar_random_zero_delays.2904676457622123002385525783128159799517232782454541035010392416899659895368","seed":2904676457622123002385525783128159799517232782454541035010392416899659895368,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/8.xbar_random_zero_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/8.xbar_random_zero_delays/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2061406792 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_zero_delays.2061406792' seed=2904676457622123002385525783128159799517232782454541035010392416899659895368 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=2904676457622123002385525783128159799517232782454541035010392416899659895368 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/8.xbar_random_zero_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_large_delays","qual_name":"8.xbar_random_large_delays.92871739526885970901146570778021864322346760970848258347909195585129721726757","seed":92871739526885970901146570778021864322346760970848258347909195585129721726757,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/8.xbar_random_large_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/8.xbar_random_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=123569957 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_large_delays.123569957' seed=92871739526885970901146570778021864322346760970848258347909195585129721726757 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=92871739526885970901146570778021864322346760970848258347909195585129721726757 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/8.xbar_random_large_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_slow_rsp","qual_name":"8.xbar_random_slow_rsp.41941763132490311669611694954714708158838420883919353328527343230066716546656","seed":41941763132490311669611694954714708158838420883919353328527343230066716546656,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/8.xbar_random_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/8.xbar_random_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3350959712 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_slow_rsp.3350959712' seed=41941763132490311669611694954714708158838420883919353328527343230066716546656 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=41941763132490311669611694954714708158838420883919353328527343230066716546656 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/8.xbar_random_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device","qual_name":"8.xbar_access_same_device.81657420885580651464493741051927982181102330584226746230114124494709043330325","seed":81657420885580651464493741051927982181102330584226746230114124494709043330325,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/8.xbar_access_same_device/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/8.xbar_access_same_device/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3308879125 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device.3308879125' seed=81657420885580651464493741051927982181102330584226746230114124494709043330325 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=81657420885580651464493741051927982181102330584226746230114124494709043330325 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/8.xbar_access_same_device/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"8.xbar_access_same_device_slow_rsp.107779681593369876550077886850507527352462473876679450428363127520653452247410","seed":107779681593369876550077886850507527352462473876679450428363127520653452247410,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/8.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/8.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3134718322 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device_slow_rsp.3134718322' seed=107779681593369876550077886850507527352462473876679450428363127520653452247410 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=107779681593369876550077886850507527352462473876679450428363127520653452247410 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/8.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_same_source","qual_name":"8.xbar_same_source.29869789555506292459295873998609492200681223515845358912881786454603540588394","seed":29869789555506292459295873998609492200681223515845358912881786454603540588394,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/8.xbar_same_source/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/8.xbar_same_source/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1663428458 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_same_source.1663428458' seed=29869789555506292459295873998609492200681223515845358912881786454603540588394 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=29869789555506292459295873998609492200681223515845358912881786454603540588394 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/8.xbar_same_source/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_same_source_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_random","qual_name":"8.xbar_error_random.9285817663231217023597429881677987053277415432672719366955543533503609865984","seed":9285817663231217023597429881677987053277415432672719366955543533503609865984,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/8.xbar_error_random/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/8.xbar_error_random/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1744602880 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_error_random.1744602880' seed=9285817663231217023597429881677987053277415432672719366955543533503609865984 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=9285817663231217023597429881677987053277415432672719366955543533503609865984 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/8.xbar_error_random/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_unmapped_addr","qual_name":"8.xbar_unmapped_addr.54553334118992380144438686033294077403148227886833314679985054786588218416283","seed":54553334118992380144438686033294077403148227886833314679985054786588218416283,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/8.xbar_unmapped_addr/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/8.xbar_unmapped_addr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=89840795 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_unmapped_addr.89840795' seed=54553334118992380144438686033294077403148227886833314679985054786588218416283 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=54553334118992380144438686033294077403148227886833314679985054786588218416283 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/8.xbar_unmapped_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_and_unmapped_addr","qual_name":"8.xbar_error_and_unmapped_addr.76104590555516697149234212574581408963641673289773278279285563146402550462045","seed":76104590555516697149234212574581408963641673289773278279285563146402550462045,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/8.xbar_error_and_unmapped_addr/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/8.xbar_error_and_unmapped_addr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4181931613 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_error_and_unmapped_addr.4181931613' seed=76104590555516697149234212574581408963641673289773278279285563146402550462045 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=76104590555516697149234212574581408963641673289773278279285563146402550462045 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/8.xbar_error_and_unmapped_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all","qual_name":"8.xbar_stress_all.78822706365913704167144931426170328629621423941888775560227893298297980059458","seed":78822706365913704167144931426170328629621423941888775560227893298297980059458,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/8.xbar_stress_all/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/8.xbar_stress_all/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2218524482 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all.2218524482' seed=78822706365913704167144931426170328629621423941888775560227893298297980059458 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=78822706365913704167144931426170328629621423941888775560227893298297980059458 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/8.xbar_stress_all/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_rand_reset","qual_name":"8.xbar_stress_all_with_rand_reset.44993310919516204410691645014905883732349253030181360563780380874416867266068","seed":44993310919516204410691645014905883732349253030181360563780380874416867266068,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/8.xbar_stress_all_with_rand_reset/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/8.xbar_stress_all_with_rand_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=804802068 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_rand_reset.804802068' seed=44993310919516204410691645014905883732349253030181360563780380874416867266068 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=44993310919516204410691645014905883732349253030181360563780380874416867266068 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/8.xbar_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"8.xbar_stress_all_with_error.75914531003638321687708727318667299533429852240709927685820948342078715741781","seed":75914531003638321687708727318667299533429852240709927685820948342078715741781,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/8.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/8.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4242032213 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_error.4242032213' seed=75914531003638321687708727318667299533429852240709927685820948342078715741781 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=75914531003638321687708727318667299533429852240709927685820948342078715741781 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/8.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"8.xbar_stress_all_with_reset_error.17197072189661316277980372518308685302278582227892121522758773446239151850805","seed":17197072189661316277980372518308685302278582227892121522758773446239151850805,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/8.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/8.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2128217397 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_reset_error.2128217397' seed=17197072189661316277980372518308685302278582227892121522758773446239151850805 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=17197072189661316277980372518308685302278582227892121522758773446239151850805 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/8.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke","qual_name":"9.xbar_smoke.105293666879009344332895341585956289511168631951407347199675881212735760348553","seed":105293666879009344332895341585956289511168631951407347199675881212735760348553,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/9.xbar_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/9.xbar_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3029841289 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke.3029841289' seed=105293666879009344332895341585956289511168631951407347199675881212735760348553 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=105293666879009344332895341585956289511168631951407347199675881212735760348553 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/9.xbar_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_zero_delays","qual_name":"9.xbar_smoke_zero_delays.51863082564042273829390161262029060106713858593018521030541418849090767785507","seed":51863082564042273829390161262029060106713858593018521030541418849090767785507,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/9.xbar_smoke_zero_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/9.xbar_smoke_zero_delays/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1942588963 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_zero_delays.1942588963' seed=51863082564042273829390161262029060106713858593018521030541418849090767785507 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=51863082564042273829390161262029060106713858593018521030541418849090767785507 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/9.xbar_smoke_zero_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_large_delays","qual_name":"9.xbar_smoke_large_delays.85763045565589447542190506607833037754327118358574889458307194748025061099202","seed":85763045565589447542190506607833037754327118358574889458307194748025061099202,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/9.xbar_smoke_large_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/9.xbar_smoke_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3601188546 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_large_delays.3601188546' seed=85763045565589447542190506607833037754327118358574889458307194748025061099202 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=85763045565589447542190506607833037754327118358574889458307194748025061099202 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/9.xbar_smoke_large_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_slow_rsp","qual_name":"9.xbar_smoke_slow_rsp.32669631491753426458824936482146539599814711049716001353338198777819187053307","seed":32669631491753426458824936482146539599814711049716001353338198777819187053307,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/9.xbar_smoke_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/9.xbar_smoke_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1401357051 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_slow_rsp.1401357051' seed=32669631491753426458824936482146539599814711049716001353338198777819187053307 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=32669631491753426458824936482146539599814711049716001353338198777819187053307 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/9.xbar_smoke_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random","qual_name":"9.xbar_random.83617902396031008526447546700144501181665738049020701932557175561288474056587","seed":83617902396031008526447546700144501181665738049020701932557175561288474056587,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/9.xbar_random/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/9.xbar_random/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3152172939 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random.3152172939' seed=83617902396031008526447546700144501181665738049020701932557175561288474056587 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=83617902396031008526447546700144501181665738049020701932557175561288474056587 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/9.xbar_random/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_zero_delays","qual_name":"9.xbar_random_zero_delays.44588824172215648139094396911413157258633111567002763489211608726570711159112","seed":44588824172215648139094396911413157258633111567002763489211608726570711159112,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/9.xbar_random_zero_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/9.xbar_random_zero_delays/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3869282632 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_zero_delays.3869282632' seed=44588824172215648139094396911413157258633111567002763489211608726570711159112 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=44588824172215648139094396911413157258633111567002763489211608726570711159112 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/9.xbar_random_zero_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_large_delays","qual_name":"9.xbar_random_large_delays.1316498869952920137706797197326002020568015991082931714719559059648617755507","seed":1316498869952920137706797197326002020568015991082931714719559059648617755507,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/9.xbar_random_large_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/9.xbar_random_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1933161331 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_large_delays.1933161331' seed=1316498869952920137706797197326002020568015991082931714719559059648617755507 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=1316498869952920137706797197326002020568015991082931714719559059648617755507 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/9.xbar_random_large_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_slow_rsp","qual_name":"9.xbar_random_slow_rsp.89362206103961384367921308380049943309493884863138880522182130384139105732932","seed":89362206103961384367921308380049943309493884863138880522182130384139105732932,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/9.xbar_random_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/9.xbar_random_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=991299908 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_slow_rsp.991299908' seed=89362206103961384367921308380049943309493884863138880522182130384139105732932 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=89362206103961384367921308380049943309493884863138880522182130384139105732932 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/9.xbar_random_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device","qual_name":"9.xbar_access_same_device.64209309870805772624408158728859083817085176517868879129201649136959996366632","seed":64209309870805772624408158728859083817085176517868879129201649136959996366632,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/9.xbar_access_same_device/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/9.xbar_access_same_device/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2186088232 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device.2186088232' seed=64209309870805772624408158728859083817085176517868879129201649136959996366632 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=64209309870805772624408158728859083817085176517868879129201649136959996366632 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/9.xbar_access_same_device/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"9.xbar_access_same_device_slow_rsp.11108123967960226795212422438271472804950399212282034185221146535865596379487","seed":11108123967960226795212422438271472804950399212282034185221146535865596379487,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/9.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/9.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1018036575 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device_slow_rsp.1018036575' seed=11108123967960226795212422438271472804950399212282034185221146535865596379487 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=11108123967960226795212422438271472804950399212282034185221146535865596379487 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/9.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_same_source","qual_name":"9.xbar_same_source.30767687464051867448371081748043252684351443934764391955135322806598274865705","seed":30767687464051867448371081748043252684351443934764391955135322806598274865705,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/9.xbar_same_source/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/9.xbar_same_source/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2565823017 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_same_source.2565823017' seed=30767687464051867448371081748043252684351443934764391955135322806598274865705 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=30767687464051867448371081748043252684351443934764391955135322806598274865705 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/9.xbar_same_source/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_same_source_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_random","qual_name":"9.xbar_error_random.50321155245323307331332813535551364362744362329272124372462587647667629877087","seed":50321155245323307331332813535551364362744362329272124372462587647667629877087,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/9.xbar_error_random/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/9.xbar_error_random/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=86140767 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_error_random.86140767' seed=50321155245323307331332813535551364362744362329272124372462587647667629877087 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=50321155245323307331332813535551364362744362329272124372462587647667629877087 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/9.xbar_error_random/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_unmapped_addr","qual_name":"9.xbar_unmapped_addr.87654683809334848040397332698323699574328996320786228282453262521576743250042","seed":87654683809334848040397332698323699574328996320786228282453262521576743250042,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/9.xbar_unmapped_addr/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/9.xbar_unmapped_addr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3554420858 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_unmapped_addr.3554420858' seed=87654683809334848040397332698323699574328996320786228282453262521576743250042 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=87654683809334848040397332698323699574328996320786228282453262521576743250042 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/9.xbar_unmapped_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_and_unmapped_addr","qual_name":"9.xbar_error_and_unmapped_addr.6054511211090556349605719294254622045914503951059306836622445172878877295306","seed":6054511211090556349605719294254622045914503951059306836622445172878877295306,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/9.xbar_error_and_unmapped_addr/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/9.xbar_error_and_unmapped_addr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1318486730 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_error_and_unmapped_addr.1318486730' seed=6054511211090556349605719294254622045914503951059306836622445172878877295306 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=6054511211090556349605719294254622045914503951059306836622445172878877295306 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/9.xbar_error_and_unmapped_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all","qual_name":"9.xbar_stress_all.104332469520826258576979643429804349790920680806075983500876506885213767237488","seed":104332469520826258576979643429804349790920680806075983500876506885213767237488,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/9.xbar_stress_all/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/9.xbar_stress_all/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3727589232 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all.3727589232' seed=104332469520826258576979643429804349790920680806075983500876506885213767237488 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=104332469520826258576979643429804349790920680806075983500876506885213767237488 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/9.xbar_stress_all/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_rand_reset","qual_name":"9.xbar_stress_all_with_rand_reset.2035672464995828991327521760457399268241706922543743817445253171766478372751","seed":2035672464995828991327521760457399268241706922543743817445253171766478372751,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/9.xbar_stress_all_with_rand_reset/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/9.xbar_stress_all_with_rand_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2894987151 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_rand_reset.2894987151' seed=2035672464995828991327521760457399268241706922543743817445253171766478372751 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=2035672464995828991327521760457399268241706922543743817445253171766478372751 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/9.xbar_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"9.xbar_stress_all_with_error.74968297512615398315160191912650883439377240948018352627273534314603875410831","seed":74968297512615398315160191912650883439377240948018352627273534314603875410831,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/9.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/9.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2513445775 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_error.2513445775' seed=74968297512615398315160191912650883439377240948018352627273534314603875410831 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=74968297512615398315160191912650883439377240948018352627273534314603875410831 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/9.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"9.xbar_stress_all_with_reset_error.89723134971236204624061060210072507064119847751561664796029245490680342910181","seed":89723134971236204624061060210072507064119847751561664796029245490680342910181,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/9.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/9.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=223745253 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_reset_error.223745253' seed=89723134971236204624061060210072507064119847751561664796029245490680342910181 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=89723134971236204624061060210072507064119847751561664796029245490680342910181 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/9.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke","qual_name":"10.xbar_smoke.34511322789074136026865330384061691755485267847130778741104379488912617999948","seed":34511322789074136026865330384061691755485267847130778741104379488912617999948,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/10.xbar_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/10.xbar_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=143363660 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke.143363660' seed=34511322789074136026865330384061691755485267847130778741104379488912617999948 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=34511322789074136026865330384061691755485267847130778741104379488912617999948 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/10.xbar_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_zero_delays","qual_name":"10.xbar_smoke_zero_delays.92136560560254492717672664901964168543137793839605344808658687801130692399420","seed":92136560560254492717672664901964168543137793839605344808658687801130692399420,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/10.xbar_smoke_zero_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/10.xbar_smoke_zero_delays/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1058033980 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_zero_delays.1058033980' seed=92136560560254492717672664901964168543137793839605344808658687801130692399420 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=92136560560254492717672664901964168543137793839605344808658687801130692399420 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/10.xbar_smoke_zero_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_large_delays","qual_name":"10.xbar_smoke_large_delays.30027569388294001188255591939138492717852941513528489353195564198826713729269","seed":30027569388294001188255591939138492717852941513528489353195564198826713729269,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/10.xbar_smoke_large_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/10.xbar_smoke_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3183659253 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_large_delays.3183659253' seed=30027569388294001188255591939138492717852941513528489353195564198826713729269 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=30027569388294001188255591939138492717852941513528489353195564198826713729269 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/10.xbar_smoke_large_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_slow_rsp","qual_name":"10.xbar_smoke_slow_rsp.93057769454824842407534039303300802442228136000356275077012359262435853174648","seed":93057769454824842407534039303300802442228136000356275077012359262435853174648,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/10.xbar_smoke_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/10.xbar_smoke_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2415626104 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_slow_rsp.2415626104' seed=93057769454824842407534039303300802442228136000356275077012359262435853174648 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=93057769454824842407534039303300802442228136000356275077012359262435853174648 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/10.xbar_smoke_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random","qual_name":"10.xbar_random.86941734994715044875200427941005921074929932274050102699275644850210319806063","seed":86941734994715044875200427941005921074929932274050102699275644850210319806063,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/10.xbar_random/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/10.xbar_random/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=750693999 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random.750693999' seed=86941734994715044875200427941005921074929932274050102699275644850210319806063 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=86941734994715044875200427941005921074929932274050102699275644850210319806063 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/10.xbar_random/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_zero_delays","qual_name":"10.xbar_random_zero_delays.94179340051295849247363999250262002419772847702374595000279051228199821482172","seed":94179340051295849247363999250262002419772847702374595000279051228199821482172,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/10.xbar_random_zero_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/10.xbar_random_zero_delays/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3453196476 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_zero_delays.3453196476' seed=94179340051295849247363999250262002419772847702374595000279051228199821482172 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=94179340051295849247363999250262002419772847702374595000279051228199821482172 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/10.xbar_random_zero_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_large_delays","qual_name":"10.xbar_random_large_delays.77087581230922782887815153424299383486878212658650165545548162636685438219738","seed":77087581230922782887815153424299383486878212658650165545548162636685438219738,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/10.xbar_random_large_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/10.xbar_random_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3232626138 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_large_delays.3232626138' seed=77087581230922782887815153424299383486878212658650165545548162636685438219738 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=77087581230922782887815153424299383486878212658650165545548162636685438219738 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/10.xbar_random_large_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_slow_rsp","qual_name":"10.xbar_random_slow_rsp.23766972519552395812703954831915703853351948539037233470672475564860003409259","seed":23766972519552395812703954831915703853351948539037233470672475564860003409259,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/10.xbar_random_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/10.xbar_random_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1701404011 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_slow_rsp.1701404011' seed=23766972519552395812703954831915703853351948539037233470672475564860003409259 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=23766972519552395812703954831915703853351948539037233470672475564860003409259 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/10.xbar_random_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device","qual_name":"10.xbar_access_same_device.91172259534978409039939792189256091676553301660331578687595823925430630275801","seed":91172259534978409039939792189256091676553301660331578687595823925430630275801,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/10.xbar_access_same_device/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/10.xbar_access_same_device/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1290590937 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device.1290590937' seed=91172259534978409039939792189256091676553301660331578687595823925430630275801 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=91172259534978409039939792189256091676553301660331578687595823925430630275801 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/10.xbar_access_same_device/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"10.xbar_access_same_device_slow_rsp.10034613380829408496435638561547547235894438778036962566695369047341483614017","seed":10034613380829408496435638561547547235894438778036962566695369047341483614017,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/10.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/10.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3601522497 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device_slow_rsp.3601522497' seed=10034613380829408496435638561547547235894438778036962566695369047341483614017 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=10034613380829408496435638561547547235894438778036962566695369047341483614017 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/10.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_same_source","qual_name":"10.xbar_same_source.51561694806976486573906263981019765089903769298649732916660029907481593186590","seed":51561694806976486573906263981019765089903769298649732916660029907481593186590,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/10.xbar_same_source/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/10.xbar_same_source/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1456277790 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_same_source.1456277790' seed=51561694806976486573906263981019765089903769298649732916660029907481593186590 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=51561694806976486573906263981019765089903769298649732916660029907481593186590 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/10.xbar_same_source/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_same_source_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_random","qual_name":"10.xbar_error_random.54525641403077072682775682197304385573539844573746195271490535069580446895042","seed":54525641403077072682775682197304385573539844573746195271490535069580446895042,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/10.xbar_error_random/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/10.xbar_error_random/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3564080066 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_error_random.3564080066' seed=54525641403077072682775682197304385573539844573746195271490535069580446895042 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=54525641403077072682775682197304385573539844573746195271490535069580446895042 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/10.xbar_error_random/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_unmapped_addr","qual_name":"10.xbar_unmapped_addr.60008727170130779562973117185786081716595995612601778926827283493076007170231","seed":60008727170130779562973117185786081716595995612601778926827283493076007170231,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/10.xbar_unmapped_addr/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/10.xbar_unmapped_addr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1417457847 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_unmapped_addr.1417457847' seed=60008727170130779562973117185786081716595995612601778926827283493076007170231 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=60008727170130779562973117185786081716595995612601778926827283493076007170231 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/10.xbar_unmapped_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_and_unmapped_addr","qual_name":"10.xbar_error_and_unmapped_addr.47037674043590009012978138538139781942686447986503751418586577622478262447329","seed":47037674043590009012978138538139781942686447986503751418586577622478262447329,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/10.xbar_error_and_unmapped_addr/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/10.xbar_error_and_unmapped_addr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3125095649 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_error_and_unmapped_addr.3125095649' seed=47037674043590009012978138538139781942686447986503751418586577622478262447329 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=47037674043590009012978138538139781942686447986503751418586577622478262447329 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/10.xbar_error_and_unmapped_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all","qual_name":"10.xbar_stress_all.100066459399469958642255617811798054270825904771099245991111361893087647735661","seed":100066459399469958642255617811798054270825904771099245991111361893087647735661,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/10.xbar_stress_all/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/10.xbar_stress_all/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1990565741 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all.1990565741' seed=100066459399469958642255617811798054270825904771099245991111361893087647735661 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=100066459399469958642255617811798054270825904771099245991111361893087647735661 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/10.xbar_stress_all/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_rand_reset","qual_name":"10.xbar_stress_all_with_rand_reset.67642996483217905067986219566154750607783329200841693373165189517905289949451","seed":67642996483217905067986219566154750607783329200841693373165189517905289949451,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/10.xbar_stress_all_with_rand_reset/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/10.xbar_stress_all_with_rand_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=519450891 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_rand_reset.519450891' seed=67642996483217905067986219566154750607783329200841693373165189517905289949451 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=67642996483217905067986219566154750607783329200841693373165189517905289949451 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/10.xbar_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"10.xbar_stress_all_with_error.89116792860782256837616615532808086685063418331343407411094986018981331127237","seed":89116792860782256837616615532808086685063418331343407411094986018981331127237,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/10.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/10.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2225130437 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_error.2225130437' seed=89116792860782256837616615532808086685063418331343407411094986018981331127237 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=89116792860782256837616615532808086685063418331343407411094986018981331127237 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/10.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"10.xbar_stress_all_with_reset_error.83062475370368074697482885218739156736180180793339402599852595794219938877135","seed":83062475370368074697482885218739156736180180793339402599852595794219938877135,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/10.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/10.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=31461071 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_reset_error.31461071' seed=83062475370368074697482885218739156736180180793339402599852595794219938877135 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=83062475370368074697482885218739156736180180793339402599852595794219938877135 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/10.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke","qual_name":"11.xbar_smoke.75613495751022827856153099100089264731205908235496400589149154920531965282321","seed":75613495751022827856153099100089264731205908235496400589149154920531965282321,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/11.xbar_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/11.xbar_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2676525073 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke.2676525073' seed=75613495751022827856153099100089264731205908235496400589149154920531965282321 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=75613495751022827856153099100089264731205908235496400589149154920531965282321 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/11.xbar_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_zero_delays","qual_name":"11.xbar_smoke_zero_delays.111940489095169573518506818050030421956262810737709678473285948945616100364168","seed":111940489095169573518506818050030421956262810737709678473285948945616100364168,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/11.xbar_smoke_zero_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/11.xbar_smoke_zero_delays/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1959235464 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_zero_delays.1959235464' seed=111940489095169573518506818050030421956262810737709678473285948945616100364168 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=111940489095169573518506818050030421956262810737709678473285948945616100364168 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/11.xbar_smoke_zero_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_large_delays","qual_name":"11.xbar_smoke_large_delays.1474622209648783204436967837399885267572427675461668312008448338097114771694","seed":1474622209648783204436967837399885267572427675461668312008448338097114771694,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/11.xbar_smoke_large_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/11.xbar_smoke_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3958173934 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_large_delays.3958173934' seed=1474622209648783204436967837399885267572427675461668312008448338097114771694 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=1474622209648783204436967837399885267572427675461668312008448338097114771694 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/11.xbar_smoke_large_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_slow_rsp","qual_name":"11.xbar_smoke_slow_rsp.36243508222774545645790194659657749653241823057289528653664616211896395824318","seed":36243508222774545645790194659657749653241823057289528653664616211896395824318,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/11.xbar_smoke_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/11.xbar_smoke_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3096116414 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_slow_rsp.3096116414' seed=36243508222774545645790194659657749653241823057289528653664616211896395824318 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=36243508222774545645790194659657749653241823057289528653664616211896395824318 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/11.xbar_smoke_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random","qual_name":"11.xbar_random.48643223643200182395287163703532191847447953717518722835523544471833755981","seed":48643223643200182395287163703532191847447953717518722835523544471833755981,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/11.xbar_random/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/11.xbar_random/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=70336845 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random.70336845' seed=48643223643200182395287163703532191847447953717518722835523544471833755981 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=48643223643200182395287163703532191847447953717518722835523544471833755981 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/11.xbar_random/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_zero_delays","qual_name":"11.xbar_random_zero_delays.27888173684668109987034147460787669108907431005422241270536575959869125843342","seed":27888173684668109987034147460787669108907431005422241270536575959869125843342,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/11.xbar_random_zero_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/11.xbar_random_zero_delays/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2470467982 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_zero_delays.2470467982' seed=27888173684668109987034147460787669108907431005422241270536575959869125843342 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=27888173684668109987034147460787669108907431005422241270536575959869125843342 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/11.xbar_random_zero_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_large_delays","qual_name":"11.xbar_random_large_delays.66580222179348809132741853511125116863012788391198593010289823812285062680852","seed":66580222179348809132741853511125116863012788391198593010289823812285062680852,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/11.xbar_random_large_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/11.xbar_random_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1609011476 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_large_delays.1609011476' seed=66580222179348809132741853511125116863012788391198593010289823812285062680852 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=66580222179348809132741853511125116863012788391198593010289823812285062680852 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/11.xbar_random_large_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_slow_rsp","qual_name":"11.xbar_random_slow_rsp.43674736452658647344048933347515951701142352566734803292557476769329289116594","seed":43674736452658647344048933347515951701142352566734803292557476769329289116594,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/11.xbar_random_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/11.xbar_random_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2787654578 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_slow_rsp.2787654578' seed=43674736452658647344048933347515951701142352566734803292557476769329289116594 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=43674736452658647344048933347515951701142352566734803292557476769329289116594 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/11.xbar_random_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device","qual_name":"11.xbar_access_same_device.35883157626707324780277143861616899873850272549875428955260912235538029845967","seed":35883157626707324780277143861616899873850272549875428955260912235538029845967,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/11.xbar_access_same_device/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/11.xbar_access_same_device/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1613864399 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device.1613864399' seed=35883157626707324780277143861616899873850272549875428955260912235538029845967 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=35883157626707324780277143861616899873850272549875428955260912235538029845967 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/11.xbar_access_same_device/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"11.xbar_access_same_device_slow_rsp.7151511787989670353431556539061394853091620730371414890765457580455786976378","seed":7151511787989670353431556539061394853091620730371414890765457580455786976378,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/11.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/11.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1332483194 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device_slow_rsp.1332483194' seed=7151511787989670353431556539061394853091620730371414890765457580455786976378 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=7151511787989670353431556539061394853091620730371414890765457580455786976378 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/11.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_same_source","qual_name":"11.xbar_same_source.5460121764184663685600573631007715304413692218747391511509203801631920317068","seed":5460121764184663685600573631007715304413692218747391511509203801631920317068,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/11.xbar_same_source/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/11.xbar_same_source/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3044369036 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_same_source.3044369036' seed=5460121764184663685600573631007715304413692218747391511509203801631920317068 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=5460121764184663685600573631007715304413692218747391511509203801631920317068 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/11.xbar_same_source/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_same_source_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_random","qual_name":"11.xbar_error_random.87235071358186016068901904923310971490117874252300525708833747946556538007073","seed":87235071358186016068901904923310971490117874252300525708833747946556538007073,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/11.xbar_error_random/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/11.xbar_error_random/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2572201505 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_error_random.2572201505' seed=87235071358186016068901904923310971490117874252300525708833747946556538007073 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=87235071358186016068901904923310971490117874252300525708833747946556538007073 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/11.xbar_error_random/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_unmapped_addr","qual_name":"11.xbar_unmapped_addr.95240918360093840567746281712654678406470513006770867942884114132273279256887","seed":95240918360093840567746281712654678406470513006770867942884114132273279256887,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/11.xbar_unmapped_addr/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/11.xbar_unmapped_addr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1866975543 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_unmapped_addr.1866975543' seed=95240918360093840567746281712654678406470513006770867942884114132273279256887 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=95240918360093840567746281712654678406470513006770867942884114132273279256887 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/11.xbar_unmapped_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_and_unmapped_addr","qual_name":"11.xbar_error_and_unmapped_addr.2508696244271929538296274943120900135134862129553693968954844517030482297043","seed":2508696244271929538296274943120900135134862129553693968954844517030482297043,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/11.xbar_error_and_unmapped_addr/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/11.xbar_error_and_unmapped_addr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2639413459 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_error_and_unmapped_addr.2639413459' seed=2508696244271929538296274943120900135134862129553693968954844517030482297043 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=2508696244271929538296274943120900135134862129553693968954844517030482297043 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/11.xbar_error_and_unmapped_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all","qual_name":"11.xbar_stress_all.86567915127961429091219077186867380950645652872404025236285599483580955421317","seed":86567915127961429091219077186867380950645652872404025236285599483580955421317,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/11.xbar_stress_all/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/11.xbar_stress_all/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1918560901 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all.1918560901' seed=86567915127961429091219077186867380950645652872404025236285599483580955421317 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=86567915127961429091219077186867380950645652872404025236285599483580955421317 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/11.xbar_stress_all/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_rand_reset","qual_name":"11.xbar_stress_all_with_rand_reset.73178174844701344499691726109330117831559172755016897936130547776414379411161","seed":73178174844701344499691726109330117831559172755016897936130547776414379411161,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/11.xbar_stress_all_with_rand_reset/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/11.xbar_stress_all_with_rand_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2117338841 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_rand_reset.2117338841' seed=73178174844701344499691726109330117831559172755016897936130547776414379411161 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=73178174844701344499691726109330117831559172755016897936130547776414379411161 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/11.xbar_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"11.xbar_stress_all_with_error.75217437413625538168457651904948929439386360447453801203486981749266334534546","seed":75217437413625538168457651904948929439386360447453801203486981749266334534546,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/11.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/11.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4028025746 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_error.4028025746' seed=75217437413625538168457651904948929439386360447453801203486981749266334534546 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=75217437413625538168457651904948929439386360447453801203486981749266334534546 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/11.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"11.xbar_stress_all_with_reset_error.56355025453720724577888075088543244433068882914383521272231301570086067476145","seed":56355025453720724577888075088543244433068882914383521272231301570086067476145,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/11.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/11.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=355178161 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_reset_error.355178161' seed=56355025453720724577888075088543244433068882914383521272231301570086067476145 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=56355025453720724577888075088543244433068882914383521272231301570086067476145 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/11.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke","qual_name":"12.xbar_smoke.57739396194730145214240598830164477617986808496207137962189325953803300101180","seed":57739396194730145214240598830164477617986808496207137962189325953803300101180,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/12.xbar_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/12.xbar_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3187137596 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke.3187137596' seed=57739396194730145214240598830164477617986808496207137962189325953803300101180 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=57739396194730145214240598830164477617986808496207137962189325953803300101180 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/12.xbar_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_zero_delays","qual_name":"12.xbar_smoke_zero_delays.61826871127428012634073860391995447087689473489577224903250638216631217185207","seed":61826871127428012634073860391995447087689473489577224903250638216631217185207,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/12.xbar_smoke_zero_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/12.xbar_smoke_zero_delays/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3480904119 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_zero_delays.3480904119' seed=61826871127428012634073860391995447087689473489577224903250638216631217185207 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=61826871127428012634073860391995447087689473489577224903250638216631217185207 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/12.xbar_smoke_zero_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_large_delays","qual_name":"12.xbar_smoke_large_delays.59539704331628836417134185971500940573812690354193241043521848367498156053312","seed":59539704331628836417134185971500940573812690354193241043521848367498156053312,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/12.xbar_smoke_large_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/12.xbar_smoke_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2935493440 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_large_delays.2935493440' seed=59539704331628836417134185971500940573812690354193241043521848367498156053312 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=59539704331628836417134185971500940573812690354193241043521848367498156053312 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/12.xbar_smoke_large_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_slow_rsp","qual_name":"12.xbar_smoke_slow_rsp.81601898117501804475889267514032534632453235281108799864447603452694837584696","seed":81601898117501804475889267514032534632453235281108799864447603452694837584696,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/12.xbar_smoke_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/12.xbar_smoke_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2636636984 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_slow_rsp.2636636984' seed=81601898117501804475889267514032534632453235281108799864447603452694837584696 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=81601898117501804475889267514032534632453235281108799864447603452694837584696 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/12.xbar_smoke_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random","qual_name":"12.xbar_random.64125132591004704580431749798966967868791400017497360024551247392805286298061","seed":64125132591004704580431749798966967868791400017497360024551247392805286298061,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/12.xbar_random/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/12.xbar_random/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1313849805 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random.1313849805' seed=64125132591004704580431749798966967868791400017497360024551247392805286298061 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=64125132591004704580431749798966967868791400017497360024551247392805286298061 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/12.xbar_random/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_zero_delays","qual_name":"12.xbar_random_zero_delays.27082134410336260108444676783133921166647677473232911372289884244395949715816","seed":27082134410336260108444676783133921166647677473232911372289884244395949715816,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/12.xbar_random_zero_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/12.xbar_random_zero_delays/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3264901480 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_zero_delays.3264901480' seed=27082134410336260108444676783133921166647677473232911372289884244395949715816 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=27082134410336260108444676783133921166647677473232911372289884244395949715816 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/12.xbar_random_zero_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_large_delays","qual_name":"12.xbar_random_large_delays.75993398272029162076752451018157144711516224088625463529240024819964568666276","seed":75993398272029162076752451018157144711516224088625463529240024819964568666276,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/12.xbar_random_large_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/12.xbar_random_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3771990180 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_large_delays.3771990180' seed=75993398272029162076752451018157144711516224088625463529240024819964568666276 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=75993398272029162076752451018157144711516224088625463529240024819964568666276 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/12.xbar_random_large_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_slow_rsp","qual_name":"12.xbar_random_slow_rsp.48574791917670103325878193273547876116114484222572050919518939191769184110772","seed":48574791917670103325878193273547876116114484222572050919518939191769184110772,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/12.xbar_random_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/12.xbar_random_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1491634356 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_slow_rsp.1491634356' seed=48574791917670103325878193273547876116114484222572050919518939191769184110772 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=48574791917670103325878193273547876116114484222572050919518939191769184110772 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/12.xbar_random_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device","qual_name":"12.xbar_access_same_device.31104353667058223635656774899412189784357284762325744624102836667218040926533","seed":31104353667058223635656774899412189784357284762325744624102836667218040926533,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/12.xbar_access_same_device/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/12.xbar_access_same_device/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=778252613 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device.778252613' seed=31104353667058223635656774899412189784357284762325744624102836667218040926533 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=31104353667058223635656774899412189784357284762325744624102836667218040926533 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/12.xbar_access_same_device/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"12.xbar_access_same_device_slow_rsp.10489992591232277979136585431233244231520112003525053885134351633616436323205","seed":10489992591232277979136585431233244231520112003525053885134351633616436323205,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/12.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/12.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1497228165 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device_slow_rsp.1497228165' seed=10489992591232277979136585431233244231520112003525053885134351633616436323205 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=10489992591232277979136585431233244231520112003525053885134351633616436323205 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/12.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_same_source","qual_name":"12.xbar_same_source.22510683617281639660750600674684259215317394090794503970312301913589824732427","seed":22510683617281639660750600674684259215317394090794503970312301913589824732427,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/12.xbar_same_source/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/12.xbar_same_source/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1702739211 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_same_source.1702739211' seed=22510683617281639660750600674684259215317394090794503970312301913589824732427 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=22510683617281639660750600674684259215317394090794503970312301913589824732427 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/12.xbar_same_source/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_same_source_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_random","qual_name":"12.xbar_error_random.107023742196931910718901834985287830263208654325696882778238058688923686155837","seed":107023742196931910718901834985287830263208654325696882778238058688923686155837,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/12.xbar_error_random/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/12.xbar_error_random/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3284678205 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_error_random.3284678205' seed=107023742196931910718901834985287830263208654325696882778238058688923686155837 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=107023742196931910718901834985287830263208654325696882778238058688923686155837 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/12.xbar_error_random/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_unmapped_addr","qual_name":"12.xbar_unmapped_addr.70689462173729907345815893167672690166284014112883351306085930164894133187803","seed":70689462173729907345815893167672690166284014112883351306085930164894133187803,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/12.xbar_unmapped_addr/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/12.xbar_unmapped_addr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2815227099 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_unmapped_addr.2815227099' seed=70689462173729907345815893167672690166284014112883351306085930164894133187803 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=70689462173729907345815893167672690166284014112883351306085930164894133187803 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/12.xbar_unmapped_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_and_unmapped_addr","qual_name":"12.xbar_error_and_unmapped_addr.6387404933429062313058411166909066451225740931697619479736738202044361912798","seed":6387404933429062313058411166909066451225740931697619479736738202044361912798,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/12.xbar_error_and_unmapped_addr/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/12.xbar_error_and_unmapped_addr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2726867422 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_error_and_unmapped_addr.2726867422' seed=6387404933429062313058411166909066451225740931697619479736738202044361912798 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=6387404933429062313058411166909066451225740931697619479736738202044361912798 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/12.xbar_error_and_unmapped_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all","qual_name":"12.xbar_stress_all.108469565088247121260718448146148665187385559654103392667776354752645951381898","seed":108469565088247121260718448146148665187385559654103392667776354752645951381898,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/12.xbar_stress_all/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/12.xbar_stress_all/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3071271306 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all.3071271306' seed=108469565088247121260718448146148665187385559654103392667776354752645951381898 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=108469565088247121260718448146148665187385559654103392667776354752645951381898 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/12.xbar_stress_all/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_rand_reset","qual_name":"12.xbar_stress_all_with_rand_reset.25465915583740341126516776558291817521053904787341823950153432940110531137272","seed":25465915583740341126516776558291817521053904787341823950153432940110531137272,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/12.xbar_stress_all_with_rand_reset/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/12.xbar_stress_all_with_rand_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=683544312 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_rand_reset.683544312' seed=25465915583740341126516776558291817521053904787341823950153432940110531137272 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=25465915583740341126516776558291817521053904787341823950153432940110531137272 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/12.xbar_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"12.xbar_stress_all_with_error.21067413497900392687617573686580261785177452178267481462881482406734690831007","seed":21067413497900392687617573686580261785177452178267481462881482406734690831007,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/12.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/12.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1466223263 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_error.1466223263' seed=21067413497900392687617573686580261785177452178267481462881482406734690831007 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=21067413497900392687617573686580261785177452178267481462881482406734690831007 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/12.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"12.xbar_stress_all_with_reset_error.25528232632241197763953503304595564986722559990804894401935024625081180397752","seed":25528232632241197763953503304595564986722559990804894401935024625081180397752,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/12.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/12.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4113473720 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_reset_error.4113473720' seed=25528232632241197763953503304595564986722559990804894401935024625081180397752 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=25528232632241197763953503304595564986722559990804894401935024625081180397752 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/12.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke","qual_name":"13.xbar_smoke.77067098660198617151770682063626916721192796231480208792659218323823254617497","seed":77067098660198617151770682063626916721192796231480208792659218323823254617497,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/13.xbar_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/13.xbar_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2156182937 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke.2156182937' seed=77067098660198617151770682063626916721192796231480208792659218323823254617497 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=77067098660198617151770682063626916721192796231480208792659218323823254617497 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/13.xbar_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_zero_delays","qual_name":"13.xbar_smoke_zero_delays.62238150143424131819958059260545824352791305948875331970768563488619288149386","seed":62238150143424131819958059260545824352791305948875331970768563488619288149386,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/13.xbar_smoke_zero_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/13.xbar_smoke_zero_delays/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3303357834 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_zero_delays.3303357834' seed=62238150143424131819958059260545824352791305948875331970768563488619288149386 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=62238150143424131819958059260545824352791305948875331970768563488619288149386 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/13.xbar_smoke_zero_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_large_delays","qual_name":"13.xbar_smoke_large_delays.80592444957368317965563544892917865403349212421653090059340436123391380895364","seed":80592444957368317965563544892917865403349212421653090059340436123391380895364,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/13.xbar_smoke_large_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/13.xbar_smoke_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=791623300 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_large_delays.791623300' seed=80592444957368317965563544892917865403349212421653090059340436123391380895364 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=80592444957368317965563544892917865403349212421653090059340436123391380895364 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/13.xbar_smoke_large_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_slow_rsp","qual_name":"13.xbar_smoke_slow_rsp.43864089133707763531741935390815379752767465326556171984276437882384525583599","seed":43864089133707763531741935390815379752767465326556171984276437882384525583599,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/13.xbar_smoke_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/13.xbar_smoke_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2296145135 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_slow_rsp.2296145135' seed=43864089133707763531741935390815379752767465326556171984276437882384525583599 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=43864089133707763531741935390815379752767465326556171984276437882384525583599 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/13.xbar_smoke_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random","qual_name":"13.xbar_random.86201329418120053679218565458282706641974363957799663060222377509781748054970","seed":86201329418120053679218565458282706641974363957799663060222377509781748054970,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/13.xbar_random/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/13.xbar_random/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=495713210 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random.495713210' seed=86201329418120053679218565458282706641974363957799663060222377509781748054970 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=86201329418120053679218565458282706641974363957799663060222377509781748054970 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/13.xbar_random/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_zero_delays","qual_name":"13.xbar_random_zero_delays.106267416010439316105281060901190475044074305325179240511371889745990886831774","seed":106267416010439316105281060901190475044074305325179240511371889745990886831774,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/13.xbar_random_zero_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/13.xbar_random_zero_delays/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=510604958 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_zero_delays.510604958' seed=106267416010439316105281060901190475044074305325179240511371889745990886831774 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=106267416010439316105281060901190475044074305325179240511371889745990886831774 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/13.xbar_random_zero_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_large_delays","qual_name":"13.xbar_random_large_delays.13093133335819828482480822368950015839344752229372676524748922543125317154395","seed":13093133335819828482480822368950015839344752229372676524748922543125317154395,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/13.xbar_random_large_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/13.xbar_random_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4130469467 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_large_delays.4130469467' seed=13093133335819828482480822368950015839344752229372676524748922543125317154395 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=13093133335819828482480822368950015839344752229372676524748922543125317154395 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/13.xbar_random_large_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_slow_rsp","qual_name":"13.xbar_random_slow_rsp.115488275095826999068573355080598648537837581270731898199089163917985817205485","seed":115488275095826999068573355080598648537837581270731898199089163917985817205485,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/13.xbar_random_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/13.xbar_random_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=521313005 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_slow_rsp.521313005' seed=115488275095826999068573355080598648537837581270731898199089163917985817205485 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=115488275095826999068573355080598648537837581270731898199089163917985817205485 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/13.xbar_random_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device","qual_name":"13.xbar_access_same_device.69468750310729342472983883576654295722742079905287211849978073475212315930837","seed":69468750310729342472983883576654295722742079905287211849978073475212315930837,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/13.xbar_access_same_device/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/13.xbar_access_same_device/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3515560149 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device.3515560149' seed=69468750310729342472983883576654295722742079905287211849978073475212315930837 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=69468750310729342472983883576654295722742079905287211849978073475212315930837 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/13.xbar_access_same_device/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"13.xbar_access_same_device_slow_rsp.80783441835699143506470438220694441636937170840388115611023320951888110290650","seed":80783441835699143506470438220694441636937170840388115611023320951888110290650,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/13.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/13.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=95028954 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device_slow_rsp.95028954' seed=80783441835699143506470438220694441636937170840388115611023320951888110290650 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=80783441835699143506470438220694441636937170840388115611023320951888110290650 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/13.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_same_source","qual_name":"13.xbar_same_source.97107275915857671767227632997497718385700361201983571428072452478362087407600","seed":97107275915857671767227632997497718385700361201983571428072452478362087407600,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/13.xbar_same_source/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/13.xbar_same_source/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3278192624 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_same_source.3278192624' seed=97107275915857671767227632997497718385700361201983571428072452478362087407600 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=97107275915857671767227632997497718385700361201983571428072452478362087407600 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/13.xbar_same_source/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_same_source_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_random","qual_name":"13.xbar_error_random.78905671285841808417145223986405232182724656250988988605666187013212102602753","seed":78905671285841808417145223986405232182724656250988988605666187013212102602753,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/13.xbar_error_random/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/13.xbar_error_random/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1643524097 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_error_random.1643524097' seed=78905671285841808417145223986405232182724656250988988605666187013212102602753 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=78905671285841808417145223986405232182724656250988988605666187013212102602753 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/13.xbar_error_random/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_unmapped_addr","qual_name":"13.xbar_unmapped_addr.26951574888341909102748283801791595943690596734876284384607095245137859729804","seed":26951574888341909102748283801791595943690596734876284384607095245137859729804,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/13.xbar_unmapped_addr/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/13.xbar_unmapped_addr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2463259020 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_unmapped_addr.2463259020' seed=26951574888341909102748283801791595943690596734876284384607095245137859729804 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=26951574888341909102748283801791595943690596734876284384607095245137859729804 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/13.xbar_unmapped_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_and_unmapped_addr","qual_name":"13.xbar_error_and_unmapped_addr.18998459752802157929786734432948130677698884529333496241185106755897790047195","seed":18998459752802157929786734432948130677698884529333496241185106755897790047195,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/13.xbar_error_and_unmapped_addr/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/13.xbar_error_and_unmapped_addr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3914867675 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_error_and_unmapped_addr.3914867675' seed=18998459752802157929786734432948130677698884529333496241185106755897790047195 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=18998459752802157929786734432948130677698884529333496241185106755897790047195 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/13.xbar_error_and_unmapped_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all","qual_name":"13.xbar_stress_all.45788266298137547089602841520120595911860390282606845684122098922067868502754","seed":45788266298137547089602841520120595911860390282606845684122098922067868502754,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/13.xbar_stress_all/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/13.xbar_stress_all/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1911016162 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all.1911016162' seed=45788266298137547089602841520120595911860390282606845684122098922067868502754 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=45788266298137547089602841520120595911860390282606845684122098922067868502754 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/13.xbar_stress_all/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_rand_reset","qual_name":"13.xbar_stress_all_with_rand_reset.72545842534107617146845807877591059040089214633431134505620809254611186064109","seed":72545842534107617146845807877591059040089214633431134505620809254611186064109,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/13.xbar_stress_all_with_rand_reset/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/13.xbar_stress_all_with_rand_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2926025453 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_rand_reset.2926025453' seed=72545842534107617146845807877591059040089214633431134505620809254611186064109 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=72545842534107617146845807877591059040089214633431134505620809254611186064109 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/13.xbar_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"13.xbar_stress_all_with_error.35645207003556649133860962966150354829574480755757260367700164187255810025872","seed":35645207003556649133860962966150354829574480755757260367700164187255810025872,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/13.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/13.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2617502096 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_error.2617502096' seed=35645207003556649133860962966150354829574480755757260367700164187255810025872 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=35645207003556649133860962966150354829574480755757260367700164187255810025872 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/13.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"13.xbar_stress_all_with_reset_error.35529238844329699086935267718772046199448420833276508765519764082252085325141","seed":35529238844329699086935267718772046199448420833276508765519764082252085325141,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/13.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/13.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=177597781 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_reset_error.177597781' seed=35529238844329699086935267718772046199448420833276508765519764082252085325141 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=35529238844329699086935267718772046199448420833276508765519764082252085325141 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/13.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke","qual_name":"14.xbar_smoke.102098699248479831803276731967093161528209289062975935364327052295030866869188","seed":102098699248479831803276731967093161528209289062975935364327052295030866869188,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/14.xbar_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/14.xbar_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=764574660 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke.764574660' seed=102098699248479831803276731967093161528209289062975935364327052295030866869188 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=102098699248479831803276731967093161528209289062975935364327052295030866869188 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/14.xbar_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_zero_delays","qual_name":"14.xbar_smoke_zero_delays.94488260227091836443967896041920947877460199841508132179749816238542616732327","seed":94488260227091836443967896041920947877460199841508132179749816238542616732327,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/14.xbar_smoke_zero_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/14.xbar_smoke_zero_delays/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1310401191 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_zero_delays.1310401191' seed=94488260227091836443967896041920947877460199841508132179749816238542616732327 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=94488260227091836443967896041920947877460199841508132179749816238542616732327 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/14.xbar_smoke_zero_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_large_delays","qual_name":"14.xbar_smoke_large_delays.115752539664733576409784666020869047116398083981940733729836256107479002677566","seed":115752539664733576409784666020869047116398083981940733729836256107479002677566,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/14.xbar_smoke_large_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/14.xbar_smoke_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3816194366 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_large_delays.3816194366' seed=115752539664733576409784666020869047116398083981940733729836256107479002677566 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=115752539664733576409784666020869047116398083981940733729836256107479002677566 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/14.xbar_smoke_large_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_slow_rsp","qual_name":"14.xbar_smoke_slow_rsp.47935843924267200274961636568215092635374206224729621812200125571856507988503","seed":47935843924267200274961636568215092635374206224729621812200125571856507988503,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/14.xbar_smoke_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/14.xbar_smoke_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1267853847 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_slow_rsp.1267853847' seed=47935843924267200274961636568215092635374206224729621812200125571856507988503 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=47935843924267200274961636568215092635374206224729621812200125571856507988503 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/14.xbar_smoke_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random","qual_name":"14.xbar_random.93234616779829164963062633646078928052025984314675331836833758752335094670495","seed":93234616779829164963062633646078928052025984314675331836833758752335094670495,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/14.xbar_random/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/14.xbar_random/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2679432351 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random.2679432351' seed=93234616779829164963062633646078928052025984314675331836833758752335094670495 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=93234616779829164963062633646078928052025984314675331836833758752335094670495 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/14.xbar_random/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_zero_delays","qual_name":"14.xbar_random_zero_delays.53062388517415181855172605396926292071568130581414366592341996821807951389575","seed":53062388517415181855172605396926292071568130581414366592341996821807951389575,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/14.xbar_random_zero_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/14.xbar_random_zero_delays/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2407670663 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_zero_delays.2407670663' seed=53062388517415181855172605396926292071568130581414366592341996821807951389575 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=53062388517415181855172605396926292071568130581414366592341996821807951389575 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/14.xbar_random_zero_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_large_delays","qual_name":"14.xbar_random_large_delays.115703547786304486171803093859434661103262774264193002336925199918698811466997","seed":115703547786304486171803093859434661103262774264193002336925199918698811466997,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/14.xbar_random_large_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/14.xbar_random_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2196874485 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_large_delays.2196874485' seed=115703547786304486171803093859434661103262774264193002336925199918698811466997 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=115703547786304486171803093859434661103262774264193002336925199918698811466997 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/14.xbar_random_large_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_slow_rsp","qual_name":"14.xbar_random_slow_rsp.36713413184941127034787835553118118334531884305308450125700181728823735763735","seed":36713413184941127034787835553118118334531884305308450125700181728823735763735,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/14.xbar_random_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/14.xbar_random_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3418899223 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_slow_rsp.3418899223' seed=36713413184941127034787835553118118334531884305308450125700181728823735763735 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=36713413184941127034787835553118118334531884305308450125700181728823735763735 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/14.xbar_random_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device","qual_name":"14.xbar_access_same_device.114496328972386562490763992252814660057499384121255691483805671233524281236047","seed":114496328972386562490763992252814660057499384121255691483805671233524281236047,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/14.xbar_access_same_device/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/14.xbar_access_same_device/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3497122383 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device.3497122383' seed=114496328972386562490763992252814660057499384121255691483805671233524281236047 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=114496328972386562490763992252814660057499384121255691483805671233524281236047 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/14.xbar_access_same_device/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"14.xbar_access_same_device_slow_rsp.46934265479402249423867309903862482661808764481950876418055926840872612075025","seed":46934265479402249423867309903862482661808764481950876418055926840872612075025,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/14.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/14.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2199328273 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device_slow_rsp.2199328273' seed=46934265479402249423867309903862482661808764481950876418055926840872612075025 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=46934265479402249423867309903862482661808764481950876418055926840872612075025 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/14.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_same_source","qual_name":"14.xbar_same_source.95350040296533144464633594174442205039547767994059054152209139487929426349005","seed":95350040296533144464633594174442205039547767994059054152209139487929426349005,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/14.xbar_same_source/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/14.xbar_same_source/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=697142221 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_same_source.697142221' seed=95350040296533144464633594174442205039547767994059054152209139487929426349005 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=95350040296533144464633594174442205039547767994059054152209139487929426349005 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/14.xbar_same_source/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_same_source_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_random","qual_name":"14.xbar_error_random.28271610656597188215406400139571206667523042745727184456442685000398861833366","seed":28271610656597188215406400139571206667523042745727184456442685000398861833366,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/14.xbar_error_random/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/14.xbar_error_random/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=617682070 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_error_random.617682070' seed=28271610656597188215406400139571206667523042745727184456442685000398861833366 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=28271610656597188215406400139571206667523042745727184456442685000398861833366 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/14.xbar_error_random/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_unmapped_addr","qual_name":"14.xbar_unmapped_addr.95811745056605183197884429358324497642436390564965439696500835553724617763534","seed":95811745056605183197884429358324497642436390564965439696500835553724617763534,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/14.xbar_unmapped_addr/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/14.xbar_unmapped_addr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1407757006 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_unmapped_addr.1407757006' seed=95811745056605183197884429358324497642436390564965439696500835553724617763534 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=95811745056605183197884429358324497642436390564965439696500835553724617763534 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/14.xbar_unmapped_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_and_unmapped_addr","qual_name":"14.xbar_error_and_unmapped_addr.5961334513516743222327715517201462553884756298698662368330286997738944891728","seed":5961334513516743222327715517201462553884756298698662368330286997738944891728,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/14.xbar_error_and_unmapped_addr/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/14.xbar_error_and_unmapped_addr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2081327952 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_error_and_unmapped_addr.2081327952' seed=5961334513516743222327715517201462553884756298698662368330286997738944891728 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=5961334513516743222327715517201462553884756298698662368330286997738944891728 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/14.xbar_error_and_unmapped_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all","qual_name":"14.xbar_stress_all.93543321962814096308084268497482099345024104307538098403556920416277457785568","seed":93543321962814096308084268497482099345024104307538098403556920416277457785568,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/14.xbar_stress_all/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/14.xbar_stress_all/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1147917024 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all.1147917024' seed=93543321962814096308084268497482099345024104307538098403556920416277457785568 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=93543321962814096308084268497482099345024104307538098403556920416277457785568 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/14.xbar_stress_all/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_rand_reset","qual_name":"14.xbar_stress_all_with_rand_reset.73694010464966313030004317373679456399018549507156864801902357925163518238283","seed":73694010464966313030004317373679456399018549507156864801902357925163518238283,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/14.xbar_stress_all_with_rand_reset/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/14.xbar_stress_all_with_rand_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=279289419 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_rand_reset.279289419' seed=73694010464966313030004317373679456399018549507156864801902357925163518238283 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=73694010464966313030004317373679456399018549507156864801902357925163518238283 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/14.xbar_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"14.xbar_stress_all_with_error.48143931049611414403871176966041074202870632736791073420229177657991054029683","seed":48143931049611414403871176966041074202870632736791073420229177657991054029683,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/14.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/14.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=607974259 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_error.607974259' seed=48143931049611414403871176966041074202870632736791073420229177657991054029683 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=48143931049611414403871176966041074202870632736791073420229177657991054029683 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/14.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"14.xbar_stress_all_with_reset_error.29770201031285564568041063722432618556794117283555810698787351168900921642095","seed":29770201031285564568041063722432618556794117283555810698787351168900921642095,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/14.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/14.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4131736687 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_reset_error.4131736687' seed=29770201031285564568041063722432618556794117283555810698787351168900921642095 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=29770201031285564568041063722432618556794117283555810698787351168900921642095 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/14.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke","qual_name":"15.xbar_smoke.109153679903467977401804618081952155106400190995755749475378021467426252914840","seed":109153679903467977401804618081952155106400190995755749475378021467426252914840,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/15.xbar_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/15.xbar_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3985899672 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke.3985899672' seed=109153679903467977401804618081952155106400190995755749475378021467426252914840 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=109153679903467977401804618081952155106400190995755749475378021467426252914840 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/15.xbar_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_zero_delays","qual_name":"15.xbar_smoke_zero_delays.46316835430846566467231950485952397651744107474048456846638745679553487373469","seed":46316835430846566467231950485952397651744107474048456846638745679553487373469,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/15.xbar_smoke_zero_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/15.xbar_smoke_zero_delays/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=232457373 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_zero_delays.232457373' seed=46316835430846566467231950485952397651744107474048456846638745679553487373469 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=46316835430846566467231950485952397651744107474048456846638745679553487373469 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/15.xbar_smoke_zero_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_large_delays","qual_name":"15.xbar_smoke_large_delays.17448729145013850550741494366645635542521775542977264534447821059117168319134","seed":17448729145013850550741494366645635542521775542977264534447821059117168319134,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/15.xbar_smoke_large_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/15.xbar_smoke_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1405475486 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_large_delays.1405475486' seed=17448729145013850550741494366645635542521775542977264534447821059117168319134 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=17448729145013850550741494366645635542521775542977264534447821059117168319134 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/15.xbar_smoke_large_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_slow_rsp","qual_name":"15.xbar_smoke_slow_rsp.37556949342335766353295974647048840736439089986007410680641444620500977847627","seed":37556949342335766353295974647048840736439089986007410680641444620500977847627,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/15.xbar_smoke_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/15.xbar_smoke_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2567441739 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_slow_rsp.2567441739' seed=37556949342335766353295974647048840736439089986007410680641444620500977847627 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=37556949342335766353295974647048840736439089986007410680641444620500977847627 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/15.xbar_smoke_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random","qual_name":"15.xbar_random.62368138096421893295671865951571953155533432631898943677356315331858917670768","seed":62368138096421893295671865951571953155533432631898943677356315331858917670768,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/15.xbar_random/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/15.xbar_random/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3495346032 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random.3495346032' seed=62368138096421893295671865951571953155533432631898943677356315331858917670768 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=62368138096421893295671865951571953155533432631898943677356315331858917670768 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/15.xbar_random/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_zero_delays","qual_name":"15.xbar_random_zero_delays.35459681256577478495205970811478035397678697578931550510691361638405452680708","seed":35459681256577478495205970811478035397678697578931550510691361638405452680708,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/15.xbar_random_zero_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/15.xbar_random_zero_delays/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=701582852 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_zero_delays.701582852' seed=35459681256577478495205970811478035397678697578931550510691361638405452680708 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=35459681256577478495205970811478035397678697578931550510691361638405452680708 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/15.xbar_random_zero_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_large_delays","qual_name":"15.xbar_random_large_delays.20247655943867880086365862223988487669854671710028146175502561667212252386982","seed":20247655943867880086365862223988487669854671710028146175502561667212252386982,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/15.xbar_random_large_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/15.xbar_random_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2881590950 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_large_delays.2881590950' seed=20247655943867880086365862223988487669854671710028146175502561667212252386982 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=20247655943867880086365862223988487669854671710028146175502561667212252386982 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/15.xbar_random_large_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_slow_rsp","qual_name":"15.xbar_random_slow_rsp.27680054099364351290729578452108437132132004413489415537438910329845066604933","seed":27680054099364351290729578452108437132132004413489415537438910329845066604933,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/15.xbar_random_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/15.xbar_random_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2371461509 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_slow_rsp.2371461509' seed=27680054099364351290729578452108437132132004413489415537438910329845066604933 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=27680054099364351290729578452108437132132004413489415537438910329845066604933 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/15.xbar_random_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device","qual_name":"15.xbar_access_same_device.32571078463539575535293701959764098537709859362311093047503707630259141303730","seed":32571078463539575535293701959764098537709859362311093047503707630259141303730,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/15.xbar_access_same_device/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/15.xbar_access_same_device/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1313562034 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device.1313562034' seed=32571078463539575535293701959764098537709859362311093047503707630259141303730 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=32571078463539575535293701959764098537709859362311093047503707630259141303730 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/15.xbar_access_same_device/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"15.xbar_access_same_device_slow_rsp.86187446330125753909685537690316652793546209661688733006551025295584040309250","seed":86187446330125753909685537690316652793546209661688733006551025295584040309250,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/15.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/15.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1511510530 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device_slow_rsp.1511510530' seed=86187446330125753909685537690316652793546209661688733006551025295584040309250 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=86187446330125753909685537690316652793546209661688733006551025295584040309250 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/15.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_same_source","qual_name":"15.xbar_same_source.35650469831997355581242741692576781230641091881265778648441915990628518760321","seed":35650469831997355581242741692576781230641091881265778648441915990628518760321,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/15.xbar_same_source/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/15.xbar_same_source/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=817270657 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_same_source.817270657' seed=35650469831997355581242741692576781230641091881265778648441915990628518760321 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=35650469831997355581242741692576781230641091881265778648441915990628518760321 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/15.xbar_same_source/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_same_source_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_random","qual_name":"15.xbar_error_random.105774620227458980443618331919242850887965450532600004453785718831589381571604","seed":105774620227458980443618331919242850887965450532600004453785718831589381571604,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/15.xbar_error_random/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/15.xbar_error_random/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=556729364 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_error_random.556729364' seed=105774620227458980443618331919242850887965450532600004453785718831589381571604 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=105774620227458980443618331919242850887965450532600004453785718831589381571604 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/15.xbar_error_random/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_unmapped_addr","qual_name":"15.xbar_unmapped_addr.47941703400769743924366893231563703911916506620706235377828982372360246632195","seed":47941703400769743924366893231563703911916506620706235377828982372360246632195,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/15.xbar_unmapped_addr/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/15.xbar_unmapped_addr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3451494147 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_unmapped_addr.3451494147' seed=47941703400769743924366893231563703911916506620706235377828982372360246632195 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=47941703400769743924366893231563703911916506620706235377828982372360246632195 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/15.xbar_unmapped_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_and_unmapped_addr","qual_name":"15.xbar_error_and_unmapped_addr.65228188390425558809875638430267851043738811771864850671944221808442738687533","seed":65228188390425558809875638430267851043738811771864850671944221808442738687533,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/15.xbar_error_and_unmapped_addr/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/15.xbar_error_and_unmapped_addr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2512338477 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_error_and_unmapped_addr.2512338477' seed=65228188390425558809875638430267851043738811771864850671944221808442738687533 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=65228188390425558809875638430267851043738811771864850671944221808442738687533 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/15.xbar_error_and_unmapped_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all","qual_name":"15.xbar_stress_all.39428367218675530841083442090564844287182665031079570415435196170238058420531","seed":39428367218675530841083442090564844287182665031079570415435196170238058420531,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/15.xbar_stress_all/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/15.xbar_stress_all/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4047886643 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all.4047886643' seed=39428367218675530841083442090564844287182665031079570415435196170238058420531 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=39428367218675530841083442090564844287182665031079570415435196170238058420531 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/15.xbar_stress_all/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_rand_reset","qual_name":"15.xbar_stress_all_with_rand_reset.63814358622410884411837064632309121976745539921908136248354673930315916449781","seed":63814358622410884411837064632309121976745539921908136248354673930315916449781,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/15.xbar_stress_all_with_rand_reset/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/15.xbar_stress_all_with_rand_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=114890741 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_rand_reset.114890741' seed=63814358622410884411837064632309121976745539921908136248354673930315916449781 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=63814358622410884411837064632309121976745539921908136248354673930315916449781 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/15.xbar_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"15.xbar_stress_all_with_error.109232016943674229705717448674252952695219819708158156387087300385833245188255","seed":109232016943674229705717448674252952695219819708158156387087300385833245188255,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/15.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/15.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2701107359 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_error.2701107359' seed=109232016943674229705717448674252952695219819708158156387087300385833245188255 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=109232016943674229705717448674252952695219819708158156387087300385833245188255 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/15.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"15.xbar_stress_all_with_reset_error.45110450129632236480096982970324384777836065024195429375016461918166475222023","seed":45110450129632236480096982970324384777836065024195429375016461918166475222023,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/15.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/15.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=464399367 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_reset_error.464399367' seed=45110450129632236480096982970324384777836065024195429375016461918166475222023 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=45110450129632236480096982970324384777836065024195429375016461918166475222023 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/15.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke","qual_name":"16.xbar_smoke.89423729388768609345054344150748077789063517254086607080601670669029593772700","seed":89423729388768609345054344150748077789063517254086607080601670669029593772700,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/16.xbar_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/16.xbar_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2442064540 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke.2442064540' seed=89423729388768609345054344150748077789063517254086607080601670669029593772700 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=89423729388768609345054344150748077789063517254086607080601670669029593772700 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/16.xbar_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_zero_delays","qual_name":"16.xbar_smoke_zero_delays.92546059698181238739146087607701711364533907693821772493066775718021772093167","seed":92546059698181238739146087607701711364533907693821772493066775718021772093167,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/16.xbar_smoke_zero_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/16.xbar_smoke_zero_delays/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4219479791 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_zero_delays.4219479791' seed=92546059698181238739146087607701711364533907693821772493066775718021772093167 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=92546059698181238739146087607701711364533907693821772493066775718021772093167 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/16.xbar_smoke_zero_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_large_delays","qual_name":"16.xbar_smoke_large_delays.69556217714326033882803643304892908817008841534160495782636427712183491748356","seed":69556217714326033882803643304892908817008841534160495782636427712183491748356,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/16.xbar_smoke_large_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/16.xbar_smoke_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3008487940 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_large_delays.3008487940' seed=69556217714326033882803643304892908817008841534160495782636427712183491748356 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=69556217714326033882803643304892908817008841534160495782636427712183491748356 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/16.xbar_smoke_large_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_slow_rsp","qual_name":"16.xbar_smoke_slow_rsp.72106803870530050114917180125632872366356156575530024029130330164756942672711","seed":72106803870530050114917180125632872366356156575530024029130330164756942672711,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/16.xbar_smoke_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/16.xbar_smoke_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1070846791 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_slow_rsp.1070846791' seed=72106803870530050114917180125632872366356156575530024029130330164756942672711 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=72106803870530050114917180125632872366356156575530024029130330164756942672711 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/16.xbar_smoke_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random","qual_name":"16.xbar_random.110391093981256813223485889930029497925823362226283259545206918071177148501984","seed":110391093981256813223485889930029497925823362226283259545206918071177148501984,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/16.xbar_random/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/16.xbar_random/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2559447008 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random.2559447008' seed=110391093981256813223485889930029497925823362226283259545206918071177148501984 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=110391093981256813223485889930029497925823362226283259545206918071177148501984 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/16.xbar_random/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_zero_delays","qual_name":"16.xbar_random_zero_delays.85103220076275430089786004745159327098406124676353054137678260326019348257160","seed":85103220076275430089786004745159327098406124676353054137678260326019348257160,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/16.xbar_random_zero_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/16.xbar_random_zero_delays/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4186134920 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_zero_delays.4186134920' seed=85103220076275430089786004745159327098406124676353054137678260326019348257160 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=85103220076275430089786004745159327098406124676353054137678260326019348257160 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/16.xbar_random_zero_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_large_delays","qual_name":"16.xbar_random_large_delays.102649117351107028686176881077358537890144606402908688331292943829073891882726","seed":102649117351107028686176881077358537890144606402908688331292943829073891882726,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/16.xbar_random_large_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/16.xbar_random_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2633168614 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_large_delays.2633168614' seed=102649117351107028686176881077358537890144606402908688331292943829073891882726 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=102649117351107028686176881077358537890144606402908688331292943829073891882726 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/16.xbar_random_large_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_slow_rsp","qual_name":"16.xbar_random_slow_rsp.81812357592466526449602492479601490233323313414299200947497657877645557834997","seed":81812357592466526449602492479601490233323313414299200947497657877645557834997,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/16.xbar_random_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/16.xbar_random_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1814635765 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_slow_rsp.1814635765' seed=81812357592466526449602492479601490233323313414299200947497657877645557834997 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=81812357592466526449602492479601490233323313414299200947497657877645557834997 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/16.xbar_random_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device","qual_name":"16.xbar_access_same_device.44117943539170713692849929429095928398182191039109652776267198682088041798939","seed":44117943539170713692849929429095928398182191039109652776267198682088041798939,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/16.xbar_access_same_device/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/16.xbar_access_same_device/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1866652955 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device.1866652955' seed=44117943539170713692849929429095928398182191039109652776267198682088041798939 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=44117943539170713692849929429095928398182191039109652776267198682088041798939 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/16.xbar_access_same_device/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"16.xbar_access_same_device_slow_rsp.73304206979768624512176175175038485740623839268916372034649639920350918605313","seed":73304206979768624512176175175038485740623839268916372034649639920350918605313,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/16.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/16.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=852490753 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device_slow_rsp.852490753' seed=73304206979768624512176175175038485740623839268916372034649639920350918605313 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=73304206979768624512176175175038485740623839268916372034649639920350918605313 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/16.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_same_source","qual_name":"16.xbar_same_source.81340580860777377664506697679726270291647687665397593823902782393330003421971","seed":81340580860777377664506697679726270291647687665397593823902782393330003421971,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/16.xbar_same_source/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/16.xbar_same_source/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=355805971 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_same_source.355805971' seed=81340580860777377664506697679726270291647687665397593823902782393330003421971 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=81340580860777377664506697679726270291647687665397593823902782393330003421971 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/16.xbar_same_source/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_same_source_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_random","qual_name":"16.xbar_error_random.38875103926102363262971081366402216230513941250379765566396866358533110170549","seed":38875103926102363262971081366402216230513941250379765566396866358533110170549,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/16.xbar_error_random/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/16.xbar_error_random/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=530121653 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_error_random.530121653' seed=38875103926102363262971081366402216230513941250379765566396866358533110170549 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=38875103926102363262971081366402216230513941250379765566396866358533110170549 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/16.xbar_error_random/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_unmapped_addr","qual_name":"16.xbar_unmapped_addr.68979641759389821646504856974566673481860372278871747803042923019252228673143","seed":68979641759389821646504856974566673481860372278871747803042923019252228673143,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/16.xbar_unmapped_addr/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/16.xbar_unmapped_addr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=53988983 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_unmapped_addr.53988983' seed=68979641759389821646504856974566673481860372278871747803042923019252228673143 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=68979641759389821646504856974566673481860372278871747803042923019252228673143 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/16.xbar_unmapped_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_and_unmapped_addr","qual_name":"16.xbar_error_and_unmapped_addr.17427011314419649511506274943694346733597108513237525618091361085452104473241","seed":17427011314419649511506274943694346733597108513237525618091361085452104473241,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/16.xbar_error_and_unmapped_addr/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/16.xbar_error_and_unmapped_addr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1577818777 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_error_and_unmapped_addr.1577818777' seed=17427011314419649511506274943694346733597108513237525618091361085452104473241 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=17427011314419649511506274943694346733597108513237525618091361085452104473241 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/16.xbar_error_and_unmapped_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all","qual_name":"16.xbar_stress_all.77753645546536760214115988148604766042726726429851574947269807683095530367601","seed":77753645546536760214115988148604766042726726429851574947269807683095530367601,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/16.xbar_stress_all/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/16.xbar_stress_all/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3827362417 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all.3827362417' seed=77753645546536760214115988148604766042726726429851574947269807683095530367601 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=77753645546536760214115988148604766042726726429851574947269807683095530367601 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/16.xbar_stress_all/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_rand_reset","qual_name":"16.xbar_stress_all_with_rand_reset.85918387123893756180196988221340103916572605579384398690579692368088243872315","seed":85918387123893756180196988221340103916572605579384398690579692368088243872315,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/16.xbar_stress_all_with_rand_reset/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/16.xbar_stress_all_with_rand_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1375969851 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_rand_reset.1375969851' seed=85918387123893756180196988221340103916572605579384398690579692368088243872315 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=85918387123893756180196988221340103916572605579384398690579692368088243872315 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/16.xbar_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"16.xbar_stress_all_with_error.70098232022056238239209638625119933307493875992185666872218204933215635811297","seed":70098232022056238239209638625119933307493875992185666872218204933215635811297,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/16.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/16.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3738086369 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_error.3738086369' seed=70098232022056238239209638625119933307493875992185666872218204933215635811297 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=70098232022056238239209638625119933307493875992185666872218204933215635811297 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/16.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"16.xbar_stress_all_with_reset_error.80103023885855277583952326974912865737014648145068037540005692532969811179106","seed":80103023885855277583952326974912865737014648145068037540005692532969811179106,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/16.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/16.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=541816418 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_reset_error.541816418' seed=80103023885855277583952326974912865737014648145068037540005692532969811179106 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=80103023885855277583952326974912865737014648145068037540005692532969811179106 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/16.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke","qual_name":"17.xbar_smoke.62453276860404959066343475545377459883850967819050157648302217713657231596131","seed":62453276860404959066343475545377459883850967819050157648302217713657231596131,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/17.xbar_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/17.xbar_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3154270819 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke.3154270819' seed=62453276860404959066343475545377459883850967819050157648302217713657231596131 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=62453276860404959066343475545377459883850967819050157648302217713657231596131 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/17.xbar_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_zero_delays","qual_name":"17.xbar_smoke_zero_delays.20821393167944269098129838265040061144574454853927227962303684782035883148039","seed":20821393167944269098129838265040061144574454853927227962303684782035883148039,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/17.xbar_smoke_zero_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/17.xbar_smoke_zero_delays/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4244521735 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_zero_delays.4244521735' seed=20821393167944269098129838265040061144574454853927227962303684782035883148039 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=20821393167944269098129838265040061144574454853927227962303684782035883148039 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/17.xbar_smoke_zero_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_large_delays","qual_name":"17.xbar_smoke_large_delays.85357459938331360393069320924051016317029918549509729790736752167388384594636","seed":85357459938331360393069320924051016317029918549509729790736752167388384594636,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/17.xbar_smoke_large_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/17.xbar_smoke_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1854671564 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_large_delays.1854671564' seed=85357459938331360393069320924051016317029918549509729790736752167388384594636 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=85357459938331360393069320924051016317029918549509729790736752167388384594636 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/17.xbar_smoke_large_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_slow_rsp","qual_name":"17.xbar_smoke_slow_rsp.86165348194340287001368889559410810588450486894018262285218996541207125682239","seed":86165348194340287001368889559410810588450486894018262285218996541207125682239,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/17.xbar_smoke_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/17.xbar_smoke_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2819352639 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_slow_rsp.2819352639' seed=86165348194340287001368889559410810588450486894018262285218996541207125682239 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=86165348194340287001368889559410810588450486894018262285218996541207125682239 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/17.xbar_smoke_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random","qual_name":"17.xbar_random.113841722775354170844582839073030564350006400375325205829293525502908844897297","seed":113841722775354170844582839073030564350006400375325205829293525502908844897297,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/17.xbar_random/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/17.xbar_random/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=951481361 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random.951481361' seed=113841722775354170844582839073030564350006400375325205829293525502908844897297 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=113841722775354170844582839073030564350006400375325205829293525502908844897297 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/17.xbar_random/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_zero_delays","qual_name":"17.xbar_random_zero_delays.80831480264879015810173157692667219349895300332184369519984257076328549818113","seed":80831480264879015810173157692667219349895300332184369519984257076328549818113,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/17.xbar_random_zero_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/17.xbar_random_zero_delays/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2602540801 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_zero_delays.2602540801' seed=80831480264879015810173157692667219349895300332184369519984257076328549818113 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=80831480264879015810173157692667219349895300332184369519984257076328549818113 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/17.xbar_random_zero_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_large_delays","qual_name":"17.xbar_random_large_delays.64783200424302103029160894081023635971596911792746187450653842901790312566751","seed":64783200424302103029160894081023635971596911792746187450653842901790312566751,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/17.xbar_random_large_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/17.xbar_random_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1517490143 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_large_delays.1517490143' seed=64783200424302103029160894081023635971596911792746187450653842901790312566751 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=64783200424302103029160894081023635971596911792746187450653842901790312566751 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/17.xbar_random_large_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_slow_rsp","qual_name":"17.xbar_random_slow_rsp.35193942691606460363704349714919810751465725364905105690742967373490266084400","seed":35193942691606460363704349714919810751465725364905105690742967373490266084400,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/17.xbar_random_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/17.xbar_random_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3431502896 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_slow_rsp.3431502896' seed=35193942691606460363704349714919810751465725364905105690742967373490266084400 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=35193942691606460363704349714919810751465725364905105690742967373490266084400 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/17.xbar_random_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device","qual_name":"17.xbar_access_same_device.64660304912316152378082158065027495046979324897946272052857079787827276325203","seed":64660304912316152378082158065027495046979324897946272052857079787827276325203,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/17.xbar_access_same_device/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/17.xbar_access_same_device/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1685627219 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device.1685627219' seed=64660304912316152378082158065027495046979324897946272052857079787827276325203 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=64660304912316152378082158065027495046979324897946272052857079787827276325203 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/17.xbar_access_same_device/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"17.xbar_access_same_device_slow_rsp.24161379122999821665058301628802881581279537217363920366169326345465215968352","seed":24161379122999821665058301628802881581279537217363920366169326345465215968352,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/17.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/17.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1376117856 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device_slow_rsp.1376117856' seed=24161379122999821665058301628802881581279537217363920366169326345465215968352 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=24161379122999821665058301628802881581279537217363920366169326345465215968352 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/17.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_same_source","qual_name":"17.xbar_same_source.109874648170255046048787284147697410290202875004484289532843445690703695714165","seed":109874648170255046048787284147697410290202875004484289532843445690703695714165,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/17.xbar_same_source/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/17.xbar_same_source/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2772834165 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_same_source.2772834165' seed=109874648170255046048787284147697410290202875004484289532843445690703695714165 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=109874648170255046048787284147697410290202875004484289532843445690703695714165 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/17.xbar_same_source/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_same_source_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_random","qual_name":"17.xbar_error_random.39025503717333154106857427848809317627718011625624054976098637851804966941358","seed":39025503717333154106857427848809317627718011625624054976098637851804966941358,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/17.xbar_error_random/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/17.xbar_error_random/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3668800174 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_error_random.3668800174' seed=39025503717333154106857427848809317627718011625624054976098637851804966941358 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=39025503717333154106857427848809317627718011625624054976098637851804966941358 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/17.xbar_error_random/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_unmapped_addr","qual_name":"17.xbar_unmapped_addr.86633117541677279321024080888234873346645132109309571779873059327748396319522","seed":86633117541677279321024080888234873346645132109309571779873059327748396319522,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/17.xbar_unmapped_addr/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/17.xbar_unmapped_addr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2153808674 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_unmapped_addr.2153808674' seed=86633117541677279321024080888234873346645132109309571779873059327748396319522 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=86633117541677279321024080888234873346645132109309571779873059327748396319522 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/17.xbar_unmapped_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_and_unmapped_addr","qual_name":"17.xbar_error_and_unmapped_addr.110544060273495922041993673753132956337909896984743401851889544872643205697419","seed":110544060273495922041993673753132956337909896984743401851889544872643205697419,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/17.xbar_error_and_unmapped_addr/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/17.xbar_error_and_unmapped_addr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=457084811 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_error_and_unmapped_addr.457084811' seed=110544060273495922041993673753132956337909896984743401851889544872643205697419 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=110544060273495922041993673753132956337909896984743401851889544872643205697419 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/17.xbar_error_and_unmapped_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all","qual_name":"17.xbar_stress_all.37503922090706674663248785862593069763202299701647244265761300810800515069845","seed":37503922090706674663248785862593069763202299701647244265761300810800515069845,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/17.xbar_stress_all/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/17.xbar_stress_all/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1697724309 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all.1697724309' seed=37503922090706674663248785862593069763202299701647244265761300810800515069845 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=37503922090706674663248785862593069763202299701647244265761300810800515069845 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/17.xbar_stress_all/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_rand_reset","qual_name":"17.xbar_stress_all_with_rand_reset.55790238540271940122419955892491959936280569962280988662290739307691953831240","seed":55790238540271940122419955892491959936280569962280988662290739307691953831240,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/17.xbar_stress_all_with_rand_reset/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/17.xbar_stress_all_with_rand_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3014081864 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_rand_reset.3014081864' seed=55790238540271940122419955892491959936280569962280988662290739307691953831240 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=55790238540271940122419955892491959936280569962280988662290739307691953831240 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/17.xbar_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"17.xbar_stress_all_with_error.74725848773655908086735147013670554412658021813904939511921469781251767557415","seed":74725848773655908086735147013670554412658021813904939511921469781251767557415,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/17.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/17.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3705822503 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_error.3705822503' seed=74725848773655908086735147013670554412658021813904939511921469781251767557415 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=74725848773655908086735147013670554412658021813904939511921469781251767557415 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/17.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"17.xbar_stress_all_with_reset_error.65848636108618286425918842923345713812097133144735397048101293558135611476602","seed":65848636108618286425918842923345713812097133144735397048101293558135611476602,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/17.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/17.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=931154554 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_reset_error.931154554' seed=65848636108618286425918842923345713812097133144735397048101293558135611476602 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=65848636108618286425918842923345713812097133144735397048101293558135611476602 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/17.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke","qual_name":"18.xbar_smoke.101896341255801727021973667786362683246301644397418468733780243538225305290183","seed":101896341255801727021973667786362683246301644397418468733780243538225305290183,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/18.xbar_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/18.xbar_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2573010375 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke.2573010375' seed=101896341255801727021973667786362683246301644397418468733780243538225305290183 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=101896341255801727021973667786362683246301644397418468733780243538225305290183 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/18.xbar_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_zero_delays","qual_name":"18.xbar_smoke_zero_delays.7205792993061983580480382233258699639793528407388484959500089832755183251594","seed":7205792993061983580480382233258699639793528407388484959500089832755183251594,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/18.xbar_smoke_zero_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/18.xbar_smoke_zero_delays/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3801378954 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_zero_delays.3801378954' seed=7205792993061983580480382233258699639793528407388484959500089832755183251594 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=7205792993061983580480382233258699639793528407388484959500089832755183251594 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/18.xbar_smoke_zero_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_large_delays","qual_name":"18.xbar_smoke_large_delays.7559741178120128748683101908364502787427919004199326938822242252329934693902","seed":7559741178120128748683101908364502787427919004199326938822242252329934693902,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/18.xbar_smoke_large_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/18.xbar_smoke_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1998366222 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_large_delays.1998366222' seed=7559741178120128748683101908364502787427919004199326938822242252329934693902 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=7559741178120128748683101908364502787427919004199326938822242252329934693902 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/18.xbar_smoke_large_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_slow_rsp","qual_name":"18.xbar_smoke_slow_rsp.73226897364969744517192086306429124031377172358808890226735108227794931660673","seed":73226897364969744517192086306429124031377172358808890226735108227794931660673,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/18.xbar_smoke_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/18.xbar_smoke_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3272980353 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_slow_rsp.3272980353' seed=73226897364969744517192086306429124031377172358808890226735108227794931660673 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=73226897364969744517192086306429124031377172358808890226735108227794931660673 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/18.xbar_smoke_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random","qual_name":"18.xbar_random.58180162912269668257867645280718542729066752906389315348629039945968647905407","seed":58180162912269668257867645280718542729066752906389315348629039945968647905407,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/18.xbar_random/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/18.xbar_random/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2762711167 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random.2762711167' seed=58180162912269668257867645280718542729066752906389315348629039945968647905407 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=58180162912269668257867645280718542729066752906389315348629039945968647905407 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/18.xbar_random/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_zero_delays","qual_name":"18.xbar_random_zero_delays.115364234384610823202951408588659912597162964611186691655639351899371767860790","seed":115364234384610823202951408588659912597162964611186691655639351899371767860790,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/18.xbar_random_zero_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/18.xbar_random_zero_delays/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2346978870 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_zero_delays.2346978870' seed=115364234384610823202951408588659912597162964611186691655639351899371767860790 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=115364234384610823202951408588659912597162964611186691655639351899371767860790 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/18.xbar_random_zero_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_large_delays","qual_name":"18.xbar_random_large_delays.98073100229907665952184363740371985189885742449340384466667989135232772934457","seed":98073100229907665952184363740371985189885742449340384466667989135232772934457,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/18.xbar_random_large_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/18.xbar_random_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=688720697 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_large_delays.688720697' seed=98073100229907665952184363740371985189885742449340384466667989135232772934457 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=98073100229907665952184363740371985189885742449340384466667989135232772934457 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/18.xbar_random_large_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_slow_rsp","qual_name":"18.xbar_random_slow_rsp.35756065132296993003190418174754896913385814229832506410864734329590449829215","seed":35756065132296993003190418174754896913385814229832506410864734329590449829215,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/18.xbar_random_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/18.xbar_random_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=714208607 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_slow_rsp.714208607' seed=35756065132296993003190418174754896913385814229832506410864734329590449829215 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=35756065132296993003190418174754896913385814229832506410864734329590449829215 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/18.xbar_random_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device","qual_name":"18.xbar_access_same_device.25672241406487196361041847221318347183872348894780130506886217819036738657529","seed":25672241406487196361041847221318347183872348894780130506886217819036738657529,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/18.xbar_access_same_device/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/18.xbar_access_same_device/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=74980601 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device.74980601' seed=25672241406487196361041847221318347183872348894780130506886217819036738657529 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=25672241406487196361041847221318347183872348894780130506886217819036738657529 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/18.xbar_access_same_device/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"18.xbar_access_same_device_slow_rsp.74139149735462204224483275295466826735650008274809035530114399752808067624550","seed":74139149735462204224483275295466826735650008274809035530114399752808067624550,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/18.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/18.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3080580710 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device_slow_rsp.3080580710' seed=74139149735462204224483275295466826735650008274809035530114399752808067624550 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=74139149735462204224483275295466826735650008274809035530114399752808067624550 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/18.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_same_source","qual_name":"18.xbar_same_source.41921723490987699589780538092694229426726364189396892949239145929994640162814","seed":41921723490987699589780538092694229426726364189396892949239145929994640162814,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/18.xbar_same_source/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/18.xbar_same_source/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1041629182 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_same_source.1041629182' seed=41921723490987699589780538092694229426726364189396892949239145929994640162814 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=41921723490987699589780538092694229426726364189396892949239145929994640162814 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/18.xbar_same_source/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_same_source_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_random","qual_name":"18.xbar_error_random.13010465712475798485241745612530009563648954371308774602222098796525841199920","seed":13010465712475798485241745612530009563648954371308774602222098796525841199920,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/18.xbar_error_random/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/18.xbar_error_random/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=113685296 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_error_random.113685296' seed=13010465712475798485241745612530009563648954371308774602222098796525841199920 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=13010465712475798485241745612530009563648954371308774602222098796525841199920 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/18.xbar_error_random/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_unmapped_addr","qual_name":"18.xbar_unmapped_addr.99708546044211587898355449579362928491550110894173037134671782265401419227619","seed":99708546044211587898355449579362928491550110894173037134671782265401419227619,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/18.xbar_unmapped_addr/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/18.xbar_unmapped_addr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3213353443 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_unmapped_addr.3213353443' seed=99708546044211587898355449579362928491550110894173037134671782265401419227619 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=99708546044211587898355449579362928491550110894173037134671782265401419227619 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/18.xbar_unmapped_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_and_unmapped_addr","qual_name":"18.xbar_error_and_unmapped_addr.105548644182064224928498259676254369251268358902471897179115285133594498662868","seed":105548644182064224928498259676254369251268358902471897179115285133594498662868,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/18.xbar_error_and_unmapped_addr/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/18.xbar_error_and_unmapped_addr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2859172308 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_error_and_unmapped_addr.2859172308' seed=105548644182064224928498259676254369251268358902471897179115285133594498662868 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=105548644182064224928498259676254369251268358902471897179115285133594498662868 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/18.xbar_error_and_unmapped_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all","qual_name":"18.xbar_stress_all.44246027267655227288237187586893789060903440185079332204098736542044518775713","seed":44246027267655227288237187586893789060903440185079332204098736542044518775713,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/18.xbar_stress_all/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/18.xbar_stress_all/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1836481441 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all.1836481441' seed=44246027267655227288237187586893789060903440185079332204098736542044518775713 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=44246027267655227288237187586893789060903440185079332204098736542044518775713 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/18.xbar_stress_all/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_rand_reset","qual_name":"18.xbar_stress_all_with_rand_reset.47557429890139738799820101740197041935739772800408080431033457576893131681259","seed":47557429890139738799820101740197041935739772800408080431033457576893131681259,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/18.xbar_stress_all_with_rand_reset/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/18.xbar_stress_all_with_rand_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4291718635 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_rand_reset.4291718635' seed=47557429890139738799820101740197041935739772800408080431033457576893131681259 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=47557429890139738799820101740197041935739772800408080431033457576893131681259 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/18.xbar_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"18.xbar_stress_all_with_error.94546156722572710746665104406640994640840616224070381227332452845760919061772","seed":94546156722572710746665104406640994640840616224070381227332452845760919061772,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/18.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/18.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2284799244 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_error.2284799244' seed=94546156722572710746665104406640994640840616224070381227332452845760919061772 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=94546156722572710746665104406640994640840616224070381227332452845760919061772 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/18.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"18.xbar_stress_all_with_reset_error.40909972573475914563029076239088618008618791208256780027784658441529070336530","seed":40909972573475914563029076239088618008618791208256780027784658441529070336530,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/18.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/18.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2931440146 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_reset_error.2931440146' seed=40909972573475914563029076239088618008618791208256780027784658441529070336530 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=40909972573475914563029076239088618008618791208256780027784658441529070336530 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/18.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke","qual_name":"19.xbar_smoke.83192069661463296765855064106703304628269429195052012362989629159359087136296","seed":83192069661463296765855064106703304628269429195052012362989629159359087136296,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/19.xbar_smoke/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/19.xbar_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1897156136 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke.1897156136' seed=83192069661463296765855064106703304628269429195052012362989629159359087136296 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=83192069661463296765855064106703304628269429195052012362989629159359087136296 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/19.xbar_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_zero_delays","qual_name":"19.xbar_smoke_zero_delays.21372114588452862850436099247963690289040259117850639583518294818081207311541","seed":21372114588452862850436099247963690289040259117850639583518294818081207311541,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/19.xbar_smoke_zero_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/19.xbar_smoke_zero_delays/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3178323125 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_zero_delays.3178323125' seed=21372114588452862850436099247963690289040259117850639583518294818081207311541 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=21372114588452862850436099247963690289040259117850639583518294818081207311541 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/19.xbar_smoke_zero_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_large_delays","qual_name":"19.xbar_smoke_large_delays.2594241710774851548731619135753347338926756180449375770314051043637890998424","seed":2594241710774851548731619135753347338926756180449375770314051043637890998424,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/19.xbar_smoke_large_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/19.xbar_smoke_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3178324120 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_large_delays.3178324120' seed=2594241710774851548731619135753347338926756180449375770314051043637890998424 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=2594241710774851548731619135753347338926756180449375770314051043637890998424 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/19.xbar_smoke_large_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_smoke_slow_rsp","qual_name":"19.xbar_smoke_slow_rsp.28356337694348607296665967707808907999066541074608964251671036505124739535897","seed":28356337694348607296665967707808907999066541074608964251671036505124739535897,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/19.xbar_smoke_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/19.xbar_smoke_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2056311833 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_slow_rsp.2056311833' seed=28356337694348607296665967707808907999066541074608964251671036505124739535897 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=28356337694348607296665967707808907999066541074608964251671036505124739535897 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/19.xbar_smoke_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_smoke_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random","qual_name":"19.xbar_random.97279950641725566177592321268127997852044218793432424345381352278095315050247","seed":97279950641725566177592321268127997852044218793432424345381352278095315050247,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/19.xbar_random/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/19.xbar_random/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=987471623 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random.987471623' seed=97279950641725566177592321268127997852044218793432424345381352278095315050247 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=97279950641725566177592321268127997852044218793432424345381352278095315050247 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/19.xbar_random/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_zero_delays","qual_name":"19.xbar_random_zero_delays.36766788271838420346793065490382690836620661329833303788427451464235696644083","seed":36766788271838420346793065490382690836620661329833303788427451464235696644083,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/19.xbar_random_zero_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/19.xbar_random_zero_delays/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3301564403 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_zero_delays.3301564403' seed=36766788271838420346793065490382690836620661329833303788427451464235696644083 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=36766788271838420346793065490382690836620661329833303788427451464235696644083 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/19.xbar_random_zero_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_large_delays","qual_name":"19.xbar_random_large_delays.89656154984451058091994656287510333571958618645246925621971142789933176000192","seed":89656154984451058091994656287510333571958618645246925621971142789933176000192,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/19.xbar_random_large_delays/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/19.xbar_random_large_delays/latest run_opts='+max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3957395136 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_large_delays.3957395136' seed=89656154984451058091994656287510333571958618645246925621971142789933176000192 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=89656154984451058091994656287510333571958618645246925621971142789933176000192 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/19.xbar_random_large_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_random_slow_rsp","qual_name":"19.xbar_random_slow_rsp.49372807655638493245346882149593304952064243790714918350280463961160238964154","seed":49372807655638493245346882149593304952064243790714918350280463961160238964154,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/19.xbar_random_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/19.xbar_random_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3955170746 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_slow_rsp.3955170746' seed=49372807655638493245346882149593304952064243790714918350280463961160238964154 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=49372807655638493245346882149593304952064243790714918350280463961160238964154 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/19.xbar_random_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device","qual_name":"19.xbar_access_same_device.98830918089312572434659186770214025574287782600325227120315822241356891050610","seed":98830918089312572434659186770214025574287782600325227120315822241356891050610,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/19.xbar_access_same_device/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/19.xbar_access_same_device/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4213985906 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device.4213985906' seed=98830918089312572434659186770214025574287782600325227120315822241356891050610 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=98830918089312572434659186770214025574287782600325227120315822241356891050610 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/19.xbar_access_same_device/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"19.xbar_access_same_device_slow_rsp.12008874328524986150694192966329856065558973833990915873229490767503120350601","seed":12008874328524986150694192966329856065558973833990915873229490767503120350601,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/19.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/19.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1910455689 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device_slow_rsp.1910455689' seed=12008874328524986150694192966329856065558973833990915873229490767503120350601 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=12008874328524986150694192966329856065558973833990915873229490767503120350601 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/19.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_same_source","qual_name":"19.xbar_same_source.43453536126437036193220277894783064260913338032688859615859653457994916984955","seed":43453536126437036193220277894783064260913338032688859615859653457994916984955,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/19.xbar_same_source/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/19.xbar_same_source/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3365304443 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_same_source.3365304443' seed=43453536126437036193220277894783064260913338032688859615859653457994916984955 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=43453536126437036193220277894783064260913338032688859615859653457994916984955 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/19.xbar_same_source/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_same_source_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_random","qual_name":"19.xbar_error_random.62347502566192928627131948721416896706648762085593408116075219647667130638655","seed":62347502566192928627131948721416896706648762085593408116075219647667130638655,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/19.xbar_error_random/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/19.xbar_error_random/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3789332799 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_error_random.3789332799' seed=62347502566192928627131948721416896706648762085593408116075219647667130638655 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=62347502566192928627131948721416896706648762085593408116075219647667130638655 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/19.xbar_error_random/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_random_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_unmapped_addr","qual_name":"19.xbar_unmapped_addr.42996204418777203808309210177245972789881159020606611852196387363934383836735","seed":42996204418777203808309210177245972789881159020606611852196387363934383836735,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/19.xbar_unmapped_addr/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/19.xbar_unmapped_addr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3016691263 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_unmapped_addr.3016691263' seed=42996204418777203808309210177245972789881159020606611852196387363934383836735 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=42996204418777203808309210177245972789881159020606611852196387363934383836735 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/19.xbar_unmapped_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_error_and_unmapped_addr","qual_name":"19.xbar_error_and_unmapped_addr.101327964431343143897953330146818541819104472327004742829394569421404547752397","seed":101327964431343143897953330146818541819104472327004742829394569421404547752397,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/19.xbar_error_and_unmapped_addr/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/19.xbar_error_and_unmapped_addr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3013255629 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_error_and_unmapped_addr.3013255629' seed=101327964431343143897953330146818541819104472327004742829394569421404547752397 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=101327964431343143897953330146818541819104472327004742829394569421404547752397 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/19.xbar_error_and_unmapped_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_unmapped_addr_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all","qual_name":"19.xbar_stress_all.63932453448811278983537602225439159343670191945146710157996520880807636096703","seed":63932453448811278983537602225439159343670191945146710157996520880807636096703,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/19.xbar_stress_all/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/19.xbar_stress_all/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2494027455 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all.2494027455' seed=63932453448811278983537602225439159343670191945146710157996520880807636096703 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=63932453448811278983537602225439159343670191945146710157996520880807636096703 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/19.xbar_stress_all/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_rand_reset","qual_name":"19.xbar_stress_all_with_rand_reset.36364900006174454168153834748670794151108450604555766676164794418951087940294","seed":36364900006174454168153834748670794151108450604555766676164794418951087940294,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/19.xbar_stress_all_with_rand_reset/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/19.xbar_stress_all_with_rand_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2264883910 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_rand_reset.2264883910' seed=36364900006174454168153834748670794151108450604555766676164794418951087940294 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=36364900006174454168153834748670794151108450604555766676164794418951087940294 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/19.xbar_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"19.xbar_stress_all_with_error.48840863508494339804847435868300384763557080036141468299827862191655257969634","seed":48840863508494339804847435868300384763557080036141468299827862191655257969634,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/19.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/19.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3974173666 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_error.3974173666' seed=48840863508494339804847435868300384763557080036141468299827862191655257969634 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=48840863508494339804847435868300384763557080036141468299827862191655257969634 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/19.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"19.xbar_stress_all_with_reset_error.72137615115918950956832104671925154930050190089574231034990847272470824113778","seed":72137615115918950956832104671925154930050190089574231034990847272470824113778,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/19.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/19.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1483232882 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_reset_error.1483232882' seed=72137615115918950956832104671925154930050190089574231034990847272470824113778 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=72137615115918950956832104671925154930050190089574231034990847272470824113778 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/19.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"20.xbar_access_same_device_slow_rsp.103880115959736323332948087293658611641447879538804459974902196157255107156571","seed":103880115959736323332948087293658611641447879538804459974902196157255107156571,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/20.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/20.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2430540379 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device_slow_rsp.2430540379' seed=103880115959736323332948087293658611641447879538804459974902196157255107156571 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=103880115959736323332948087293658611641447879538804459974902196157255107156571 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/20.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"20.xbar_stress_all_with_error.102557915468663992679307472421654301057465345968389220309073699042932389255419","seed":102557915468663992679307472421654301057465345968389220309073699042932389255419,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/20.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/20.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=980621563 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_error.980621563' seed=102557915468663992679307472421654301057465345968389220309073699042932389255419 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=102557915468663992679307472421654301057465345968389220309073699042932389255419 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/20.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"20.xbar_stress_all_with_reset_error.44347173616797707481854443188028062613524035742412831529995417578051698903969","seed":44347173616797707481854443188028062613524035742412831529995417578051698903969,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/20.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/20.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2932820897 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_reset_error.2932820897' seed=44347173616797707481854443188028062613524035742412831529995417578051698903969 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=44347173616797707481854443188028062613524035742412831529995417578051698903969 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/20.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"21.xbar_access_same_device_slow_rsp.8752510246721397205082030281045899906254185321514060135529647369689873608401","seed":8752510246721397205082030281045899906254185321514060135529647369689873608401,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/21.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/21.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2873716433 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device_slow_rsp.2873716433' seed=8752510246721397205082030281045899906254185321514060135529647369689873608401 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=8752510246721397205082030281045899906254185321514060135529647369689873608401 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/21.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"21.xbar_stress_all_with_error.45590821171601668841412365724997567699577264111850924050067085713648322886857","seed":45590821171601668841412365724997567699577264111850924050067085713648322886857,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/21.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/21.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1595686089 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_error.1595686089' seed=45590821171601668841412365724997567699577264111850924050067085713648322886857 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=45590821171601668841412365724997567699577264111850924050067085713648322886857 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/21.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"21.xbar_stress_all_with_reset_error.29496090011926841325796814976999313398818279785400009357827322875917758983767","seed":29496090011926841325796814976999313398818279785400009357827322875917758983767,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/21.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/21.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1589210711 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_reset_error.1589210711' seed=29496090011926841325796814976999313398818279785400009357827322875917758983767 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=29496090011926841325796814976999313398818279785400009357827322875917758983767 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/21.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"22.xbar_access_same_device_slow_rsp.51954215345601198831455916115622400413641392349210866599500123121553735409775","seed":51954215345601198831455916115622400413641392349210866599500123121553735409775,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/22.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/22.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2756173935 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device_slow_rsp.2756173935' seed=51954215345601198831455916115622400413641392349210866599500123121553735409775 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=51954215345601198831455916115622400413641392349210866599500123121553735409775 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/22.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"22.xbar_stress_all_with_error.63634903843514850171189198426650082482497617188653555940309482801320799488629","seed":63634903843514850171189198426650082482497617188653555940309482801320799488629,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/22.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/22.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2576075381 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_error.2576075381' seed=63634903843514850171189198426650082482497617188653555940309482801320799488629 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=63634903843514850171189198426650082482497617188653555940309482801320799488629 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/22.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"22.xbar_stress_all_with_reset_error.105826664355758100920252445906757112796391979875733349211704446434009264902920","seed":105826664355758100920252445906757112796391979875733349211704446434009264902920,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/22.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/22.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=264459016 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_reset_error.264459016' seed=105826664355758100920252445906757112796391979875733349211704446434009264902920 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=105826664355758100920252445906757112796391979875733349211704446434009264902920 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/22.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"23.xbar_access_same_device_slow_rsp.6853428615033168074035567123653487633047395581158981776747443554162578888150","seed":6853428615033168074035567123653487633047395581158981776747443554162578888150,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/23.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/23.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3589608918 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device_slow_rsp.3589608918' seed=6853428615033168074035567123653487633047395581158981776747443554162578888150 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=6853428615033168074035567123653487633047395581158981776747443554162578888150 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/23.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"23.xbar_stress_all_with_error.59165335505041506032023036367817950777161091823620759685986027159057189416270","seed":59165335505041506032023036367817950777161091823620759685986027159057189416270,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/23.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/23.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=612216142 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_error.612216142' seed=59165335505041506032023036367817950777161091823620759685986027159057189416270 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=59165335505041506032023036367817950777161091823620759685986027159057189416270 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/23.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"23.xbar_stress_all_with_reset_error.112664391263619931904737674020706825767010570965548045737187702147097090320892","seed":112664391263619931904737674020706825767010570965548045737187702147097090320892,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/23.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/23.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3956271612 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_reset_error.3956271612' seed=112664391263619931904737674020706825767010570965548045737187702147097090320892 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=112664391263619931904737674020706825767010570965548045737187702147097090320892 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/23.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"24.xbar_access_same_device_slow_rsp.87651230521429009617579002976585675573571309458171564994894691900532403915753","seed":87651230521429009617579002976585675573571309458171564994894691900532403915753,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/24.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/24.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1917766633 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device_slow_rsp.1917766633' seed=87651230521429009617579002976585675573571309458171564994894691900532403915753 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=87651230521429009617579002976585675573571309458171564994894691900532403915753 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/24.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"24.xbar_stress_all_with_error.25557504736653748631283184434659012286018434588082987365072217785433688955848","seed":25557504736653748631283184434659012286018434588082987365072217785433688955848,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/24.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/24.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1032379336 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_error.1032379336' seed=25557504736653748631283184434659012286018434588082987365072217785433688955848 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=25557504736653748631283184434659012286018434588082987365072217785433688955848 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/24.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"24.xbar_stress_all_with_reset_error.88006705625110964266004339372853803270887168814385879422593395472505398478054","seed":88006705625110964266004339372853803270887168814385879422593395472505398478054,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/24.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/24.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3961111782 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_reset_error.3961111782' seed=88006705625110964266004339372853803270887168814385879422593395472505398478054 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=88006705625110964266004339372853803270887168814385879422593395472505398478054 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/24.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"25.xbar_access_same_device_slow_rsp.7743478393695738205608882331260501594121337470121419183785594059085863710326","seed":7743478393695738205608882331260501594121337470121419183785594059085863710326,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/25.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/25.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1837362806 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device_slow_rsp.1837362806' seed=7743478393695738205608882331260501594121337470121419183785594059085863710326 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=7743478393695738205608882331260501594121337470121419183785594059085863710326 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/25.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"25.xbar_stress_all_with_error.112760275380134343530495737911221845701167819267891105264441621506757875379367","seed":112760275380134343530495737911221845701167819267891105264441621506757875379367,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/25.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/25.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2850991271 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_error.2850991271' seed=112760275380134343530495737911221845701167819267891105264441621506757875379367 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=112760275380134343530495737911221845701167819267891105264441621506757875379367 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/25.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"25.xbar_stress_all_with_reset_error.89381025342402358589203886667849049548547345705155418145135494498383251077671","seed":89381025342402358589203886667849049548547345705155418145135494498383251077671,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/25.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/25.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3557521959 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_reset_error.3557521959' seed=89381025342402358589203886667849049548547345705155418145135494498383251077671 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=89381025342402358589203886667849049548547345705155418145135494498383251077671 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/25.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"26.xbar_access_same_device_slow_rsp.20157657901045475372596665929597422345247669186217072433821545580325203825400","seed":20157657901045475372596665929597422345247669186217072433821545580325203825400,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/26.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/26.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=411783928 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device_slow_rsp.411783928' seed=20157657901045475372596665929597422345247669186217072433821545580325203825400 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=20157657901045475372596665929597422345247669186217072433821545580325203825400 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/26.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"26.xbar_stress_all_with_error.20779851419397162381661304114301406833223292954897399392918691194297795912238","seed":20779851419397162381661304114301406833223292954897399392918691194297795912238,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/26.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/26.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3145638446 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_error.3145638446' seed=20779851419397162381661304114301406833223292954897399392918691194297795912238 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=20779851419397162381661304114301406833223292954897399392918691194297795912238 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/26.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"26.xbar_stress_all_with_reset_error.75187556865182690030989718096490118543674480434277433569140006634507373754573","seed":75187556865182690030989718096490118543674480434277433569140006634507373754573,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/26.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/26.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3566581965 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_reset_error.3566581965' seed=75187556865182690030989718096490118543674480434277433569140006634507373754573 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=75187556865182690030989718096490118543674480434277433569140006634507373754573 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/26.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"27.xbar_access_same_device_slow_rsp.113587323570287644869503235745407611189606954190368947297400539716476781838733","seed":113587323570287644869503235745407611189606954190368947297400539716476781838733,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/27.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/27.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=350339469 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device_slow_rsp.350339469' seed=113587323570287644869503235745407611189606954190368947297400539716476781838733 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=113587323570287644869503235745407611189606954190368947297400539716476781838733 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/27.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"27.xbar_stress_all_with_error.89314934672088462755672407477752087213794015805141964118703611173448523589186","seed":89314934672088462755672407477752087213794015805141964118703611173448523589186,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/27.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/27.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4240582210 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_error.4240582210' seed=89314934672088462755672407477752087213794015805141964118703611173448523589186 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=89314934672088462755672407477752087213794015805141964118703611173448523589186 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/27.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"27.xbar_stress_all_with_reset_error.104896237825317290393221885861145144704529555351564746308986092677071716497349","seed":104896237825317290393221885861145144704529555351564746308986092677071716497349,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/27.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/27.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3693361093 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_reset_error.3693361093' seed=104896237825317290393221885861145144704529555351564746308986092677071716497349 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=104896237825317290393221885861145144704529555351564746308986092677071716497349 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/27.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"28.xbar_access_same_device_slow_rsp.104975482567256617947485635097215124844194307620554231525281300069340909780939","seed":104975482567256617947485635097215124844194307620554231525281300069340909780939,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/28.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/28.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1791868875 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device_slow_rsp.1791868875' seed=104975482567256617947485635097215124844194307620554231525281300069340909780939 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=104975482567256617947485635097215124844194307620554231525281300069340909780939 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/28.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"28.xbar_stress_all_with_error.33709253557294023361425772235828834678763596882456120390188807856658235763032","seed":33709253557294023361425772235828834678763596882456120390188807856658235763032,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/28.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/28.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=79931736 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_error.79931736' seed=33709253557294023361425772235828834678763596882456120390188807856658235763032 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=33709253557294023361425772235828834678763596882456120390188807856658235763032 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/28.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"28.xbar_stress_all_with_reset_error.42559560524097669967254322533259298055039999449454479330424965336444212315496","seed":42559560524097669967254322533259298055039999449454479330424965336444212315496,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/28.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/28.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3437462888 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_reset_error.3437462888' seed=42559560524097669967254322533259298055039999449454479330424965336444212315496 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=42559560524097669967254322533259298055039999449454479330424965336444212315496 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/28.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"29.xbar_access_same_device_slow_rsp.106169822487541492341165609707025721866472001247642572533548576472594196535633","seed":106169822487541492341165609707025721866472001247642572533548576472594196535633,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/29.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/29.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1225070929 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device_slow_rsp.1225070929' seed=106169822487541492341165609707025721866472001247642572533548576472594196535633 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=106169822487541492341165609707025721866472001247642572533548576472594196535633 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/29.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"29.xbar_stress_all_with_error.21490247290838841513350691793564682439526092132853552371466310327997186264804","seed":21490247290838841513350691793564682439526092132853552371466310327997186264804,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/29.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/29.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3658305252 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_error.3658305252' seed=21490247290838841513350691793564682439526092132853552371466310327997186264804 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=21490247290838841513350691793564682439526092132853552371466310327997186264804 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/29.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"29.xbar_stress_all_with_reset_error.114334071168425172480754823110846154972983906120477866966121446918825148122902","seed":114334071168425172480754823110846154972983906120477866966121446918825148122902,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/29.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/29.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3496445718 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_reset_error.3496445718' seed=114334071168425172480754823110846154972983906120477866966121446918825148122902 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=114334071168425172480754823110846154972983906120477866966121446918825148122902 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/29.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"30.xbar_access_same_device_slow_rsp.114674134542449591382526706279105025527799198664802367057486867348205978961938","seed":114674134542449591382526706279105025527799198664802367057486867348205978961938,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/30.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/30.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=174770194 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device_slow_rsp.174770194' seed=114674134542449591382526706279105025527799198664802367057486867348205978961938 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=114674134542449591382526706279105025527799198664802367057486867348205978961938 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/30.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"30.xbar_stress_all_with_error.105973612044703680051964423865259383943424619571735482172253986508025342396151","seed":105973612044703680051964423865259383943424619571735482172253986508025342396151,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/30.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/30.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2112816887 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_error.2112816887' seed=105973612044703680051964423865259383943424619571735482172253986508025342396151 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=105973612044703680051964423865259383943424619571735482172253986508025342396151 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/30.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"30.xbar_stress_all_with_reset_error.101741228518421208690165568003547970712575142048245720163709812100894466084995","seed":101741228518421208690165568003547970712575142048245720163709812100894466084995,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/30.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/30.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=675385475 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_reset_error.675385475' seed=101741228518421208690165568003547970712575142048245720163709812100894466084995 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=101741228518421208690165568003547970712575142048245720163709812100894466084995 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/30.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"31.xbar_access_same_device_slow_rsp.77772920255301763081564780262092769083650476235165819765338135180251755091904","seed":77772920255301763081564780262092769083650476235165819765338135180251755091904,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/31.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/31.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2812975040 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device_slow_rsp.2812975040' seed=77772920255301763081564780262092769083650476235165819765338135180251755091904 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=77772920255301763081564780262092769083650476235165819765338135180251755091904 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/31.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"31.xbar_stress_all_with_error.46117232797521955499598095621813840190588881397996936114651651528696973259555","seed":46117232797521955499598095621813840190588881397996936114651651528696973259555,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/31.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/31.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=916222755 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_error.916222755' seed=46117232797521955499598095621813840190588881397996936114651651528696973259555 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=46117232797521955499598095621813840190588881397996936114651651528696973259555 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/31.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"31.xbar_stress_all_with_reset_error.49413446686661308854545686286230841288383181891008797481069859180721503271679","seed":49413446686661308854545686286230841288383181891008797481069859180721503271679,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/31.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/31.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=212138751 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_reset_error.212138751' seed=49413446686661308854545686286230841288383181891008797481069859180721503271679 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=49413446686661308854545686286230841288383181891008797481069859180721503271679 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/31.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"32.xbar_access_same_device_slow_rsp.85709923890537679836736246090738965131959018392987132906143413011165167480137","seed":85709923890537679836736246090738965131959018392987132906143413011165167480137,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/32.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/32.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1261432137 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device_slow_rsp.1261432137' seed=85709923890537679836736246090738965131959018392987132906143413011165167480137 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=85709923890537679836736246090738965131959018392987132906143413011165167480137 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/32.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"32.xbar_stress_all_with_error.25183963861402662685472892363770903936727575463667892933865466974480950382012","seed":25183963861402662685472892363770903936727575463667892933865466974480950382012,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/32.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/32.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=574377404 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_error.574377404' seed=25183963861402662685472892363770903936727575463667892933865466974480950382012 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=25183963861402662685472892363770903936727575463667892933865466974480950382012 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/32.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"32.xbar_stress_all_with_reset_error.80389671498454961448431813806887538215985600075548210514559223985360487244647","seed":80389671498454961448431813806887538215985600075548210514559223985360487244647,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/32.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/32.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2572608359 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_reset_error.2572608359' seed=80389671498454961448431813806887538215985600075548210514559223985360487244647 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=80389671498454961448431813806887538215985600075548210514559223985360487244647 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/32.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"33.xbar_access_same_device_slow_rsp.11114273223699376556197422853912255614022787360675935045283208451454687392264","seed":11114273223699376556197422853912255614022787360675935045283208451454687392264,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/33.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/33.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1245327880 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device_slow_rsp.1245327880' seed=11114273223699376556197422853912255614022787360675935045283208451454687392264 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=11114273223699376556197422853912255614022787360675935045283208451454687392264 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/33.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"33.xbar_stress_all_with_error.16804617652036795135572849709001785058231074241775443873001767561944773247927","seed":16804617652036795135572849709001785058231074241775443873001767561944773247927,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/33.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/33.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2941600695 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_error.2941600695' seed=16804617652036795135572849709001785058231074241775443873001767561944773247927 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=16804617652036795135572849709001785058231074241775443873001767561944773247927 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/33.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"33.xbar_stress_all_with_reset_error.73211355494312654799927299143778142125082786673457370938601821286946969222077","seed":73211355494312654799927299143778142125082786673457370938601821286946969222077,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/33.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/33.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1187511229 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_reset_error.1187511229' seed=73211355494312654799927299143778142125082786673457370938601821286946969222077 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=73211355494312654799927299143778142125082786673457370938601821286946969222077 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/33.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"34.xbar_access_same_device_slow_rsp.71618143024903228826198098549162510711439232913884436280470838354712342219684","seed":71618143024903228826198098549162510711439232913884436280470838354712342219684,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/34.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/34.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2911292324 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device_slow_rsp.2911292324' seed=71618143024903228826198098549162510711439232913884436280470838354712342219684 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=71618143024903228826198098549162510711439232913884436280470838354712342219684 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/34.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"34.xbar_stress_all_with_error.63746579098806561571257088378793059095052915538831502933282402529851505749247","seed":63746579098806561571257088378793059095052915538831502933282402529851505749247,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/34.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/34.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2042998015 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_error.2042998015' seed=63746579098806561571257088378793059095052915538831502933282402529851505749247 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=63746579098806561571257088378793059095052915538831502933282402529851505749247 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/34.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"34.xbar_stress_all_with_reset_error.97205606821256446668678939572968433416877097027751093526777843084102083505524","seed":97205606821256446668678939572968433416877097027751093526777843084102083505524,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/34.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/34.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1958440308 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_reset_error.1958440308' seed=97205606821256446668678939572968433416877097027751093526777843084102083505524 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=97205606821256446668678939572968433416877097027751093526777843084102083505524 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/34.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"35.xbar_access_same_device_slow_rsp.86924606373363810734742487670791447773874202110352496848949837735516557645706","seed":86924606373363810734742487670791447773874202110352496848949837735516557645706,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/35.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/35.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4024014730 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device_slow_rsp.4024014730' seed=86924606373363810734742487670791447773874202110352496848949837735516557645706 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=86924606373363810734742487670791447773874202110352496848949837735516557645706 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/35.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"35.xbar_stress_all_with_error.79359822375223893672456684221725900055676771626395142861465403475427295409678","seed":79359822375223893672456684221725900055676771626395142861465403475427295409678,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/35.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/35.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=38712846 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_error.38712846' seed=79359822375223893672456684221725900055676771626395142861465403475427295409678 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=79359822375223893672456684221725900055676771626395142861465403475427295409678 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/35.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"35.xbar_stress_all_with_reset_error.70632522481989139584799520564507366829081894032977158529663116789866678742566","seed":70632522481989139584799520564507366829081894032977158529663116789866678742566,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/35.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/35.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=660368934 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_reset_error.660368934' seed=70632522481989139584799520564507366829081894032977158529663116789866678742566 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=70632522481989139584799520564507366829081894032977158529663116789866678742566 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/35.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"36.xbar_access_same_device_slow_rsp.111734636425361643257923771874465973486562269011142107518782669003107038232548","seed":111734636425361643257923771874465973486562269011142107518782669003107038232548,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/36.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/36.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2329772004 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device_slow_rsp.2329772004' seed=111734636425361643257923771874465973486562269011142107518782669003107038232548 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=111734636425361643257923771874465973486562269011142107518782669003107038232548 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/36.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"36.xbar_stress_all_with_error.69835320017144479357264053975602711331810993547076126484633726616107866128702","seed":69835320017144479357264053975602711331810993547076126484633726616107866128702,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/36.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/36.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3224633662 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_error.3224633662' seed=69835320017144479357264053975602711331810993547076126484633726616107866128702 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=69835320017144479357264053975602711331810993547076126484633726616107866128702 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/36.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"36.xbar_stress_all_with_reset_error.59112300680625225470509086897153250326172704598117812131316365710238482617450","seed":59112300680625225470509086897153250326172704598117812131316365710238482617450,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/36.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/36.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4140487786 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_reset_error.4140487786' seed=59112300680625225470509086897153250326172704598117812131316365710238482617450 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=59112300680625225470509086897153250326172704598117812131316365710238482617450 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/36.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"37.xbar_access_same_device_slow_rsp.21165661159720409657479019864728821286851466228560617443153697278138425123992","seed":21165661159720409657479019864728821286851466228560617443153697278138425123992,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/37.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/37.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2568856728 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device_slow_rsp.2568856728' seed=21165661159720409657479019864728821286851466228560617443153697278138425123992 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=21165661159720409657479019864728821286851466228560617443153697278138425123992 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/37.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"37.xbar_stress_all_with_error.65351527977134108109792650958919499191245515468256570209739564013720125841888","seed":65351527977134108109792650958919499191245515468256570209739564013720125841888,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/37.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/37.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3973587424 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_error.3973587424' seed=65351527977134108109792650958919499191245515468256570209739564013720125841888 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=65351527977134108109792650958919499191245515468256570209739564013720125841888 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/37.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"37.xbar_stress_all_with_reset_error.57776880900333243799083370793303411206440217996667720033884645971526465908541","seed":57776880900333243799083370793303411206440217996667720033884645971526465908541,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/37.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/37.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1240756029 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_reset_error.1240756029' seed=57776880900333243799083370793303411206440217996667720033884645971526465908541 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=57776880900333243799083370793303411206440217996667720033884645971526465908541 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/37.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"38.xbar_access_same_device_slow_rsp.52863420979299408798586712372758389695110498382896459033687202851741303915816","seed":52863420979299408798586712372758389695110498382896459033687202851741303915816,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/38.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/38.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2440643880 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device_slow_rsp.2440643880' seed=52863420979299408798586712372758389695110498382896459033687202851741303915816 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=52863420979299408798586712372758389695110498382896459033687202851741303915816 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/38.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"38.xbar_stress_all_with_error.81842304651305510401367288886258685050031857299247471671993917599954299921202","seed":81842304651305510401367288886258685050031857299247471671993917599954299921202,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/38.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/38.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2570724146 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_error.2570724146' seed=81842304651305510401367288886258685050031857299247471671993917599954299921202 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=81842304651305510401367288886258685050031857299247471671993917599954299921202 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/38.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"38.xbar_stress_all_with_reset_error.97189253390088680932868003501573564787342720951640616125518225020659722687179","seed":97189253390088680932868003501573564787342720951640616125518225020659722687179,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/38.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/38.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2589790923 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_reset_error.2589790923' seed=97189253390088680932868003501573564787342720951640616125518225020659722687179 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=97189253390088680932868003501573564787342720951640616125518225020659722687179 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/38.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"39.xbar_access_same_device_slow_rsp.9041240624638505037316376544327322492670154064280445620870055385966335826492","seed":9041240624638505037316376544327322492670154064280445620870055385966335826492,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/39.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/39.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3612678716 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device_slow_rsp.3612678716' seed=9041240624638505037316376544327322492670154064280445620870055385966335826492 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=9041240624638505037316376544327322492670154064280445620870055385966335826492 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/39.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"39.xbar_stress_all_with_error.49899700027374981563470328504993807731537999231485529046714575460629859245810","seed":49899700027374981563470328504993807731537999231485529046714575460629859245810,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/39.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/39.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2946735858 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_error.2946735858' seed=49899700027374981563470328504993807731537999231485529046714575460629859245810 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=49899700027374981563470328504993807731537999231485529046714575460629859245810 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/39.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"39.xbar_stress_all_with_reset_error.29343648467664122979530954816957934130164089564971020640186554402991877277039","seed":29343648467664122979530954816957934130164089564971020640186554402991877277039,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/39.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/39.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=736773487 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_reset_error.736773487' seed=29343648467664122979530954816957934130164089564971020640186554402991877277039 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=29343648467664122979530954816957934130164089564971020640186554402991877277039 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/39.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"40.xbar_access_same_device_slow_rsp.71573861345757675336553830895653004974624029778473134220259086127450072877113","seed":71573861345757675336553830895653004974624029778473134220259086127450072877113,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/40.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/40.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3165456441 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device_slow_rsp.3165456441' seed=71573861345757675336553830895653004974624029778473134220259086127450072877113 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=71573861345757675336553830895653004974624029778473134220259086127450072877113 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/40.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"40.xbar_stress_all_with_error.110451979794014324106777345811913089093017878725379476360134091746491836265684","seed":110451979794014324106777345811913089093017878725379476360134091746491836265684,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/40.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/40.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2191652052 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_error.2191652052' seed=110451979794014324106777345811913089093017878725379476360134091746491836265684 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=110451979794014324106777345811913089093017878725379476360134091746491836265684 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/40.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"40.xbar_stress_all_with_reset_error.72762292809800283797354218927661864191622930033301099197004562974672721448460","seed":72762292809800283797354218927661864191622930033301099197004562974672721448460,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/40.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/40.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2731183628 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_reset_error.2731183628' seed=72762292809800283797354218927661864191622930033301099197004562974672721448460 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=72762292809800283797354218927661864191622930033301099197004562974672721448460 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/40.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"41.xbar_access_same_device_slow_rsp.26225481150510249039436671719353261832951771744655725203159187678306306576633","seed":26225481150510249039436671719353261832951771744655725203159187678306306576633,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/41.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/41.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3899609337 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device_slow_rsp.3899609337' seed=26225481150510249039436671719353261832951771744655725203159187678306306576633 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=26225481150510249039436671719353261832951771744655725203159187678306306576633 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/41.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"41.xbar_stress_all_with_error.32376111302170667243704190138020034592338564315224667469894597660556532157513","seed":32376111302170667243704190138020034592338564315224667469894597660556532157513,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/41.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/41.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3048508489 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_error.3048508489' seed=32376111302170667243704190138020034592338564315224667469894597660556532157513 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=32376111302170667243704190138020034592338564315224667469894597660556532157513 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/41.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"41.xbar_stress_all_with_reset_error.3457898179928447573908078168226696756825608661089762459963583811332689632658","seed":3457898179928447573908078168226696756825608661089762459963583811332689632658,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/41.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/41.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1423711634 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_reset_error.1423711634' seed=3457898179928447573908078168226696756825608661089762459963583811332689632658 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=3457898179928447573908078168226696756825608661089762459963583811332689632658 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/41.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"42.xbar_access_same_device_slow_rsp.101482555782681944843108255657467670678568309774885749641093599392389379523562","seed":101482555782681944843108255657467670678568309774885749641093599392389379523562,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/42.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/42.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2768110570 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device_slow_rsp.2768110570' seed=101482555782681944843108255657467670678568309774885749641093599392389379523562 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=101482555782681944843108255657467670678568309774885749641093599392389379523562 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/42.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"42.xbar_stress_all_with_error.55019782111596850287190212863728091049937005639887021339010541990667227919359","seed":55019782111596850287190212863728091049937005639887021339010541990667227919359,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/42.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/42.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=209351679 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_error.209351679' seed=55019782111596850287190212863728091049937005639887021339010541990667227919359 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=55019782111596850287190212863728091049937005639887021339010541990667227919359 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/42.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"42.xbar_stress_all_with_reset_error.84334832396093264241693605705050021735284375529810392321178962264447480883527","seed":84334832396093264241693605705050021735284375529810392321178962264447480883527,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/42.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/42.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=238938439 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_reset_error.238938439' seed=84334832396093264241693605705050021735284375529810392321178962264447480883527 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=84334832396093264241693605705050021735284375529810392321178962264447480883527 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/42.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"43.xbar_access_same_device_slow_rsp.108256116927764366895093273803975687245977062918152607370944414553107788979382","seed":108256116927764366895093273803975687245977062918152607370944414553107788979382,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/43.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/43.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3981171894 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device_slow_rsp.3981171894' seed=108256116927764366895093273803975687245977062918152607370944414553107788979382 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=108256116927764366895093273803975687245977062918152607370944414553107788979382 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/43.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"43.xbar_stress_all_with_error.49646599015661653266742894518464611624030767609232999382736400723936750209178","seed":49646599015661653266742894518464611624030767609232999382736400723936750209178,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/43.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/43.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1480460442 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_error.1480460442' seed=49646599015661653266742894518464611624030767609232999382736400723936750209178 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=49646599015661653266742894518464611624030767609232999382736400723936750209178 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/43.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"43.xbar_stress_all_with_reset_error.22609170207859489725960049922138956823094084090610369510997893885577424289853","seed":22609170207859489725960049922138956823094084090610369510997893885577424289853,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/43.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/43.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=611074109 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_reset_error.611074109' seed=22609170207859489725960049922138956823094084090610369510997893885577424289853 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=22609170207859489725960049922138956823094084090610369510997893885577424289853 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/43.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"44.xbar_access_same_device_slow_rsp.71985300827103975885835141035131705812846813806244361719398929288456828707835","seed":71985300827103975885835141035131705812846813806244361719398929288456828707835,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/44.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/44.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3036505083 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device_slow_rsp.3036505083' seed=71985300827103975885835141035131705812846813806244361719398929288456828707835 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=71985300827103975885835141035131705812846813806244361719398929288456828707835 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/44.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"44.xbar_stress_all_with_error.79054343522053267377200762660906816443275746756977400879667919098963029646437","seed":79054343522053267377200762660906816443275746756977400879667919098963029646437,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/44.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/44.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2780552293 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_error.2780552293' seed=79054343522053267377200762660906816443275746756977400879667919098963029646437 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=79054343522053267377200762660906816443275746756977400879667919098963029646437 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/44.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"44.xbar_stress_all_with_reset_error.55381691611512029793166491860090759390113204750169653338817942002533259838217","seed":55381691611512029793166491860090759390113204750169653338817942002533259838217,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/44.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/44.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2665251593 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_reset_error.2665251593' seed=55381691611512029793166491860090759390113204750169653338817942002533259838217 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=55381691611512029793166491860090759390113204750169653338817942002533259838217 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/44.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"45.xbar_access_same_device_slow_rsp.24645674862786605722920618038846787529132513847227235134982294349122077823344","seed":24645674862786605722920618038846787529132513847227235134982294349122077823344,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/45.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/45.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1908248944 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device_slow_rsp.1908248944' seed=24645674862786605722920618038846787529132513847227235134982294349122077823344 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=24645674862786605722920618038846787529132513847227235134982294349122077823344 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/45.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"45.xbar_stress_all_with_error.98284704336932954988111202461010404246466076324429874628707795331342763250617","seed":98284704336932954988111202461010404246466076324429874628707795331342763250617,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/45.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/45.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1338987449 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_error.1338987449' seed=98284704336932954988111202461010404246466076324429874628707795331342763250617 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=98284704336932954988111202461010404246466076324429874628707795331342763250617 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/45.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"45.xbar_stress_all_with_reset_error.70485829550539232767634409005249726972749252950194457814265029014341873049522","seed":70485829550539232767634409005249726972749252950194457814265029014341873049522,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/45.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/45.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3305119666 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_reset_error.3305119666' seed=70485829550539232767634409005249726972749252950194457814265029014341873049522 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=70485829550539232767634409005249726972749252950194457814265029014341873049522 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/45.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"46.xbar_access_same_device_slow_rsp.108403797078888678104834426313375085431045747851844396982675755635624763076918","seed":108403797078888678104834426313375085431045747851844396982675755635624763076918,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/46.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/46.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3826135350 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device_slow_rsp.3826135350' seed=108403797078888678104834426313375085431045747851844396982675755635624763076918 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=108403797078888678104834426313375085431045747851844396982675755635624763076918 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/46.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"46.xbar_stress_all_with_error.40929300126546322626682899660761112962919869969524494444392067242772241129363","seed":40929300126546322626682899660761112962919869969524494444392067242772241129363,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/46.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/46.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=767893395 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_error.767893395' seed=40929300126546322626682899660761112962919869969524494444392067242772241129363 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=40929300126546322626682899660761112962919869969524494444392067242772241129363 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/46.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"46.xbar_stress_all_with_reset_error.38152976065434417493002092418374819902420449871471207460674847984702817437695","seed":38152976065434417493002092418374819902420449871471207460674847984702817437695,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/46.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/46.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2922252287 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_reset_error.2922252287' seed=38152976065434417493002092418374819902420449871471207460674847984702817437695 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=38152976065434417493002092418374819902420449871471207460674847984702817437695 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/46.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"47.xbar_access_same_device_slow_rsp.72117454096808578584228539055836837612853738002857630393930285523429104841087","seed":72117454096808578584228539055836837612853738002857630393930285523429104841087,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/47.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/47.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=29389183 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device_slow_rsp.29389183' seed=72117454096808578584228539055836837612853738002857630393930285523429104841087 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=72117454096808578584228539055836837612853738002857630393930285523429104841087 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/47.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"47.xbar_stress_all_with_error.59537058821986634094559565083181194658362284818781797399321996109610959473724","seed":59537058821986634094559565083181194658362284818781797399321996109610959473724,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/47.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/47.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1130073148 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_error.1130073148' seed=59537058821986634094559565083181194658362284818781797399321996109610959473724 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=59537058821986634094559565083181194658362284818781797399321996109610959473724 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/47.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"47.xbar_stress_all_with_reset_error.6051146802205677244416570695062463085683933808588012386021982676572752055201","seed":6051146802205677244416570695062463085683933808588012386021982676572752055201,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/47.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/47.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3295677345 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_reset_error.3295677345' seed=6051146802205677244416570695062463085683933808588012386021982676572752055201 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=6051146802205677244416570695062463085683933808588012386021982676572752055201 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/47.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"48.xbar_access_same_device_slow_rsp.5270447784195187702565508559360249899351423305191510808639184445757740582920","seed":5270447784195187702565508559360249899351423305191510808639184445757740582920,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/48.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/48.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=269518856 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device_slow_rsp.269518856' seed=5270447784195187702565508559360249899351423305191510808639184445757740582920 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=5270447784195187702565508559360249899351423305191510808639184445757740582920 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/48.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"48.xbar_stress_all_with_error.74764698002668939131052907367148364784006596897956603629068616600797221037254","seed":74764698002668939131052907367148364784006596897956603629068616600797221037254,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/48.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/48.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3477415110 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_error.3477415110' seed=74764698002668939131052907367148364784006596897956603629068616600797221037254 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=74764698002668939131052907367148364784006596897956603629068616600797221037254 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/48.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"48.xbar_stress_all_with_reset_error.58176849469216901103037258761569202630890288497413441331178062612760582222395","seed":58176849469216901103037258761569202630890288497413441331178062612760582222395,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/48.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/48.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1985016379 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_reset_error.1985016379' seed=58176849469216901103037258761569202630890288497413441331178062612760582222395 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=58176849469216901103037258761569202630890288497413441331178062612760582222395 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/48.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_access_same_device_slow_rsp","qual_name":"49.xbar_access_same_device_slow_rsp.70192600840826162092577165807092369465128555260599805568169577351158776031227","seed":70192600840826162092577165807092369465128555260599805568169577351158776031227,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/49.xbar_access_same_device_slow_rsp/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/49.xbar_access_same_device_slow_rsp/latest run_opts='+max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2055563259 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device_slow_rsp.2055563259' seed=70192600840826162092577165807092369465128555260599805568169577351158776031227 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=70192600840826162092577165807092369465128555260599805568169577351158776031227 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/49.xbar_access_same_device_slow_rsp/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_base_test uvm_test_seq=xbar_access_same_device_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_error","qual_name":"49.xbar_stress_all_with_error.20271744659564426252737544237277044342404333372561875695015644749544530122962","seed":20271744659564426252737544237277044342404333372561875695015644749544530122962,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/49.xbar_stress_all_with_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/49.xbar_stress_all_with_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1493965010 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_error.1493965010' seed=20271744659564426252737544237277044342404333372561875695015644749544530122962 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=20271744659564426252737544237277044342404333372561875695015644749544530122962 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/49.xbar_stress_all_with_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]},{"name":"xbar_stress_all_with_reset_error","qual_name":"49.xbar_stress_all_with_reset_error.23169648971468025477713868297001071924772871930649407037886668639858646433253","seed":23169648971468025477713868297001071924772871930649407037886668639858646433253,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/49.xbar_stress_all_with_reset_error/latest/run.log","log_context":["[Executing]:\n","make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/xbar_build_mode/simv run_dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/49.xbar_stress_all_with_reset_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3380723173 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_reset_error.3380723173' seed=23169648971468025477713868297001071924772871930649407037886668639858646433253 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='\"'\"''\"'\"' --sw-build-opts='\"'\"''\"'\"' --sw-build-device= --seed=23169648971468025477713868297001071924772871930649407037886668639858646433253 --run-dir=/nightly/current_run/scratch/master/xbar_peri-sim-vcs/49.xbar_stress_all_with_reset_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=xbar_error_test uvm_test_seq=xbar_stress_all_with_rand_reset_vseq\n","\n","/usr/bin/env: ‘bash’: Input/output error\n","make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126\n"]}],"Job cancelled because all of its dependencies failed or were killed.":[{"name":"xbar_peri","qual_name":"cov_merge","seed":null,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/cov_merge/merged.vdb/cov_merge.log","log_context":[]}],"Job cancelled because one of its dependencies failed or was killed.":[{"name":"xbar_peri","qual_name":"cov_report","seed":null,"line":null,"log_path":"/nightly/current_run/scratch/master/xbar_peri-sim-vcs/cov_report/cov_report.log","log_context":[]}]}},"passed":0,"total":450,"percent":0.0}