ADC_CTRL Simulation Results

Friday January 24 2025 17:10:00 UTC

GitHub Revision: 002bb67a7c

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	22.170s	5.805ms	50	50	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	3.870s	979.737us	5	5	100.00
V1	csr_rw	adc_ctrl_csr_rw	3.010s	419.633us	20	20	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	1.661m	51.246ms	5	5	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	4.380s	1.147ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	3.190s	541.484us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	3.010s	419.633us	20	20	100.00
		adc_ctrl_csr_aliasing	4.380s	1.147ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	filters_polled	adc_ctrl_filters_polled	14.942m	496.654ms	50	50	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	14.157m	486.886ms	50	50	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	13.767m	492.049ms	50	50	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	16.038m	493.249ms	50	50	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	18.161m	565.641ms	50	50	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	18.873m	616.428ms	50	50	100.00
V2	filters_both	adc_ctrl_filters_both	16.820m	600.000ms	47	50	94.00
V2	clock_gating	adc_ctrl_clock_gating	19.261m	2.000s	31	50	62.00
V2	poweron_counter	adc_ctrl_poweron_counter	16.750s	5.027ms	50	50	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	1.442m	30.748ms	50	50	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	3.974m	119.574ms	50	50	100.00
V2	stress_all	adc_ctrl_stress_all	13.842m	520.740ms	50	50	100.00
V2	alert_test	adc_ctrl_alert_test	3.570s	492.966us	50	50	100.00
V2	intr_test	adc_ctrl_intr_test	2.840s	526.743us	50	50	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	4.160s	822.014us	20	20	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	4.160s	822.014us	20	20	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	3.870s	979.737us	5	5	100.00
		adc_ctrl_csr_rw	3.010s	419.633us	20	20	100.00
		adc_ctrl_csr_aliasing	4.380s	1.147ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	15.710s	6.053ms	20	20	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	3.870s	979.737us	5	5	100.00
		adc_ctrl_csr_rw	3.010s	419.633us	20	20	100.00
		adc_ctrl_csr_aliasing	4.380s	1.147ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	15.710s	6.053ms	20	20	100.00
V2		TOTAL			718	740	97.03
V2S	tl_intg_err	adc_ctrl_sec_cm	12.290s	4.374ms	5	5	100.00
		adc_ctrl_tl_intg_err	23.200s	8.484ms	20	20	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	23.200s	8.484ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	4.003m	10.000s	48	50	96.00
V3		TOTAL			48	50	96.00
		TOTAL			896	920	97.39

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.62	99.09	96.38	100.00	100.00	98.83	98.35	90.72

Failure Buckets

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 15 failures:

  • Test adc_ctrl_filters_both has 2 failures.

    • 3.adc_ctrl_filters_both.11740895539024316846100530343994571823744599319272003501926211282147295452260
      Line 178, in log /nightly/runs/opentitan/scratch/master/adc_ctrl-sim-vcs/3.adc_ctrl_filters_both/latest/run.log

        UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 4.adc_ctrl_filters_both.66886454403696052334884442086173812748630385522620000448615965369312508823970
      Line 178, in log /nightly/runs/opentitan/scratch/master/adc_ctrl-sim-vcs/4.adc_ctrl_filters_both/latest/run.log

        UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test adc_ctrl_clock_gating has 12 failures.

    • 7.adc_ctrl_clock_gating.16218791442629850934003764785896033577070739737834135792056564078854364449289
      Line 163, in log /nightly/runs/opentitan/scratch/master/adc_ctrl-sim-vcs/7.adc_ctrl_clock_gating/latest/run.log

        UVM_FATAL @ 2000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 2000000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 2000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 9.adc_ctrl_clock_gating.112819459960324855009539387399964681011139837918583535023571272725084681783714
      Line 163, in log /nightly/runs/opentitan/scratch/master/adc_ctrl-sim-vcs/9.adc_ctrl_clock_gating/latest/run.log

        UVM_FATAL @ 2000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 2000000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 2000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 10 more failures.

  • Test adc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 9.adc_ctrl_stress_all_with_rand_reset.76179237503738265636134206548257211952301273743284070428708040006880290026229
      Line 159, in log /nightly/runs/opentitan/scratch/master/adc_ctrl-sim-vcs/9.adc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_scoreboard.sv:249) scoreboard [scoreboard] alert fatal_fault has unexpected timeout error has 7 failures:

  • Test adc_ctrl_clock_gating has 6 failures.

    • 3.adc_ctrl_clock_gating.47479445393006059100708076511947395898818825555591410106930032457302657261252
      Line 180, in log /nightly/runs/opentitan/scratch/master/adc_ctrl-sim-vcs/3.adc_ctrl_clock_gating/latest/run.log

        UVM_ERROR @ 416855327024 ps: (cip_base_scoreboard.sv:249) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
        UVM_INFO @ 416855327024 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 20.adc_ctrl_clock_gating.58074432496070232831075323153931277733878374640380586618939491816027983789423
      Line 146, in log /nightly/runs/opentitan/scratch/master/adc_ctrl-sim-vcs/20.adc_ctrl_clock_gating/latest/run.log

        UVM_ERROR @ 4486566641 ps: (cip_base_scoreboard.sv:249) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
        UVM_INFO @ 4486566641 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 4 more failures.

  • Test adc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 28.adc_ctrl_stress_all_with_rand_reset.92265521580000594756843226799422382592802477369176058350388183943235787749458
      Line 197, in log /nightly/runs/opentitan/scratch/master/adc_ctrl-sim-vcs/28.adc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 58432855536 ps: (cip_base_scoreboard.sv:249) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
        UVM_INFO @ 58432855536 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (adc_ctrl_scoreboard.sv:405) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: adc_ctrl_reg_block.intr_state has 2 failures:

  • Test adc_ctrl_clock_gating has 1 failures.

    • 1.adc_ctrl_clock_gating.102969414154263671252878843520693786798434400988691164122578492174874311483373
      Line 146, in log /nightly/runs/opentitan/scratch/master/adc_ctrl-sim-vcs/1.adc_ctrl_clock_gating/latest/run.log

        UVM_ERROR @ 80305491495 ps: (adc_ctrl_scoreboard.sv:405) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
        UVM_INFO @ 80305491495 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test adc_ctrl_filters_both has 1 failures.

    • 49.adc_ctrl_filters_both.7276881663572653023398335864848892300536495035389387786125742667704065641468
      Line 146, in log /nightly/runs/opentitan/scratch/master/adc_ctrl-sim-vcs/49.adc_ctrl_filters_both/latest/run.log

        UVM_ERROR @ 81421436335 ps: (adc_ctrl_scoreboard.sv:405) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
        UVM_INFO @ 81421436335 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---