AES/MASKED Simulation Results

Friday January 24 2025 17:10:00 UTC

GitHub Revision: `002bb67a7c`

Branch: master

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	7.000s	66.779us	1	1	100.00
V1	smoke	aes_smoke	9.000s	658.302us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	7.000s	78.213us	5	5	100.00
V1	csr_rw	aes_csr_rw	7.000s	65.378us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	11.000s	776.061us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	9.000s	516.858us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	7.000s	76.015us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	7.000s	65.378us	20	20	100.00
		aes_csr_aliasing	9.000s	516.858us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	9.000s	658.302us	50	50	100.00
		aes_config_error	28.000s	1.432ms	50	50	100.00
		aes_stress	12.000s	320.961us	50	50	100.00
V2	key_length	aes_smoke	9.000s	658.302us	50	50	100.00
		aes_config_error	28.000s	1.432ms	50	50	100.00
		aes_stress	12.000s	320.961us	50	50	100.00
V2	back2back	aes_stress	12.000s	320.961us	50	50	100.00
		aes_b2b	30.000s	582.559us	50	50	100.00
V2	backpressure	aes_stress	12.000s	320.961us	50	50	100.00
V2	multi_message	aes_smoke	9.000s	658.302us	50	50	100.00
		aes_config_error	28.000s	1.432ms	50	50	100.00
		aes_stress	12.000s	320.961us	50	50	100.00
		aes_alert_reset	59.000s	4.533ms	47	50	94.00
V2	failure_test	aes_man_cfg_err	9.000s	132.788us	50	50	100.00
		aes_config_error	28.000s	1.432ms	50	50	100.00
		aes_alert_reset	59.000s	4.533ms	47	50	94.00
V2	trigger_clear_test	aes_clear	18.000s	710.158us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	15.000s	3.355ms	1	1	100.00
V2	reset_recovery	aes_alert_reset	59.000s	4.533ms	47	50	94.00
V2	stress	aes_stress	12.000s	320.961us	50	50	100.00
V2	sideload	aes_stress	12.000s	320.961us	50	50	100.00
		aes_sideload	1.383m	4.492ms	50	50	100.00
V2	deinitialization	aes_deinit	9.000s	176.522us	50	50	100.00
V2	stress_all	aes_stress_all	1.733m	21.793ms	9	10	90.00
V2	alert_test	aes_alert_test	8.000s	89.481us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	9.000s	223.354us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	9.000s	223.354us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	7.000s	78.213us	5	5	100.00
		aes_csr_rw	7.000s	65.378us	20	20	100.00
		aes_csr_aliasing	9.000s	516.858us	5	5	100.00
		aes_same_csr_outstanding	7.000s	283.531us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	7.000s	78.213us	5	5	100.00
		aes_csr_rw	7.000s	65.378us	20	20	100.00
		aes_csr_aliasing	9.000s	516.858us	5	5	100.00
		aes_same_csr_outstanding	7.000s	283.531us	20	20	100.00
V2		TOTAL			497	501	99.20
V2S	reseeding	aes_reseed	13.000s	345.431us	50	50	100.00
V2S	fault_inject	aes_fi	16.000s	655.306us	46	50	92.00
		aes_control_fi	58.000s	10.154ms	277	300	92.33
		aes_cipher_fi	55.000s	10.006ms	341	350	97.43
V2S	shadow_reg_update_error	aes_shadow_reg_errors	9.000s	132.496us	8	20	40.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	9.000s	132.496us	8	20	40.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	9.000s	132.496us	8	20	40.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	9.000s	132.496us	8	20	40.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	19.000s	1.954ms	13	20	65.00
V2S	tl_intg_err	aes_sec_cm	28.000s	1.309ms	5	5	100.00
		aes_tl_intg_err	12.000s	302.512us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	12.000s	302.512us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	59.000s	4.533ms	47	50	94.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	9.000s	132.496us	8	20	40.00
V2S	sec_cm_main_config_sparse	aes_smoke	9.000s	658.302us	50	50	100.00
		aes_stress	12.000s	320.961us	50	50	100.00
		aes_alert_reset	59.000s	4.533ms	47	50	94.00
		aes_core_fi	38.000s	10.003ms	68	70	97.14
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	9.000s	132.496us	8	20	40.00
V2S	sec_cm_aux_config_regwen	aes_readability	10.000s	334.354us	50	50	100.00
		aes_stress	12.000s	320.961us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	12.000s	320.961us	50	50	100.00
		aes_sideload	1.383m	4.492ms	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	10.000s	334.354us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	10.000s	334.354us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	10.000s	334.354us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	10.000s	334.354us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	10.000s	334.354us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	12.000s	320.961us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	12.000s	320.961us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	16.000s	655.306us	46	50	92.00
V2S	sec_cm_main_fsm_redun	aes_fi	16.000s	655.306us	46	50	92.00
		aes_control_fi	58.000s	10.154ms	277	300	92.33
		aes_cipher_fi	55.000s	10.006ms	341	350	97.43
		aes_ctr_fi	9.000s	304.773us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	16.000s	655.306us	46	50	92.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	16.000s	655.306us	46	50	92.00
		aes_control_fi	58.000s	10.154ms	277	300	92.33
		aes_cipher_fi	55.000s	10.006ms	341	350	97.43
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	55.000s	10.006ms	341	350	97.43
V2S	sec_cm_ctr_fsm_sparse	aes_fi	16.000s	655.306us	46	50	92.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	16.000s	655.306us	46	50	92.00
		aes_control_fi	58.000s	10.154ms	277	300	92.33
		aes_ctr_fi	9.000s	304.773us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	16.000s	655.306us	46	50	92.00
		aes_control_fi	58.000s	10.154ms	277	300	92.33
		aes_cipher_fi	55.000s	10.006ms	341	350	97.43
		aes_ctr_fi	9.000s	304.773us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	59.000s	4.533ms	47	50	94.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	16.000s	655.306us	46	50	92.00
		aes_control_fi	58.000s	10.154ms	277	300	92.33
		aes_cipher_fi	55.000s	10.006ms	341	350	97.43
		aes_ctr_fi	9.000s	304.773us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	16.000s	655.306us	46	50	92.00
		aes_control_fi	58.000s	10.154ms	277	300	92.33
		aes_cipher_fi	55.000s	10.006ms	341	350	97.43
		aes_ctr_fi	9.000s	304.773us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	16.000s	655.306us	46	50	92.00
		aes_control_fi	58.000s	10.154ms	277	300	92.33
		aes_ctr_fi	9.000s	304.773us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	16.000s	655.306us	46	50	92.00
		aes_control_fi	58.000s	10.154ms	277	300	92.33
		aes_cipher_fi	55.000s	10.006ms	341	350	97.43
V2S		TOTAL			928	985	94.21
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	53.000s	12.296ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1531	1602	95.57

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.36	98.54	96.30	99.42	95.71	97.99	97.78	99.11	98.20

Failure Buckets

UVM_FATAL (alert_receiver_driver.sv:146) [driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q has 28 failures:

Test aes_shadow_reg_errors_with_csr_rw has 7 failures.

0.aes_shadow_reg_errors_with_csr_rw.14708426751890466535513194086888619127770398363464943291871302832072462020738
Line 104, in log /nightly/runs/opentitan/scratch/master/aes_masked-sim-xcelium/0.aes_shadow_reg_errors_with_csr_rw/latest/run.log

  UVM_FATAL @ 400193359 ps: (alert_receiver_driver.sv:146) [uvm_test_top.env.m_alert_agent_fatal_fault.driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q
  UVM_INFO @ 400193359 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.aes_shadow_reg_errors_with_csr_rw.101053383912394969763205722245113329167309477440715740684427996955024784632658
Line 103, in log /nightly/runs/opentitan/scratch/master/aes_masked-sim-xcelium/4.aes_shadow_reg_errors_with_csr_rw/latest/run.log

  UVM_FATAL @  25260679 ps: (alert_receiver_driver.sv:146) [uvm_test_top.env.m_alert_agent_fatal_fault.driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q
  UVM_INFO @  25260679 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

Test aes_shadow_reg_errors has 12 failures.

1.aes_shadow_reg_errors.98977395797012655871300288209376276316126858920538958793968900823932705420554
Line 103, in log /nightly/runs/opentitan/scratch/master/aes_masked-sim-xcelium/1.aes_shadow_reg_errors/latest/run.log

  UVM_FATAL @  31799793 ps: (alert_receiver_driver.sv:146) [uvm_test_top.env.m_alert_agent_fatal_fault.driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q
  UVM_INFO @  31799793 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.aes_shadow_reg_errors.50475603679754176307796590666867487139703099553265967455949848872534726099293
Line 103, in log /nightly/runs/opentitan/scratch/master/aes_masked-sim-xcelium/2.aes_shadow_reg_errors/latest/run.log

  UVM_FATAL @  19505348 ps: (alert_receiver_driver.sv:146) [uvm_test_top.env.m_alert_agent_fatal_fault.driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q
  UVM_INFO @  19505348 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 10 more failures.

Test aes_stress_all has 1 failures.

2.aes_stress_all.63311144468624235134129182380211255594078180464940251902310343983217707894533
Line 42277, in log /nightly/runs/opentitan/scratch/master/aes_masked-sim-xcelium/2.aes_stress_all/latest/run.log

  UVM_FATAL @ 539708435 ps: (alert_receiver_driver.sv:146) [uvm_test_top.env.m_alert_agent_fatal_fault.driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q
  UVM_INFO @ 539708435 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test aes_stress_all_with_rand_reset has 1 failures.

4.aes_stress_all_with_rand_reset.37128308278616223102074545907337326831894078876505849580176731245977503360531
Line 148, in log /nightly/runs/opentitan/scratch/master/aes_masked-sim-xcelium/4.aes_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @  31307000 ps: (alert_receiver_driver.sv:146) [uvm_test_top.env.m_alert_agent_fatal_fault.driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q
  UVM_INFO @  31307000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test aes_alert_reset has 3 failures.

5.aes_alert_reset.20059954601345598293685247017326893848466900228370216442041651297539308022916
Line 1034, in log /nightly/runs/opentitan/scratch/master/aes_masked-sim-xcelium/5.aes_alert_reset/latest/run.log

  UVM_FATAL @  99221242 ps: (alert_receiver_driver.sv:146) [uvm_test_top.env.m_alert_agent_fatal_fault.driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q
  UVM_INFO @  99221242 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

10.aes_alert_reset.16642116491949435271387125633692014989716789219092376316564901479487253571711
Line 2460, in log /nightly/runs/opentitan/scratch/master/aes_masked-sim-xcelium/10.aes_alert_reset/latest/run.log

  UVM_FATAL @   9373180 ps: (alert_receiver_driver.sv:146) [uvm_test_top.env.m_alert_agent_fatal_fault.driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q
  UVM_INFO @   9373180 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

... and 2 more tests.

UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 15 failures:
- Test aes_control_fi has 15 failures.
  - 9.aes_control_fi.54574443964042898337086428497564025174105209712187288151178235159176524858108
    Line 134, in log /nightly/runs/opentitan/scratch/master/aes_masked-sim-xcelium/9.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10013871215 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10013871215 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 11.aes_control_fi.115146630637851194157625527892551200553384858508622903124679695154029801103188
    Line 143, in log /nightly/runs/opentitan/scratch/master/aes_masked-sim-xcelium/11.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10004112013 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10004112013 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 13 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 9 failures:
- Test aes_cipher_fi has 9 failures.
  - 8.aes_cipher_fi.45049044460648500057558759471178037753150778754463617322197180532192020702717
    Line 141, in log /nightly/runs/opentitan/scratch/master/aes_masked-sim-xcelium/8.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10002735471 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10002735471 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 22.aes_cipher_fi.62537716355735607212544188763528273743054451828714841041824198205722160757376
    Line 142, in log /nightly/runs/opentitan/scratch/master/aes_masked-sim-xcelium/22.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10096847484 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10096847484 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 7 more failures.
Job timed out after * minutes has 8 failures:
- Test aes_control_fi has 8 failures.
  - 7.aes_control_fi.77437982486014515962880425103814454904309236496851558141806180033183629483531
    Log /nightly/runs/opentitan/scratch/master/aes_masked-sim-xcelium/7.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 22.aes_control_fi.98693260576269378318776030209746997663114037102620623191505427903593957839812
    Log /nightly/runs/opentitan/scratch/master/aes_masked-sim-xcelium/22.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 6 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 7 failures:

Test aes_stress_all_with_rand_reset has 7 failures.

0.aes_stress_all_with_rand_reset.60254816045649383522243901037723312889039965784121798783330491782478047637593
Line 258, in log /nightly/runs/opentitan/scratch/master/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 356047716 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 356047716 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.aes_stress_all_with_rand_reset.27624422286886151590408347274116355461287794782582745469776788540510923703589
Line 919, in log /nightly/runs/opentitan/scratch/master/aes_masked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 3320040893 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 3320040893 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

UVM_ERROR (cip_base_vseq.sv:891) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 3.aes_stress_all_with_rand_reset.6774063029056904127489845046729851865374952213838634283788147744365576391746
    Line 596, in log /nightly/runs/opentitan/scratch/master/aes_masked-sim-xcelium/3.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 881937360 ps: (cip_base_vseq.sv:891) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 881937360 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_base_vseq.sv:74) [aes_reseed_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 6.aes_stress_all_with_rand_reset.109564520595744348200451584659835845548630440605183442340777043483276558099070
    Line 1565, in log /nightly/runs/opentitan/scratch/master/aes_masked-sim-xcelium/6.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 12295617409 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 12295617409 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

xmsim: *E,ASRTST (/nightly/runs/opentitan/scratch/master/aes_masked-sim-xcelium/default/src/lowrisc_ip_aes_*/rtl/aes_core.sv,993): Assertion AesSecCmDataRegLocalEscIv has failed (* cycles, starting * PS) has 1 failures:

Test aes_fi has 1 failures.

36.aes_fi.40783614094087701036777798415924064603359172038190462221440914107092668791141
Line 1454, in log /nightly/runs/opentitan/scratch/master/aes_masked-sim-xcelium/36.aes_fi/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/opentitan/scratch/master/aes_masked-sim-xcelium/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,993): (time 7680983 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscIv has failed (2 cycles, starting 7670983 PS)
  UVM_ERROR @   7680983 ps: (aes_core.sv:993) [ASSERT FAILED] AesSecCmDataRegLocalEscIv
  UVM_INFO @   7680983 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 1 failures:
- Test aes_core_fi has 1 failures.
  - 64.aes_core_fi.65185811581620874343947891901963987129121347615200382600580634725669738079886
    Line 142, in log /nightly/runs/opentitan/scratch/master/aes_masked-sim-xcelium/64.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10003471978 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10003471978 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```