AES/UNMASKED Simulation Results

Friday January 24 2025 17:10:00 UTC

GitHub Revision: `002bb67a7c`

Branch: master

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	6.000s	66.481us	1	1	100.00
V1	smoke	aes_smoke	8.000s	114.756us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	7.000s	198.343us	5	5	100.00
V1	csr_rw	aes_csr_rw	7.000s	54.635us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	14.000s	4.577ms	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	7.000s	96.124us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	7.000s	67.087us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	7.000s	54.635us	20	20	100.00
		aes_csr_aliasing	7.000s	96.124us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	8.000s	114.756us	50	50	100.00
		aes_config_error	13.000s	557.634us	50	50	100.00
		aes_stress	8.000s	226.427us	50	50	100.00
V2	key_length	aes_smoke	8.000s	114.756us	50	50	100.00
		aes_config_error	13.000s	557.634us	50	50	100.00
		aes_stress	8.000s	226.427us	50	50	100.00
V2	back2back	aes_stress	8.000s	226.427us	50	50	100.00
		aes_b2b	10.000s	361.318us	50	50	100.00
V2	backpressure	aes_stress	8.000s	226.427us	50	50	100.00
V2	multi_message	aes_smoke	8.000s	114.756us	50	50	100.00
		aes_config_error	13.000s	557.634us	50	50	100.00
		aes_stress	8.000s	226.427us	50	50	100.00
		aes_alert_reset	9.000s	361.946us	49	50	98.00
V2	failure_test	aes_man_cfg_err	7.000s	101.322us	50	50	100.00
		aes_config_error	13.000s	557.634us	50	50	100.00
		aes_alert_reset	9.000s	361.946us	49	50	98.00
V2	trigger_clear_test	aes_clear	8.000s	273.823us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	9.000s	356.399us	1	1	100.00
V2	reset_recovery	aes_alert_reset	9.000s	361.946us	49	50	98.00
V2	stress	aes_stress	8.000s	226.427us	50	50	100.00
V2	sideload	aes_stress	8.000s	226.427us	50	50	100.00
		aes_sideload	8.000s	118.110us	50	50	100.00
V2	deinitialization	aes_deinit	8.000s	97.009us	50	50	100.00
V2	stress_all	aes_stress_all	20.000s	492.079us	9	10	90.00
V2	alert_test	aes_alert_test	8.000s	54.768us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	8.000s	169.942us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	8.000s	169.942us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	7.000s	198.343us	5	5	100.00
		aes_csr_rw	7.000s	54.635us	20	20	100.00
		aes_csr_aliasing	7.000s	96.124us	5	5	100.00
		aes_same_csr_outstanding	7.000s	90.745us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	7.000s	198.343us	5	5	100.00
		aes_csr_rw	7.000s	54.635us	20	20	100.00
		aes_csr_aliasing	7.000s	96.124us	5	5	100.00
		aes_same_csr_outstanding	7.000s	90.745us	20	20	100.00
V2		TOTAL			499	501	99.60
V2S	reseeding	aes_reseed	9.000s	318.755us	50	50	100.00
V2S	fault_inject	aes_fi	9.000s	269.326us	47	50	94.00
		aes_control_fi	38.000s	10.002ms	282	300	94.00
		aes_cipher_fi	32.000s	10.003ms	323	350	92.29
V2S	shadow_reg_update_error	aes_shadow_reg_errors	9.000s	257.271us	13	20	65.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	9.000s	257.271us	13	20	65.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	9.000s	257.271us	13	20	65.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	9.000s	257.271us	13	20	65.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	9.000s	159.154us	17	20	85.00
V2S	tl_intg_err	aes_sec_cm	26.000s	681.482us	5	5	100.00
		aes_tl_intg_err	32.000s	1.214ms	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	32.000s	1.214ms	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	9.000s	361.946us	49	50	98.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	9.000s	257.271us	13	20	65.00
V2S	sec_cm_main_config_sparse	aes_smoke	8.000s	114.756us	50	50	100.00
		aes_stress	8.000s	226.427us	50	50	100.00
		aes_alert_reset	9.000s	361.946us	49	50	98.00
		aes_core_fi	12.600m	10.107ms	67	70	95.71
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	9.000s	257.271us	13	20	65.00
V2S	sec_cm_aux_config_regwen	aes_readability	8.000s	62.588us	50	50	100.00
		aes_stress	8.000s	226.427us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	8.000s	226.427us	50	50	100.00
		aes_sideload	8.000s	118.110us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	8.000s	62.588us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	8.000s	62.588us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	8.000s	62.588us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	8.000s	62.588us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	8.000s	62.588us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	8.000s	226.427us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	8.000s	226.427us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	9.000s	269.326us	47	50	94.00
V2S	sec_cm_main_fsm_redun	aes_fi	9.000s	269.326us	47	50	94.00
		aes_control_fi	38.000s	10.002ms	282	300	94.00
		aes_cipher_fi	32.000s	10.003ms	323	350	92.29
		aes_ctr_fi	8.000s	74.620us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	9.000s	269.326us	47	50	94.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	9.000s	269.326us	47	50	94.00
		aes_control_fi	38.000s	10.002ms	282	300	94.00
		aes_cipher_fi	32.000s	10.003ms	323	350	92.29
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	32.000s	10.003ms	323	350	92.29
V2S	sec_cm_ctr_fsm_sparse	aes_fi	9.000s	269.326us	47	50	94.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	9.000s	269.326us	47	50	94.00
		aes_control_fi	38.000s	10.002ms	282	300	94.00
		aes_ctr_fi	8.000s	74.620us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	9.000s	269.326us	47	50	94.00
		aes_control_fi	38.000s	10.002ms	282	300	94.00
		aes_cipher_fi	32.000s	10.003ms	323	350	92.29
		aes_ctr_fi	8.000s	74.620us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	9.000s	361.946us	49	50	98.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	9.000s	269.326us	47	50	94.00
		aes_control_fi	38.000s	10.002ms	282	300	94.00
		aes_cipher_fi	32.000s	10.003ms	323	350	92.29
		aes_ctr_fi	8.000s	74.620us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	9.000s	269.326us	47	50	94.00
		aes_control_fi	38.000s	10.002ms	282	300	94.00
		aes_cipher_fi	32.000s	10.003ms	323	350	92.29
		aes_ctr_fi	8.000s	74.620us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	9.000s	269.326us	47	50	94.00
		aes_control_fi	38.000s	10.002ms	282	300	94.00
		aes_ctr_fi	8.000s	74.620us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	9.000s	269.326us	47	50	94.00
		aes_control_fi	38.000s	10.002ms	282	300	94.00
		aes_cipher_fi	32.000s	10.003ms	323	350	92.29
V2S		TOTAL			924	985	93.81
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	17.000s	1.849ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1529	1602	95.44

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.13	97.41	94.14	98.71	93.48	97.99	91.11	98.85	97.60

Failure Buckets

Job timed out after * minutes has 25 failures:
- Test aes_control_fi has 12 failures.
  - 0.aes_control_fi.80714904887824972885258187078767754168382989418471865336152368941392088629016
    Log /nightly/runs/opentitan/scratch/master/aes_unmasked-sim-xcelium/0.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 18.aes_control_fi.79462656060676311968504571139218914059996696651245268675280930292747634125344
    Log /nightly/runs/opentitan/scratch/master/aes_unmasked-sim-xcelium/18.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 10 more failures.
- Test aes_cipher_fi has 13 failures.
  - 2.aes_cipher_fi.18963243074025975779294862755846632354821939682265326516316919397859349800103
    Log /nightly/runs/opentitan/scratch/master/aes_unmasked-sim-xcelium/2.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 44.aes_cipher_fi.80926299634459672379666271188481543017036278758495851778390312202563902748597
    Log /nightly/runs/opentitan/scratch/master/aes_unmasked-sim-xcelium/44.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 11 more failures.

UVM_FATAL (alert_receiver_driver.sv:146) [driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q has 14 failures:

Test aes_shadow_reg_errors_with_csr_rw has 3 failures.

2.aes_shadow_reg_errors_with_csr_rw.78873398451607915100618478097045515257253034274318810183116686983718221465632
Line 103, in log /nightly/runs/opentitan/scratch/master/aes_unmasked-sim-xcelium/2.aes_shadow_reg_errors_with_csr_rw/latest/run.log

  UVM_FATAL @ 154968896 ps: (alert_receiver_driver.sv:146) [uvm_test_top.env.m_alert_agent_fatal_fault.driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q
  UVM_INFO @ 154968896 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

15.aes_shadow_reg_errors_with_csr_rw.41682067921998011200080210327067802121596815085039124473950013325212097498001
Line 103, in log /nightly/runs/opentitan/scratch/master/aes_unmasked-sim-xcelium/15.aes_shadow_reg_errors_with_csr_rw/latest/run.log

  UVM_FATAL @  11739212 ps: (alert_receiver_driver.sv:146) [uvm_test_top.env.m_alert_agent_fatal_fault.driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q
  UVM_INFO @  11739212 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test aes_shadow_reg_errors has 7 failures.

5.aes_shadow_reg_errors.55762240491330709465446380303035284543385907020750656654985487757850022812687
Line 103, in log /nightly/runs/opentitan/scratch/master/aes_unmasked-sim-xcelium/5.aes_shadow_reg_errors/latest/run.log

  UVM_FATAL @  10242938 ps: (alert_receiver_driver.sv:146) [uvm_test_top.env.m_alert_agent_fatal_fault.driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q
  UVM_INFO @  10242938 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

10.aes_shadow_reg_errors.77985325817153455907221796393036301233925872514751430201853128770974529674835
Line 103, in log /nightly/runs/opentitan/scratch/master/aes_unmasked-sim-xcelium/10.aes_shadow_reg_errors/latest/run.log

  UVM_FATAL @  13655508 ps: (alert_receiver_driver.sv:146) [uvm_test_top.env.m_alert_agent_fatal_fault.driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q
  UVM_INFO @  13655508 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

Test aes_stress_all_with_rand_reset has 1 failures.

7.aes_stress_all_with_rand_reset.98558017926994618844120557868730764955058049792076017531885930614659982700390
Line 222, in log /nightly/runs/opentitan/scratch/master/aes_unmasked-sim-xcelium/7.aes_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @ 678539101 ps: (alert_receiver_driver.sv:146) [uvm_test_top.env.m_alert_agent_fatal_fault.driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q
  UVM_INFO @ 678539101 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test aes_fi has 2 failures.

12.aes_fi.27147303515502970856752483644346027510094177056578979699986547955690539240307
Line 3482, in log /nightly/runs/opentitan/scratch/master/aes_unmasked-sim-xcelium/12.aes_fi/latest/run.log

  UVM_FATAL @  11780702 ps: (alert_receiver_driver.sv:146) [uvm_test_top.env.m_alert_agent_fatal_fault.driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q
  UVM_INFO @  11780702 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

31.aes_fi.21573626292911501424903720113027942763197659494827404138545056579038349563140
Line 1200, in log /nightly/runs/opentitan/scratch/master/aes_unmasked-sim-xcelium/31.aes_fi/latest/run.log

  UVM_FATAL @  26777436 ps: (alert_receiver_driver.sv:146) [uvm_test_top.env.m_alert_agent_fatal_fault.driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q
  UVM_INFO @  26777436 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test aes_alert_reset has 1 failures.

28.aes_alert_reset.57441750239705194232567575267641410512645931360241970294119824446896752701381
Line 876, in log /nightly/runs/opentitan/scratch/master/aes_unmasked-sim-xcelium/28.aes_alert_reset/latest/run.log

  UVM_FATAL @  28372979 ps: (alert_receiver_driver.sv:146) [uvm_test_top.env.m_alert_agent_fatal_fault.driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q
  UVM_INFO @  28372979 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 14 failures:
- Test aes_cipher_fi has 14 failures.
  - 26.aes_cipher_fi.50937727953162578349200537639651396290488565389989495415790642085401078720456
    Line 139, in log /nightly/runs/opentitan/scratch/master/aes_unmasked-sim-xcelium/26.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10020950356 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10020950356 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 69.aes_cipher_fi.21839439321716901457636775271790624831121538195617800511124378955373324050295
    Line 144, in log /nightly/runs/opentitan/scratch/master/aes_unmasked-sim-xcelium/69.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10009453455 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10009453455 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 12 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 6 failures:
- Test aes_control_fi has 6 failures.
  - 101.aes_control_fi.14540226500285292883442418438325166916053692202862530696340745756720128205637
    Line 145, in log /nightly/runs/opentitan/scratch/master/aes_unmasked-sim-xcelium/101.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10002995071 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10002995071 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 113.aes_control_fi.92538215697888908942244580196762612410060236976649367670315291914255171391339
    Line 137, in log /nightly/runs/opentitan/scratch/master/aes_unmasked-sim-xcelium/113.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10014194289 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10014194289 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 4 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 4 failures:

Test aes_stress_all_with_rand_reset has 4 failures.

1.aes_stress_all_with_rand_reset.90839665350603859980572843367805444934419920347548017197702340771445873240767
Line 189, in log /nightly/runs/opentitan/scratch/master/aes_unmasked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @  52268770 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @  52268770 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.aes_stress_all_with_rand_reset.36634394223333820395570335977510812544403851272145727729444799155412951385554
Line 185, in log /nightly/runs/opentitan/scratch/master/aes_unmasked-sim-xcelium/4.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @  49779346 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @  49779346 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

UVM_ERROR (cip_base_vseq.sv:891) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:
- Test aes_stress_all_with_rand_reset has 2 failures.
  - 0.aes_stress_all_with_rand_reset.7283992156283794578355619086959305661787419627107696995558689528586503219336
    Line 161, in log /nightly/runs/opentitan/scratch/master/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 702244765 ps: (cip_base_vseq.sv:891) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 702244765 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.aes_stress_all_with_rand_reset.12817036442772642541050849569954238907018086853516147480392891239384185299820
    Line 559, in log /nightly/runs/opentitan/scratch/master/aes_unmasked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1848559108 ps: (cip_base_vseq.sv:891) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1848559108 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

xmsim: *E,ASRTST (/nightly/runs/opentitan/scratch/master/aes_unmasked-sim-xcelium/default/src/lowrisc_ip_aes_*/rtl/aes_core.sv,993): Assertion AesSecCmDataRegLocalEscIv has failed (* cycles, starting * PS) has 2 failures:

Test aes_fi has 1 failures.

4.aes_fi.60745776268350223252109956159070861025719891238233197190498313331463587663906
Line 3582, in log /nightly/runs/opentitan/scratch/master/aes_unmasked-sim-xcelium/4.aes_fi/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/opentitan/scratch/master/aes_unmasked-sim-xcelium/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,993): (time 28632816 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscIv has failed (2 cycles, starting 28605789 PS)
  UVM_ERROR @  28632816 ps: (aes_core.sv:993) [ASSERT FAILED] AesSecCmDataRegLocalEscIv
  UVM_INFO @  28632816 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test aes_stress_all has 1 failures.

9.aes_stress_all.25288111743092017516022456804489017482342917725395405495750544251344203502933
Line 3704, in log /nightly/runs/opentitan/scratch/master/aes_unmasked-sim-xcelium/9.aes_stress_all/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/opentitan/scratch/master/aes_unmasked-sim-xcelium/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,993): (time 94735477 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscIv has failed (2 cycles, starting 94695477 PS)
  UVM_ERROR @  94735477 ps: (aes_core.sv:993) [ASSERT FAILED] AesSecCmDataRegLocalEscIv
  UVM_INFO @  94735477 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 2 failures:
- Test aes_core_fi has 2 failures.
  - 31.aes_core_fi.4183889047504149337097350519720021487328470659232165469619507883386070752268
    Line 146, in log /nightly/runs/opentitan/scratch/master/aes_unmasked-sim-xcelium/31.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10005711885 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10005711885 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 69.aes_core_fi.6479595356723015864704331981248846714994999828260087316568347019100119319626
    Line 131, in log /nightly/runs/opentitan/scratch/master/aes_unmasked-sim-xcelium/69.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10008487179 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10008487179 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:580) [aes_alert_reset_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_fault fired unexpectedly! has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 3.aes_stress_all_with_rand_reset.110771878058322337734862991778119966745246222873700145834116975454321267003380
    Line 207, in log /nightly/runs/opentitan/scratch/master/aes_unmasked-sim-xcelium/3.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @  35942426 ps: (cip_base_vseq.sv:580) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_fault fired unexpectedly!
  UVM_INFO @  35942426 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_base_vseq.sv:74) [aes_reseed_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 5.aes_stress_all_with_rand_reset.27924973172926534418336630545904707588220376275949799899152190482413609149051
    Line 478, in log /nightly/runs/opentitan/scratch/master/aes_unmasked-sim-xcelium/5.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 942286197 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 942286197 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_base_vseq.sv:74) [aes_stress_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 6.aes_stress_all_with_rand_reset.64905394730773790869928775089699109979641485550104745394307260650360458373117
    Line 132, in log /nightly/runs/opentitan/scratch/master/aes_unmasked-sim-xcelium/6.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @  11827022 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_stress_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @  11827022 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_core_fi_vseq.sv:89) [aes_core_fi_vseq] wait timeout occurred! has 1 failures:
- Test aes_core_fi has 1 failures.
  - 38.aes_core_fi.17787105659755554765480630987620285496473589832929739471575572579115320456718
    Line 133, in log /nightly/runs/opentitan/scratch/master/aes_unmasked-sim-xcelium/38.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10107200850 ps: (aes_core_fi_vseq.sv:89) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10107200850 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```