AON_TIMER Simulation Results

Friday January 24 2025 17:10:00 UTC

GitHub Revision: `002bb67a7c`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	aon_timer_smoke	3.050s	593.094us	50	50	100.00
V1	csr_hw_reset	aon_timer_csr_hw_reset	2.710s	1.038ms	5	5	100.00
V1	csr_rw	aon_timer_csr_rw	2.510s	451.795us	20	20	100.00
V1	csr_bit_bash	aon_timer_csr_bit_bash	13.460s	6.881ms	5	5	100.00
V1	csr_aliasing	aon_timer_csr_aliasing	2.370s	580.752us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aon_timer_csr_mem_rw_with_rand_reset	2.440s	364.270us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aon_timer_csr_rw	2.510s	451.795us	20	20	100.00
		aon_timer_csr_aliasing	2.370s	580.752us	5	5	100.00
V1	mem_walk	aon_timer_mem_walk	2.370s	389.554us	5	5	100.00
V1	mem_partial_access	aon_timer_mem_partial_access	1.980s	533.458us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	prescaler	aon_timer_prescaler	51.220s	43.715ms	50	50	100.00
V2	jump	aon_timer_jump	2.830s	368.947us	50	50	100.00
V2	stress_all	aon_timer_stress_all	7.089m	475.800ms	49	50	98.00
V2	intr_test	aon_timer_intr_test	2.570s	497.198us	50	50	100.00
V2	tl_d_oob_addr_access	aon_timer_tl_errors	3.250s	787.103us	20	20	100.00
V2	tl_d_illegal_access	aon_timer_tl_errors	3.250s	787.103us	20	20	100.00
V2	tl_d_outstanding_access	aon_timer_csr_hw_reset	2.710s	1.038ms	5	5	100.00
		aon_timer_csr_rw	2.510s	451.795us	20	20	100.00
		aon_timer_csr_aliasing	2.370s	580.752us	5	5	100.00
		aon_timer_same_csr_outstanding	5.590s	1.957ms	20	20	100.00
V2	tl_d_partial_access	aon_timer_csr_hw_reset	2.710s	1.038ms	5	5	100.00
		aon_timer_csr_rw	2.510s	451.795us	20	20	100.00
		aon_timer_csr_aliasing	2.370s	580.752us	5	5	100.00
		aon_timer_same_csr_outstanding	5.590s	1.957ms	20	20	100.00
V2		TOTAL			239	240	99.58
V2S	tl_intg_err	aon_timer_sec_cm	11.170s	8.558ms	5	5	100.00
		aon_timer_tl_intg_err	3.560m	17.115ms	19	20	95.00
V2S	sec_cm_bus_integrity	aon_timer_tl_intg_err	3.560m	17.115ms	19	20	95.00
V2S		TOTAL			24	25	96.00
V3	stress_all_with_rand_reset	aon_timer_stress_all_with_rand_reset	41.650s	43.934ms	48	50	96.00
V3		TOTAL			48	50	96.00
	Unmapped tests	aon_timer_alert_test	3.110s	323.159us	50	50	100.00
		TOTAL			476	480	99.17

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.99	99.32	95.93	100.00	--	98.39	99.51	94.78

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:492) [aon_timer_common_vseq] Check failed exp_val == act_val (* [*] vs * [*]) when reading the intr CSR aon_timer_reg_block.intr_state has 3 failures:

Test aon_timer_stress_all_with_rand_reset has 2 failures.

4.aon_timer_stress_all_with_rand_reset.7776746409746445112293695791476257451619841961484965188185578338744990656898
Line 225, in log /nightly/runs/opentitan/scratch/master/aon_timer-sim-vcs/4.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 660398042 ps: (cip_base_vseq.sv:492) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (2 [0x2] vs 3 [0x3]) when reading the intr CSR aon_timer_reg_block.intr_state
  UVM_INFO @ 660398042 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

42.aon_timer_stress_all_with_rand_reset.69817241371517199121336525453084781444263862783590433232285478105868953829180
Line 242, in log /nightly/runs/opentitan/scratch/master/aon_timer-sim-vcs/42.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 967395069 ps: (cip_base_vseq.sv:492) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 1 [0x1]) when reading the intr CSR aon_timer_reg_block.intr_state
  UVM_INFO @ 967395069 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test aon_timer_stress_all has 1 failures.

47.aon_timer_stress_all.110242867302598949410222684285970940329118667054850544351411385043015375862377
Line 267, in log /nightly/runs/opentitan/scratch/master/aon_timer-sim-vcs/47.aon_timer_stress_all/latest/run.log

  UVM_ERROR @ 154754097915 ps: (cip_base_vseq.sv:492) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 3 [0x3]) when reading the intr CSR aon_timer_reg_block.intr_state
  UVM_INFO @ 154754097915 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (cip_base_vseq.sv:665) [aon_timer_common_vseq] timeout wait for alert handshake:fatal_fault has 1 failures:
- Test aon_timer_tl_intg_err has 1 failures.
  - 4.aon_timer_tl_intg_err.14996306272345809815276649402420959638703754445413388355517961386322263201700
    Line 330, in log /nightly/runs/opentitan/scratch/master/aon_timer-sim-vcs/4.aon_timer_tl_intg_err/latest/run.log
```
  UVM_FATAL @ 17114906221 ps: (cip_base_vseq.sv:665) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] timeout wait for alert handshake:fatal_fault
  UVM_INFO @ 17114906221 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```