CSRNG Simulation Results

Friday January 24 2025 17:10:00 UTC

GitHub Revision: `002bb67a7c`

Branch: master

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	14.000s	37.772us	50	50	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	21.000s	12.338us	5	5	100.00
V1	csr_rw	csrng_csr_rw	21.000s	37.062us	20	20	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	40.000s	1.408ms	5	5	100.00
V1	csr_aliasing	csrng_csr_aliasing	22.000s	101.344us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	21.000s	65.762us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	21.000s	37.062us	20	20	100.00
		csrng_csr_aliasing	22.000s	101.344us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	interrupts	csrng_intr	23.000s	1.955ms	200	200	100.00
V2	alerts	csrng_alert	16.767m	10.618ms	499	500	99.80
V2	err	csrng_err	15.000s	115.353us	499	500	99.80
V2	cmds	csrng_cmds	10.800m	69.820ms	50	50	100.00
V2	life cycle	csrng_cmds	10.800m	69.820ms	50	50	100.00
V2	stress_all	csrng_stress_all	27.933m	157.299ms	50	50	100.00
V2	intr_test	csrng_intr_test	20.000s	11.989us	50	50	100.00
V2	alert_test	csrng_alert_test	13.000s	48.933us	50	50	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	25.000s	2.092ms	20	20	100.00
V2	tl_d_illegal_access	csrng_tl_errors	25.000s	2.092ms	20	20	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	21.000s	12.338us	5	5	100.00
		csrng_csr_rw	21.000s	37.062us	20	20	100.00
		csrng_csr_aliasing	22.000s	101.344us	5	5	100.00
		csrng_same_csr_outstanding	22.000s	106.614us	20	20	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	21.000s	12.338us	5	5	100.00
		csrng_csr_rw	21.000s	37.062us	20	20	100.00
		csrng_csr_aliasing	22.000s	101.344us	5	5	100.00
		csrng_same_csr_outstanding	22.000s	106.614us	20	20	100.00
V2		TOTAL			1438	1440	99.86
V2S	tl_intg_err	csrng_sec_cm	20.000s	247.302us	5	5	100.00
		csrng_tl_intg_err	36.000s	487.949us	20	20	100.00
V2S	sec_cm_config_regwen	csrng_regwen	13.000s	32.972us	50	50	100.00
		csrng_csr_rw	21.000s	37.062us	20	20	100.00
V2S	sec_cm_config_mubi	csrng_alert	16.767m	10.618ms	499	500	99.80
V2S	sec_cm_intersig_mubi	csrng_stress_all	27.933m	157.299ms	50	50	100.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	23.000s	1.955ms	200	200	100.00
		csrng_err	15.000s	115.353us	499	500	99.80
		csrng_sec_cm	20.000s	247.302us	5	5	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	23.000s	1.955ms	200	200	100.00
		csrng_err	15.000s	115.353us	499	500	99.80
		csrng_sec_cm	20.000s	247.302us	5	5	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	23.000s	1.955ms	200	200	100.00
		csrng_err	15.000s	115.353us	499	500	99.80
		csrng_sec_cm	20.000s	247.302us	5	5	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	23.000s	1.955ms	200	200	100.00
		csrng_err	15.000s	115.353us	499	500	99.80
		csrng_sec_cm	20.000s	247.302us	5	5	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	23.000s	1.955ms	200	200	100.00
		csrng_err	15.000s	115.353us	499	500	99.80
		csrng_sec_cm	20.000s	247.302us	5	5	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	23.000s	1.955ms	200	200	100.00
		csrng_err	15.000s	115.353us	499	500	99.80
		csrng_sec_cm	20.000s	247.302us	5	5	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	23.000s	1.955ms	200	200	100.00
		csrng_err	15.000s	115.353us	499	500	99.80
		csrng_sec_cm	20.000s	247.302us	5	5	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	16.767m	10.618ms	499	500	99.80
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	23.000s	1.955ms	200	200	100.00
		csrng_err	15.000s	115.353us	499	500	99.80
V2S	sec_cm_constants_lc_gated	csrng_stress_all	27.933m	157.299ms	50	50	100.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	16.767m	10.618ms	499	500	99.80
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	36.000s	487.949us	20	20	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	23.000s	1.955ms	200	200	100.00
		csrng_err	15.000s	115.353us	499	500	99.80
		csrng_sec_cm	20.000s	247.302us	5	5	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	23.000s	1.955ms	200	200	100.00
		csrng_err	15.000s	115.353us	499	500	99.80
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	23.000s	1.955ms	200	200	100.00
		csrng_err	15.000s	115.353us	499	500	99.80
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	23.000s	1.955ms	200	200	100.00
		csrng_err	15.000s	115.353us	499	500	99.80
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	23.000s	1.955ms	200	200	100.00
		csrng_err	15.000s	115.353us	499	500	99.80
		csrng_sec_cm	20.000s	247.302us	5	5	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	23.000s	1.955ms	200	200	100.00
		csrng_err	15.000s	115.353us	499	500	99.80
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	1.800m	7.692ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1618	1630	99.26

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.69	98.55	96.50	99.88	97.48	92.02	100.00	96.99	90.76

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:891) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 8 failures:
- Test csrng_stress_all_with_rand_reset has 8 failures.
  - 0.csrng_stress_all_with_rand_reset.16277335932936735020741572197787720447004303407172929515470195692005210706477
    Line 102, in log /nightly/runs/opentitan/scratch/master/csrng-sim-xcelium/0.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1728853795 ps: (cip_base_vseq.sv:891) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1728853795 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.csrng_stress_all_with_rand_reset.24166732440759858270866222531038124470542737731709546307298828988760516003395
    Line 100, in log /nightly/runs/opentitan/scratch/master/csrng-sim-xcelium/1.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 212996571 ps: (cip_base_vseq.sv:891) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 212996571 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 6 more failures.

UVM_FATAL sequencer [SEQ_NOT_DONE] Sequence m_edn_push_seq[*] already started has 2 failures:

Test csrng_stress_all_with_rand_reset has 2 failures.

2.csrng_stress_all_with_rand_reset.53898196175081400231979596017179362388194964934166722989902922329147237784161
Line 123, in log /nightly/runs/opentitan/scratch/master/csrng-sim-xcelium/2.csrng_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @  74181670 ps: uvm_test_top.env.m_edn_agent[0].m_cmd_push_agent.sequencer [SEQ_NOT_DONE] Sequence uvm_test_top.env.m_edn_agent[0].m_cmd_push_agent.sequencer.m_edn_push_seq[0] already started
  UVM_INFO @  74181670 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

9.csrng_stress_all_with_rand_reset.20934549202960336160998353466274049118142407189118401261184610025864844055220
Line 120, in log /nightly/runs/opentitan/scratch/master/csrng-sim-xcelium/9.csrng_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @   6410009 ps: uvm_test_top.env.m_edn_agent[0].m_cmd_push_agent.sequencer [SEQ_NOT_DONE] Sequence uvm_test_top.env.m_edn_agent[0].m_cmd_push_agent.sequencer.m_edn_push_seq[0] already started
  UVM_INFO @   6410009 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (csr_utils_pkg.sv:468) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: csrng_reg_block.err_code.cmd_gen_cnt_err reset value: * has 1 failures:
- Test csrng_err has 1 failures.
  - 122.csrng_err.71135218984246903944918805786956560510174300065915890286640400338290429588148
    Line 134, in log /nightly/runs/opentitan/scratch/master/csrng-sim-xcelium/122.csrng_err/latest/run.log
```
  UVM_ERROR @  16060815 ps: (csr_utils_pkg.sv:468) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: csrng_reg_block.err_code.cmd_gen_cnt_err reset value: 0x0
  UVM_INFO @  16060815 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (cip_base_vseq.sv:573) [csrng_alert_vseq] timeout occurred! has 1 failures:
- Test csrng_alert has 1 failures.
  - 482.csrng_alert.43597800640587115231369892458553417098950333757327941813550898096116919794536
    Line 128, in log /nightly/runs/opentitan/scratch/master/csrng-sim-xcelium/482.csrng_alert/latest/run.log
```
  UVM_FATAL @ 10618121314 ps: (cip_base_vseq.sv:573) [uvm_test_top.env.virtual_sequencer.csrng_alert_vseq] timeout occurred!
  UVM_INFO @ 10618121314 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```