EDN Simulation Results

Friday January 24 2025 17:10:00 UTC

GitHub Revision: 002bb67a7c

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke edn_smoke 2.160s 45.082us 50 50 100.00
V1 csr_hw_reset edn_csr_hw_reset 1.940s 91.406us 5 5 100.00
V1 csr_rw edn_csr_rw 1.960s 84.268us 20 20 100.00
V1 csr_bit_bash edn_csr_bit_bash 5.750s 2.446ms 5 5 100.00
V1 csr_aliasing edn_csr_aliasing 2.270s 150.961us 5 5 100.00
V1 csr_mem_rw_with_rand_reset edn_csr_mem_rw_with_rand_reset 2.270s 40.586us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr edn_csr_rw 1.960s 84.268us 20 20 100.00
edn_csr_aliasing 2.270s 150.961us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 firmware edn_genbits 1.971m 14.661ms 300 300 100.00
V2 csrng_commands edn_genbits 1.971m 14.661ms 300 300 100.00
V2 genbits edn_genbits 1.971m 14.661ms 300 300 100.00
V2 interrupts edn_intr 2.990s 21.893us 50 50 100.00
V2 alerts edn_alert 2.770s 313.065us 200 200 100.00
V2 errs edn_err 3.120s 150.992us 100 100 100.00
V2 disable edn_disable 2.190s 31.468us 50 50 100.00
edn_disable_auto_req_mode 2.470s 43.025us 50 50 100.00
V2 stress_all edn_stress_all 6.350s 407.426us 50 50 100.00
V2 intr_test edn_intr_test 2.020s 62.421us 50 50 100.00
V2 alert_test edn_alert_test 2.160s 12.144us 50 50 100.00
V2 tl_d_oob_addr_access edn_tl_errors 4.330s 142.363us 20 20 100.00
V2 tl_d_illegal_access edn_tl_errors 4.330s 142.363us 20 20 100.00
V2 tl_d_outstanding_access edn_csr_hw_reset 1.940s 91.406us 5 5 100.00
edn_csr_rw 1.960s 84.268us 20 20 100.00
edn_csr_aliasing 2.270s 150.961us 5 5 100.00
edn_same_csr_outstanding 2.770s 124.108us 20 20 100.00
V2 tl_d_partial_access edn_csr_hw_reset 1.940s 91.406us 5 5 100.00
edn_csr_rw 1.960s 84.268us 20 20 100.00
edn_csr_aliasing 2.270s 150.961us 5 5 100.00
edn_same_csr_outstanding 2.770s 124.108us 20 20 100.00
V2 TOTAL 940 940 100.00
V2S tl_intg_err edn_sec_cm 31.520s 1.517ms 5 5 100.00
edn_tl_intg_err 7.490s 297.288us 20 20 100.00
V2S sec_cm_config_regwen edn_regwen 1.970s 20.088us 10 10 100.00
V2S sec_cm_config_mubi edn_alert 2.770s 313.065us 200 200 100.00
V2S sec_cm_main_sm_fsm_sparse edn_sec_cm 31.520s 1.517ms 5 5 100.00
V2S sec_cm_ack_sm_fsm_sparse edn_sec_cm 31.520s 1.517ms 5 5 100.00
V2S sec_cm_fifo_ctr_redun edn_sec_cm 31.520s 1.517ms 5 5 100.00
V2S sec_cm_ctr_redun edn_sec_cm 31.520s 1.517ms 5 5 100.00
V2S sec_cm_main_sm_ctr_local_esc edn_alert 2.770s 313.065us 200 200 100.00
edn_sec_cm 31.520s 1.517ms 5 5 100.00
V2S sec_cm_cs_rdata_bus_consistency edn_alert 2.770s 313.065us 200 200 100.00
V2S sec_cm_tile_link_bus_integrity edn_tl_intg_err 7.490s 297.288us 20 20 100.00
V2S TOTAL 35 35 100.00
V3 stress_all_with_rand_reset edn_stress_all_with_rand_reset 1.964m 40.362ms 29 50 58.00
V3 TOTAL 29 50 58.00
TOTAL 1109 1130 98.14

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
95.54 98.21 94.17 97.02 90.12 96.33 99.78 93.18

Failure Buckets