ENTROPY_SRC Simulation Results

Friday January 24 2025 17:10:00 UTC

GitHub Revision: 002bb67a7c

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke entropy_src_smoke 20.000s 68.503us 50 50 100.00
V1 csr_hw_reset entropy_src_csr_hw_reset 7.000s 158.296us 5 5 100.00
V1 csr_rw entropy_src_csr_rw 6.000s 93.312us 20 20 100.00
V1 csr_bit_bash entropy_src_csr_bit_bash 14.000s 1.944ms 5 5 100.00
V1 csr_aliasing entropy_src_csr_aliasing 9.000s 889.123us 5 5 100.00
V1 csr_mem_rw_with_rand_reset entropy_src_csr_mem_rw_with_rand_reset 6.000s 81.088us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr entropy_src_csr_rw 6.000s 93.312us 20 20 100.00
entropy_src_csr_aliasing 9.000s 889.123us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 firmware entropy_src_smoke 20.000s 68.503us 50 50 100.00
entropy_src_rng 7.183m 20.091ms 200 300 66.67
entropy_src_fw_ov 6.183m 19.052ms 161 300 53.67
V2 firmware_mode entropy_src_fw_ov 6.183m 19.052ms 161 300 53.67
V2 rng_mode entropy_src_rng 7.183m 20.091ms 200 300 66.67
V2 rng_max_rate entropy_src_rng_max_rate 11.833m 20.070ms 191 400 47.75
V2 health_checks entropy_src_rng 7.183m 20.091ms 200 300 66.67
V2 conditioning entropy_src_rng 7.183m 20.091ms 200 300 66.67
V2 interrupts entropy_src_rng 7.183m 20.091ms 200 300 66.67
entropy_src_intr 20.000s 7.276ms 50 50 100.00
V2 alerts entropy_src_rng 7.183m 20.091ms 200 300 66.67
entropy_src_functional_alerts 13.000s 493.146us 50 50 100.00
V2 stress_all entropy_src_stress_all 5.283m 19.235ms 49 50 98.00
V2 functional_errors entropy_src_functional_errors 23.050m 10.012ms 972 1000 97.20
V2 firmware_ov_read_contiguous_data entropy_src_fw_ov_contiguous 27.000s 340.800us 50 50 100.00
V2 intr_test entropy_src_intr_test 6.000s 38.552us 50 50 100.00
V2 alert_test entropy_src_alert_test 7.000s 92.763us 50 50 100.00
V2 tl_d_oob_addr_access entropy_src_tl_errors 8.000s 198.755us 20 20 100.00
V2 tl_d_illegal_access entropy_src_tl_errors 8.000s 198.755us 20 20 100.00
V2 tl_d_outstanding_access entropy_src_csr_hw_reset 7.000s 158.296us 5 5 100.00
entropy_src_csr_rw 6.000s 93.312us 20 20 100.00
entropy_src_csr_aliasing 9.000s 889.123us 5 5 100.00
entropy_src_same_csr_outstanding 7.000s 97.236us 20 20 100.00
V2 tl_d_partial_access entropy_src_csr_hw_reset 7.000s 158.296us 5 5 100.00
entropy_src_csr_rw 6.000s 93.312us 20 20 100.00
entropy_src_csr_aliasing 9.000s 889.123us 5 5 100.00
entropy_src_same_csr_outstanding 7.000s 97.236us 20 20 100.00
V2 TOTAL 1863 2340 79.62
V2S tl_intg_err entropy_src_sec_cm 9.000s 110.014us 5 5 100.00
entropy_src_tl_intg_err 16.000s 209.467us 20 20 100.00
V2S sec_cm_config_regwen entropy_src_rng 7.183m 20.091ms 200 300 66.67
entropy_src_cfg_regwen 9.000s 38.114us 50 50 100.00
V2S sec_cm_config_mubi entropy_src_rng 7.183m 20.091ms 200 300 66.67
V2S sec_cm_config_redun entropy_src_rng 7.183m 20.091ms 200 300 66.67
V2S sec_cm_intersig_mubi entropy_src_rng 7.183m 20.091ms 200 300 66.67
entropy_src_fw_ov 6.183m 19.052ms 161 300 53.67
V2S sec_cm_main_sm_fsm_sparse entropy_src_functional_errors 23.050m 10.012ms 972 1000 97.20
entropy_src_sec_cm 9.000s 110.014us 5 5 100.00
V2S sec_cm_ack_sm_fsm_sparse entropy_src_functional_errors 23.050m 10.012ms 972 1000 97.20
entropy_src_sec_cm 9.000s 110.014us 5 5 100.00
V2S sec_cm_rng_bkgn_chk entropy_src_rng 7.183m 20.091ms 200 300 66.67
V2S sec_cm_fifo_ctr_redun entropy_src_functional_errors 23.050m 10.012ms 972 1000 97.20
entropy_src_sec_cm 9.000s 110.014us 5 5 100.00
V2S sec_cm_ctr_redun entropy_src_functional_errors 23.050m 10.012ms 972 1000 97.20
entropy_src_sec_cm 9.000s 110.014us 5 5 100.00
V2S sec_cm_ctr_local_esc entropy_src_functional_errors 23.050m 10.012ms 972 1000 97.20
V2S sec_cm_esfinal_rdata_bus_consistency entropy_src_functional_alerts 13.000s 493.146us 50 50 100.00
V2S sec_cm_tile_link_bus_integrity entropy_src_tl_intg_err 16.000s 209.467us 20 20 100.00
V2S TOTAL 75 75 100.00
V3 external_health_tests entropy_src_rng_with_xht_rsps 5.900m 18.056ms 31 50 62.00
V3 TOTAL 31 50 62.00
TOTAL 2074 2570 80.70

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
97.14 98.19 95.43 98.35 95.59 96.74 96.88 90.95 95.70

Failure Buckets