GPIO Simulation Results

Friday January 24 2025 17:10:00 UTC

GitHub Revision: 002bb67a7c

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	gpio_smoke	2.510s	73.794us	50	50	100.00
		gpio_smoke_no_pullup_pulldown	2.300s	380.361us	50	50	100.00
		gpio_smoke_en_cdc_prim	2.840s	80.901us	50	50	100.00
		gpio_smoke_no_pullup_pulldown_en_cdc_prim	2.800s	235.710us	50	50	100.00
V1	csr_hw_reset	gpio_csr_hw_reset	2.000s	13.243us	5	5	100.00
V1	csr_rw	gpio_csr_rw	2.130s	15.165us	20	20	100.00
V1	csr_bit_bash	gpio_csr_bit_bash	3.420s	250.613us	5	5	100.00
V1	csr_aliasing	gpio_csr_aliasing	1.930s	29.128us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	gpio_csr_mem_rw_with_rand_reset	2.450s	56.202us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	gpio_csr_rw	2.130s	15.165us	20	20	100.00
		gpio_csr_aliasing	1.930s	29.128us	5	5	100.00
V1		TOTAL			255	255	100.00
V2	direct_and_masked_out	gpio_random_dout_din	2.440s	670.508us	50	50	100.00
		gpio_random_dout_din_no_pullup_pulldown	2.280s	47.153us	50	50	100.00
V2	out_in_regs_read_write	gpio_dout_din_regs_random_rw	2.010s	27.400us	50	50	100.00
V2	gpio_interrupt_programming	gpio_intr_rand_pgm	2.380s	203.066us	50	50	100.00
V2	random_interrupt_trigger	gpio_rand_intr_trigger	3.820s	123.696us	50	50	100.00
V2	interrupt_and_noise_filter	gpio_intr_with_filter_rand_intr_event	3.630s	94.296us	50	50	100.00
V2	noise_filter_stress	gpio_filter_stress	18.650s	2.146ms	50	50	100.00
V2	regs_long_reads_and_writes	gpio_random_long_reg_writes_reg_reads	5.280s	1.116ms	50	50	100.00
V2	full_random	gpio_full_random	2.270s	341.011us	50	50	100.00
V2	stress_all	gpio_stress_all	2.312m	60.893ms	50	50	100.00
V2	alert_test	gpio_alert_test	1.930s	20.852us	50	50	100.00
V2	intr_test	gpio_intr_test	2.160s	17.761us	50	50	100.00
V2	tl_d_oob_addr_access	gpio_tl_errors	3.910s	168.173us	20	20	100.00
V2	tl_d_illegal_access	gpio_tl_errors	3.910s	168.173us	20	20	100.00
V2	tl_d_outstanding_access	gpio_csr_rw	2.130s	15.165us	20	20	100.00
		gpio_same_csr_outstanding	2.360s	49.187us	20	20	100.00
		gpio_csr_aliasing	1.930s	29.128us	5	5	100.00
		gpio_csr_hw_reset	2.000s	13.243us	5	5	100.00
V2	tl_d_partial_access	gpio_csr_rw	2.130s	15.165us	20	20	100.00
		gpio_same_csr_outstanding	2.360s	49.187us	20	20	100.00
		gpio_csr_aliasing	1.930s	29.128us	5	5	100.00
		gpio_csr_hw_reset	2.000s	13.243us	5	5	100.00
V2		TOTAL			640	640	100.00
V2S	tl_intg_err	gpio_tl_intg_err	5.820s	101.924us	20	20	100.00
		gpio_sec_cm	3.400s	87.515us	5	5	100.00
V2S	sec_cm_bus_integrity	gpio_tl_intg_err	5.820s	101.924us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	gpio_stress_all_with_rand_reset	2.020m	11.587ms	20	50	40.00
V3		TOTAL			20	50	40.00
		TOTAL			940	970	96.91

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.41	98.22	99.56	94.02	--	99.01	99.68	99.99

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:890) [gpio_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 30 failures:
  • Test gpio_stress_all_with_rand_reset has 30 failures.

    • 0.gpio_stress_all_with_rand_reset.37083267988318183042692143526689620203938673966318751555740359546345540490386
      Line 1112, in log /nightly/runs/opentitan/scratch/master/gpio-sim-vcs/0.gpio_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 3234428437 ps: (cip_base_vseq.sv:890) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Waited 10015 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 3234428437 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.gpio_stress_all_with_rand_reset.115686864710910312814618623743998459230442721968372199052619458205178811492106
      Line 234, in log /nightly/runs/opentitan/scratch/master/gpio-sim-vcs/1.gpio_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 436732796 ps: (cip_base_vseq.sv:890) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Waited 10010 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 436732796 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 28 more failures.