HMAC Simulation Results

Friday January 24 2025 17:10:00 UTC

GitHub Revision: 002bb67a7c

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	hmac_smoke	16.110s	4.021ms	50	50	100.00
V1	csr_hw_reset	hmac_csr_hw_reset	2.190s	47.028us	5	5	100.00
V1	csr_rw	hmac_csr_rw	2.320s	29.045us	20	20	100.00
V1	csr_bit_bash	hmac_csr_bit_bash	10.920s	308.617us	5	5	100.00
V1	csr_aliasing	hmac_csr_aliasing	6.540s	533.808us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	hmac_csr_mem_rw_with_rand_reset	11.423m	279.196ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	hmac_csr_rw	2.320s	29.045us	20	20	100.00
		hmac_csr_aliasing	6.540s	533.808us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	long_msg	hmac_long_msg	1.227m	7.397ms	50	50	100.00
V2	back_pressure	hmac_back_pressure	1.254m	7.430ms	50	50	100.00
V2	test_vectors	hmac_test_sha256_vectors	7.227m	71.147ms	5	5	100.00
		hmac_test_sha384_vectors	30.455m	194.546ms	5	5	100.00
		hmac_test_sha512_vectors	29.054m	421.818ms	5	5	100.00
		hmac_test_hmac256_vectors	35.330s	5.992ms	5	5	100.00
		hmac_test_hmac384_vectors	1.260m	28.337ms	5	5	100.00
		hmac_test_hmac512_vectors	1.667m	44.695ms	5	5	100.00
V2	burst_wr	hmac_burst_wr	28.940s	7.139ms	50	50	100.00
V2	datapath_stress	hmac_datapath_stress	17.852m	52.018ms	50	50	100.00
V2	error	hmac_error	1.588m	49.304ms	50	50	100.00
V2	wipe_secret	hmac_wipe_secret	2.076m	23.969ms	50	50	100.00
V2	save_and_restore	hmac_smoke	16.110s	4.021ms	50	50	100.00
		hmac_long_msg	1.227m	7.397ms	50	50	100.00
		hmac_back_pressure	1.254m	7.430ms	50	50	100.00
		hmac_datapath_stress	17.852m	52.018ms	50	50	100.00
		hmac_burst_wr	28.940s	7.139ms	50	50	100.00
		hmac_stress_all	1.147h	131.225ms	50	50	100.00
V2	fifo_empty_status_interrupt	hmac_smoke	16.110s	4.021ms	50	50	100.00
		hmac_long_msg	1.227m	7.397ms	50	50	100.00
		hmac_back_pressure	1.254m	7.430ms	50	50	100.00
		hmac_datapath_stress	17.852m	52.018ms	50	50	100.00
		hmac_wipe_secret	2.076m	23.969ms	50	50	100.00
		hmac_test_sha256_vectors	7.227m	71.147ms	5	5	100.00
		hmac_test_sha384_vectors	30.455m	194.546ms	5	5	100.00
		hmac_test_sha512_vectors	29.054m	421.818ms	5	5	100.00
		hmac_test_hmac256_vectors	35.330s	5.992ms	5	5	100.00
		hmac_test_hmac384_vectors	1.260m	28.337ms	5	5	100.00
		hmac_test_hmac512_vectors	1.667m	44.695ms	5	5	100.00
V2	wide_digest_configurable_key_length	hmac_smoke	16.110s	4.021ms	50	50	100.00
		hmac_long_msg	1.227m	7.397ms	50	50	100.00
		hmac_back_pressure	1.254m	7.430ms	50	50	100.00
		hmac_datapath_stress	17.852m	52.018ms	50	50	100.00
		hmac_burst_wr	28.940s	7.139ms	50	50	100.00
		hmac_error	1.588m	49.304ms	50	50	100.00
		hmac_wipe_secret	2.076m	23.969ms	50	50	100.00
		hmac_test_sha256_vectors	7.227m	71.147ms	5	5	100.00
		hmac_test_sha384_vectors	30.455m	194.546ms	5	5	100.00
		hmac_test_sha512_vectors	29.054m	421.818ms	5	5	100.00
		hmac_test_hmac256_vectors	35.330s	5.992ms	5	5	100.00
		hmac_test_hmac384_vectors	1.260m	28.337ms	5	5	100.00
		hmac_test_hmac512_vectors	1.667m	44.695ms	5	5	100.00
		hmac_stress_all	1.147h	131.225ms	50	50	100.00
V2	stress_all	hmac_stress_all	1.147h	131.225ms	50	50	100.00
V2	alert_test	hmac_alert_test	4.820s	16.604us	50	50	100.00
V2	intr_test	hmac_intr_test	2.610s	33.636us	50	50	100.00
V2	tl_d_oob_addr_access	hmac_tl_errors	4.110s	482.286us	20	20	100.00
V2	tl_d_illegal_access	hmac_tl_errors	4.110s	482.286us	20	20	100.00
V2	tl_d_outstanding_access	hmac_csr_hw_reset	2.190s	47.028us	5	5	100.00
		hmac_csr_rw	2.320s	29.045us	20	20	100.00
		hmac_csr_aliasing	6.540s	533.808us	5	5	100.00
		hmac_same_csr_outstanding	3.120s	344.850us	20	20	100.00
V2	tl_d_partial_access	hmac_csr_hw_reset	2.190s	47.028us	5	5	100.00
		hmac_csr_rw	2.320s	29.045us	20	20	100.00
		hmac_csr_aliasing	6.540s	533.808us	5	5	100.00
		hmac_same_csr_outstanding	3.120s	344.850us	20	20	100.00
V2		TOTAL			520	520	100.00
V2S	tl_intg_err	hmac_sec_cm	6.020s	228.904us	5	5	100.00
		hmac_tl_intg_err	8.780s	543.203us	20	20	100.00
V2S	sec_cm_bus_integrity	hmac_tl_intg_err	8.780s	543.203us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	write_config_and_secret_key_during_msg_wr	hmac_smoke	16.110s	4.021ms	50	50	100.00
V3	stress_reset	hmac_stress_reset	7.000s	149.625us	50	50	100.00
V3	stress_all_with_rand_reset	hmac_stress_all_with_rand_reset	3.411m	9.367ms	10	10	100.00
V3		TOTAL			60	60	100.00
		TOTAL			710	710	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.05	96.31	96.04	100.00	97.06	97.90	99.03	100.00