002bb67a7c| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | host_smoke | i2c_host_smoke | 1.227m | 8.284ms | 50 | 50 | 100.00 |
| V1 | target_smoke | i2c_target_smoke | 30.660s | 5.556ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | i2c_csr_hw_reset | 3.180s | 46.257us | 5 | 5 | 100.00 |
| V1 | csr_rw | i2c_csr_rw | 2.960s | 99.062us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | i2c_csr_bit_bash | 5.400s | 2.083ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | i2c_csr_aliasing | 3.290s | 111.933us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | i2c_csr_mem_rw_with_rand_reset | 3.100s | 32.244us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | i2c_csr_rw | 2.960s | 99.062us | 20 | 20 | 100.00 |
| i2c_csr_aliasing | 3.290s | 111.933us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 155 | 155 | 100.00 | |||
| V2 | host_error_intr | i2c_host_error_intr | 5.770s | 596.866us | 50 | 50 | 100.00 |
| V2 | host_stress_all | i2c_host_stress_all | 36.067m | 36.590ms | 17 | 50 | 34.00 |
| V2 | host_maxperf | i2c_host_perf | 47.890m | 50.728ms | 49 | 50 | 98.00 |
| V2 | host_override | i2c_host_override | 1.840s | 51.739us | 50 | 50 | 100.00 |
| V2 | host_fifo_watermark | i2c_host_fifo_watermark | 3.752m | 10.038ms | 50 | 50 | 100.00 |
| V2 | host_fifo_overflow | i2c_host_fifo_overflow | 1.993m | 5.173ms | 50 | 50 | 100.00 |
| V2 | host_fifo_reset | i2c_host_fifo_reset_fmt | 2.520s | 99.150us | 50 | 50 | 100.00 |
| i2c_host_fifo_fmt_empty | 22.940s | 923.994us | 50 | 50 | 100.00 | ||
| i2c_host_fifo_reset_rx | 9.870s | 989.867us | 50 | 50 | 100.00 | ||
| V2 | host_fifo_full | i2c_host_fifo_full | 2.683m | 3.728ms | 50 | 50 | 100.00 |
| V2 | host_timeout | i2c_host_stretch_timeout | 35.170s | 17.641ms | 50 | 50 | 100.00 |
| V2 | i2c_host_mode_toggle | i2c_host_mode_toggle | 6.410s | 164.800us | 9 | 50 | 18.00 |
| V2 | target_glitch | i2c_target_glitch | 11.400s | 17.244ms | 2 | 2 | 100.00 |
| V2 | target_stress_all | i2c_target_stress_all | 12.071m | 45.345ms | 48 | 50 | 96.00 |
| V2 | target_maxperf | i2c_target_perf | 6.920s | 1.031ms | 50 | 50 | 100.00 |
| V2 | target_fifo_empty | i2c_target_stress_rd | 55.750s | 9.072ms | 50 | 50 | 100.00 |
| i2c_target_intr_smoke | 12.390s | 1.486ms | 50 | 50 | 100.00 | ||
| V2 | target_fifo_reset | i2c_target_fifo_reset_acq | 2.720s | 913.125us | 50 | 50 | 100.00 |
| i2c_target_fifo_reset_tx | 3.080s | 1.902ms | 50 | 50 | 100.00 | ||
| V2 | target_fifo_full | i2c_target_stress_wr | 17.127m | 66.206ms | 50 | 50 | 100.00 |
| i2c_target_stress_rd | 55.750s | 9.072ms | 50 | 50 | 100.00 | ||
| i2c_target_intr_stress_wr | 4.369m | 21.326ms | 50 | 50 | 100.00 | ||
| V2 | target_timeout | i2c_target_timeout | 8.690s | 1.516ms | 50 | 50 | 100.00 |
| V2 | target_clock_stretch | i2c_target_stretch | 2.602m | 5.191ms | 39 | 50 | 78.00 |
| V2 | bad_address | i2c_target_bad_addr | 9.270s | 1.299ms | 50 | 50 | 100.00 |
| V2 | target_mode_glitch | i2c_target_hrst | 23.060s | 10.018ms | 17 | 50 | 34.00 |
| V2 | target_fifo_watermark | i2c_target_fifo_watermarks_acq | 4.780s | 1.057ms | 50 | 50 | 100.00 |
| i2c_target_fifo_watermarks_tx | 3.030s | 122.673us | 50 | 50 | 100.00 | ||
| V2 | host_mode_config_perf | i2c_host_perf | 47.890m | 50.728ms | 49 | 50 | 98.00 |
| i2c_host_perf_precise | 5.313m | 24.443ms | 50 | 50 | 100.00 | ||
| V2 | host_mode_clock_stretching | i2c_host_stretch_timeout | 35.170s | 17.641ms | 50 | 50 | 100.00 |
| V2 | target_mode_tx_stretch_ctrl | i2c_target_tx_stretch_ctrl | 12.590s | 1.192ms | 49 | 50 | 98.00 |
| V2 | target_mode_nack_generation | i2c_target_nack_acqfull | 3.580s | 589.719us | 50 | 50 | 100.00 |
| i2c_target_nack_acqfull_addr | 3.820s | 1.063ms | 50 | 50 | 100.00 | ||
| i2c_target_nack_txstretch | 2.550s | 153.762us | 34 | 50 | 68.00 | ||
| V2 | host_mode_halt_on_nak | i2c_host_may_nack | 16.990s | 621.268us | 50 | 50 | 100.00 |
| V2 | target_mode_smbus_maxlen | i2c_target_smbus_maxlen | 3.830s | 534.432us | 50 | 50 | 100.00 |
| V2 | alert_test | i2c_alert_test | 2.130s | 49.799us | 50 | 50 | 100.00 |
| V2 | intr_test | i2c_intr_test | 2.920s | 24.756us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | i2c_tl_errors | 4.050s | 313.223us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | i2c_tl_errors | 4.050s | 313.223us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | i2c_csr_hw_reset | 3.180s | 46.257us | 5 | 5 | 100.00 |
| i2c_csr_rw | 2.960s | 99.062us | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 3.290s | 111.933us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 3.130s | 26.931us | 19 | 20 | 95.00 | ||
| V2 | tl_d_partial_access | i2c_csr_hw_reset | 3.180s | 46.257us | 5 | 5 | 100.00 |
| i2c_csr_rw | 2.960s | 99.062us | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 3.290s | 111.933us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 3.130s | 26.931us | 19 | 20 | 95.00 | ||
| V2 | TOTAL | 1653 | 1792 | 92.24 | |||
| V2S | tl_intg_err | i2c_tl_intg_err | 7.180s | 201.830us | 20 | 20 | 100.00 |
| i2c_sec_cm | 4.200s | 214.521us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | i2c_tl_intg_err | 7.180s | 201.830us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | host_stress_all_with_rand_reset | i2c_host_stress_all_with_rand_reset | 24.940s | 593.736us | 0 | 10 | 0.00 |
| V3 | target_error_intr | i2c_target_unexp_stop | 3.150s | 309.590us | 0 | 50 | 0.00 |
| V3 | target_stress_all_with_rand_reset | i2c_target_stress_all_with_rand_reset | 27.150s | 2.658ms | 0 | 10 | 0.00 |
| V3 | TOTAL | 0 | 70 | 0.00 | |||
| TOTAL | 1833 | 2042 | 89.76 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 91.04 | 97.20 | 89.65 | 95.24 | 72.62 | 94.18 | 98.51 | 89.89 |
UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 45 failures:
0.i2c_host_stress_all.80853338789759957586836657362567894107591519011942558548094178753588499882320
Line 180, in log /nightly/runs/opentitan/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 21725785099 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @1539328
2.i2c_host_stress_all.26091672486842657638480439057739341356131880368447362171609201747392098881122
Line 254, in log /nightly/runs/opentitan/scratch/master/i2c-sim-vcs/2.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 9802705303 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @2437312
... and 22 more failures.
4.i2c_host_mode_toggle.9002774745999263142974701902903478912986578241975806566342243739774068108366
Line 80, in log /nightly/runs/opentitan/scratch/master/i2c-sim-vcs/4.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 164799692 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @144845
5.i2c_host_mode_toggle.27168982704418177336192166758851309797591624461370673773072278313567931171915
Line 80, in log /nightly/runs/opentitan/scratch/master/i2c-sim-vcs/5.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 430808839 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @120799
... and 19 more failures.
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! has 33 failures:
2.i2c_target_hrst.87097887898975743083726784427575281283218802411271162288653515611138239929915
Line 74, in log /nightly/runs/opentitan/scratch/master/i2c-sim-vcs/2.i2c_target_hrst/latest/run.log
UVM_FATAL @ 10056231026 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
UVM_INFO @ 10056231026 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.i2c_target_hrst.4647144881362884158426336626194608706320296826082086549743521786767524069540
Line 74, in log /nightly/runs/opentitan/scratch/master/i2c-sim-vcs/4.i2c_target_hrst/latest/run.log
UVM_FATAL @ 13643189835 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
UVM_INFO @ 13643189835 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 31 more failures.
UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 26 failures:
1.i2c_target_unexp_stop.22434689197387094213488979992132840685903286253530914338406077313172994840253
Line 73, in log /nightly/runs/opentitan/scratch/master/i2c-sim-vcs/1.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 238718658 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 230 [0xe6])
UVM_INFO @ 238718658 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.i2c_target_unexp_stop.4797875432627793314089465686674334572153576186399311650096996029576695683799
Line 73, in log /nightly/runs/opentitan/scratch/master/i2c-sim-vcs/2.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 208027124 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 121 [0x79])
UVM_INFO @ 208027124 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 23 more failures.
1.i2c_target_stress_all_with_rand_reset.10737578393128937472935311829658327913993637598273538603955438317264761093217
Line 110, in log /nightly/runs/opentitan/scratch/master/i2c-sim-vcs/1.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 457499655 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 116 [0x74])
UVM_INFO @ 457499655 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [*] vs * [*]) has 19 failures:
0.i2c_target_unexp_stop.20450808110998733597497224896850894179498115927872165123718591710692422826291
Line 73, in log /nightly/runs/opentitan/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 1357637238 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
UVM_INFO @ 1357637238 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
8.i2c_target_unexp_stop.24103391130141580877766861612635156473217315417479814295528108010363899241657
Line 73, in log /nightly/runs/opentitan/scratch/master/i2c-sim-vcs/8.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 42965863 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
UVM_INFO @ 42965863 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 17 more failures.
UVM_ERROR (cip_base_vseq.sv:890) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 19 failures:
0.i2c_host_stress_all_with_rand_reset.67042442150755001627908367014967340354200407944427697732900923963529888609303
Line 80, in log /nightly/runs/opentitan/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 218774217 ps: (cip_base_vseq.sv:890) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 218774217 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_host_stress_all_with_rand_reset.17742451362602469149528523810669738225694145495473965179492085090391910180616
Line 92, in log /nightly/runs/opentitan/scratch/master/i2c-sim-vcs/1.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 593736186 ps: (cip_base_vseq.sv:890) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 593736186 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 8 more failures.
0.i2c_target_stress_all_with_rand_reset.51019447555379094434120852398485663128219116714076259458961849813281553520707
Line 81, in log /nightly/runs/opentitan/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 592121593 ps: (cip_base_vseq.sv:890) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 592121593 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.i2c_target_stress_all_with_rand_reset.17464991340453722338286966455185783468348142888072099633782186568875622375912
Line 87, in log /nightly/runs/opentitan/scratch/master/i2c-sim-vcs/2.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 11763980279 ps: (cip_base_vseq.sv:890) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 11763980279 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 7 more failures.
UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpRead has 16 failures:
1.i2c_host_mode_toggle.64122700807707816784275462437355772525730880307456767776451575118606331162388
Line 82, in log /nightly/runs/opentitan/scratch/master/i2c-sim-vcs/1.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 73775481 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
--> EXP:
---------------------------------------------------
Name Type Size Value
---------------------------------------------------
2.i2c_host_mode_toggle.80988567958058427275869136446603975017838697120815592996398908051733236619221
Line 82, in log /nightly/runs/opentitan/scratch/master/i2c-sim-vcs/2.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 708024070 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
--> EXP:
---------------------------------------------------
Name Type Size Value
---------------------------------------------------
... and 14 more failures.
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.target_nack_count reset value: * has 16 failures:
2.i2c_target_nack_txstretch.45633290027636373094251137435689728826510956435957620597503890150293148059921
Line 73, in log /nightly/runs/opentitan/scratch/master/i2c-sim-vcs/2.i2c_target_nack_txstretch/latest/run.log
UVM_ERROR @ 129405999 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
UVM_INFO @ 129405999 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
7.i2c_target_nack_txstretch.80127830407187881916281157448838355375623495161586001031724225530675803837784
Line 73, in log /nightly/runs/opentitan/scratch/master/i2c-sim-vcs/7.i2c_target_nack_txstretch/latest/run.log
UVM_ERROR @ 153549774 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
UVM_INFO @ 153549774 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 14 more failures.
UVM_FATAL (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred! has 11 failures:
0.i2c_target_stretch.85063379969395904809887437129956868062441084466961622276088341134957659657358
Line 73, in log /nightly/runs/opentitan/scratch/master/i2c-sim-vcs/0.i2c_target_stretch/latest/run.log
UVM_FATAL @ 10009438377 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
UVM_INFO @ 10009438377 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.i2c_target_stretch.38575726552291731664687834832849354594741300753055931687935571685295502139031
Line 73, in log /nightly/runs/opentitan/scratch/master/i2c-sim-vcs/3.i2c_target_stretch/latest/run.log
UVM_FATAL @ 10005290102 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
UVM_INFO @ 10005290102 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 9 more failures.
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))' has 6 failures:
5.i2c_target_unexp_stop.6110496861750214441559909088520258637626964520491186326211922677883439448204
Line 74, in log /nightly/runs/opentitan/scratch/master/i2c-sim-vcs/5.i2c_target_unexp_stop/latest/run.log
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
UVM_ERROR @ 383631384 ps: (i2c_fifos.sv:318) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
UVM_INFO @ 383631384 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
13.i2c_target_unexp_stop.78069881534121074315787063835082754866269639855568141744763434733807100467264
Line 74, in log /nightly/runs/opentitan/scratch/master/i2c-sim-vcs/13.i2c_target_unexp_stop/latest/run.log
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
UVM_ERROR @ 514612030 ps: (i2c_fifos.sv:318) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
UVM_INFO @ 514612030 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
Job timed out after * minutes has 6 failures:
6.i2c_host_stress_all.115539484209184639721844827523554829427108120530815797596530631219925841130389
Log /nightly/runs/opentitan/scratch/master/i2c-sim-vcs/6.i2c_host_stress_all/latest/run.log
Job timed out after 60 minutes
16.i2c_host_stress_all.71803010709531119389535923841526459102971530313161868907004865257272997429845
Log /nightly/runs/opentitan/scratch/master/i2c-sim-vcs/16.i2c_host_stress_all/latest/run.log
Job timed out after 60 minutes
... and 3 more failures.
34.i2c_host_perf.48884590606766722805329215675867020809244971500422858136698823763900667893543
Log /nightly/runs/opentitan/scratch/master/i2c-sim-vcs/34.i2c_host_perf/latest/run.log
Job timed out after 60 minutes
UVM_ERROR (i2c_scoreboard.sv:717) [scoreboard] controller_mode_wr_obs_fifo item uncompared: has 4 failures:
1.i2c_host_stress_all.2019311936675053981267378639636009448512992576543743751118911829256031308175
Line 236, in log /nightly/runs/opentitan/scratch/master/i2c-sim-vcs/1.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 81064921614 ps: (i2c_scoreboard.sv:717) [uvm_test_top.env.scoreboard] controller_mode_wr_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @22919382
15.i2c_host_stress_all.99415416173508876665875100024058670347340783018862004052714300691961475527340
Line 206, in log /nightly/runs/opentitan/scratch/master/i2c-sim-vcs/15.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 64071668899 ps: (i2c_scoreboard.sv:717) [uvm_test_top.env.scoreboard] controller_mode_wr_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @3673878
... and 2 more failures.
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) has 4 failures:
13.i2c_host_mode_toggle.60235136826706441740901236878716920353033362276859759433206014470700084587200
Line 74, in log /nightly/runs/opentitan/scratch/master/i2c-sim-vcs/13.i2c_host_mode_toggle/latest/run.log
UVM_FATAL @ 235004043 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=0x7d214894, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
UVM_INFO @ 235004043 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
35.i2c_host_mode_toggle.60185805867510777201702336346196196138289915050429586807734764777970965149018
Line 74, in log /nightly/runs/opentitan/scratch/master/i2c-sim-vcs/35.i2c_host_mode_toggle/latest/run.log
UVM_FATAL @ 305339690 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=0x5cdf9c94, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
UVM_INFO @ 305339690 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
UVM_FATAL (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred! has 2 failures:
22.i2c_target_stress_all.24939803873456607458514094006611086485979173605798539069136929396065986978038
Line 100, in log /nightly/runs/opentitan/scratch/master/i2c-sim-vcs/22.i2c_target_stress_all/latest/run.log
UVM_FATAL @ 42232496463 ps: (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred!
UVM_INFO @ 42232496463 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
39.i2c_target_stress_all.7299241827160536067540787935054007222642942875284788080259614120777018557114
Line 92, in log /nightly/runs/opentitan/scratch/master/i2c-sim-vcs/39.i2c_target_stress_all/latest/run.log
UVM_FATAL @ 59133386197 ps: (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred!
UVM_INFO @ 59133386197 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Error-[CNST-CIF] Constraints inconsistency failure has 1 failures:
0.i2c_target_tx_stretch_ctrl.49637780509649241426805109351286816025126871898240343221362110260028523470027
Line 119, in log /nightly/runs/opentitan/scratch/master/i2c-sim-vcs/0.i2c_target_tx_stretch_ctrl/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 872
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
UVM_ERROR (cip_base_vseq.sv:524) [i2c_common_vseq] Check failed data & ~ro_mask == * (* [*] vs * [*]) has 1 failures:
15.i2c_same_csr_outstanding.68987674544376084718641525908635446835461973180685012919798314325560901257665
Line 73, in log /nightly/runs/opentitan/scratch/master/i2c-sim-vcs/15.i2c_same_csr_outstanding/latest/run.log
UVM_ERROR @ 53032482 ps: (cip_base_vseq.sv:524) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed data & ~ro_mask == 0 (64 [0x40] vs 0 [0x0])
UVM_INFO @ 53032482 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---