002bb67a7c| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | keymgr_smoke | 20.910s | 1.790ms | 50 | 50 | 100.00 |
| V1 | random | keymgr_random | 50.330s | 13.613ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | keymgr_csr_hw_reset | 2.030s | 117.234us | 5 | 5 | 100.00 |
| V1 | csr_rw | keymgr_csr_rw | 2.740s | 104.275us | 18 | 20 | 90.00 |
| V1 | csr_bit_bash | keymgr_csr_bit_bash | 11.010s | 1.508ms | 4 | 5 | 80.00 |
| V1 | csr_aliasing | keymgr_csr_aliasing | 8.890s | 1.367ms | 2 | 5 | 40.00 |
| V1 | csr_mem_rw_with_rand_reset | keymgr_csr_mem_rw_with_rand_reset | 3.370s | 45.647us | 19 | 20 | 95.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | keymgr_csr_rw | 2.740s | 104.275us | 18 | 20 | 90.00 |
| keymgr_csr_aliasing | 8.890s | 1.367ms | 2 | 5 | 40.00 | ||
| V1 | TOTAL | 148 | 155 | 95.48 | |||
| V2 | cfgen_during_op | keymgr_cfg_regwen | 1.110m | 4.134ms | 49 | 50 | 98.00 |
| V2 | sideload | keymgr_sideload | 36.520s | 4.944ms | 50 | 50 | 100.00 |
| keymgr_sideload_kmac | 26.470s | 3.063ms | 50 | 50 | 100.00 | ||
| keymgr_sideload_aes | 42.860s | 6.756ms | 50 | 50 | 100.00 | ||
| keymgr_sideload_otbn | 39.530s | 1.725ms | 50 | 50 | 100.00 | ||
| V2 | direct_to_disabled_state | keymgr_direct_to_disabled | 30.120s | 3.286ms | 50 | 50 | 100.00 |
| V2 | lc_disable | keymgr_lc_disable | 15.190s | 460.172us | 48 | 50 | 96.00 |
| V2 | kmac_error_response | keymgr_kmac_rsp_err | 9.600s | 401.182us | 49 | 50 | 98.00 |
| V2 | invalid_sw_input | keymgr_sw_invalid_input | 26.630s | 3.134ms | 49 | 50 | 98.00 |
| V2 | invalid_hw_input | keymgr_hwsw_invalid_input | 33.970s | 5.057ms | 50 | 50 | 100.00 |
| V2 | sync_async_fault_cross | keymgr_sync_async_fault_cross | 11.950s | 1.114ms | 50 | 50 | 100.00 |
| V2 | stress_all | keymgr_stress_all | 4.109m | 18.058ms | 41 | 50 | 82.00 |
| V2 | intr_test | keymgr_intr_test | 2.690s | 11.204us | 50 | 50 | 100.00 |
| V2 | alert_test | keymgr_alert_test | 2.110s | 118.663us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | keymgr_tl_errors | 4.990s | 695.170us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | keymgr_tl_errors | 4.990s | 695.170us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | keymgr_csr_hw_reset | 2.030s | 117.234us | 5 | 5 | 100.00 |
| keymgr_csr_rw | 2.740s | 104.275us | 18 | 20 | 90.00 | ||
| keymgr_csr_aliasing | 8.890s | 1.367ms | 2 | 5 | 40.00 | ||
| keymgr_same_csr_outstanding | 3.940s | 285.853us | 15 | 20 | 75.00 | ||
| V2 | tl_d_partial_access | keymgr_csr_hw_reset | 2.030s | 117.234us | 5 | 5 | 100.00 |
| keymgr_csr_rw | 2.740s | 104.275us | 18 | 20 | 90.00 | ||
| keymgr_csr_aliasing | 8.890s | 1.367ms | 2 | 5 | 40.00 | ||
| keymgr_same_csr_outstanding | 3.940s | 285.853us | 15 | 20 | 75.00 | ||
| V2 | TOTAL | 721 | 740 | 97.43 | |||
| V2S | sec_cm_additional_check | keymgr_sec_cm | 33.060s | 1.612ms | 5 | 5 | 100.00 |
| V2S | tl_intg_err | keymgr_sec_cm | 33.060s | 1.612ms | 5 | 5 | 100.00 |
| keymgr_tl_intg_err | 12.980s | 780.527us | 17 | 20 | 85.00 | ||
| V2S | shadow_reg_update_error | keymgr_shadow_reg_errors | 6.220s | 2.244ms | 5 | 20 | 25.00 |
| V2S | shadow_reg_read_clear_staged_value | keymgr_shadow_reg_errors | 6.220s | 2.244ms | 5 | 20 | 25.00 |
| V2S | shadow_reg_storage_error | keymgr_shadow_reg_errors | 6.220s | 2.244ms | 5 | 20 | 25.00 |
| V2S | shadowed_reset_glitch | keymgr_shadow_reg_errors | 6.220s | 2.244ms | 5 | 20 | 25.00 |
| V2S | shadow_reg_update_error_with_csr_rw | keymgr_shadow_reg_errors_with_csr_rw | 11.080s | 504.656us | 0 | 20 | 0.00 |
| V2S | prim_count_check | keymgr_sec_cm | 33.060s | 1.612ms | 5 | 5 | 100.00 |
| V2S | prim_fsm_check | keymgr_sec_cm | 33.060s | 1.612ms | 5 | 5 | 100.00 |
| V2S | sec_cm_bus_integrity | keymgr_tl_intg_err | 12.980s | 780.527us | 17 | 20 | 85.00 |
| V2S | sec_cm_config_shadow | keymgr_shadow_reg_errors | 6.220s | 2.244ms | 5 | 20 | 25.00 |
| V2S | sec_cm_op_config_regwen | keymgr_cfg_regwen | 1.110m | 4.134ms | 49 | 50 | 98.00 |
| V2S | sec_cm_reseed_config_regwen | keymgr_random | 50.330s | 13.613ms | 50 | 50 | 100.00 |
| keymgr_csr_rw | 2.740s | 104.275us | 18 | 20 | 90.00 | ||
| V2S | sec_cm_sw_binding_config_regwen | keymgr_random | 50.330s | 13.613ms | 50 | 50 | 100.00 |
| keymgr_csr_rw | 2.740s | 104.275us | 18 | 20 | 90.00 | ||
| V2S | sec_cm_max_key_ver_config_regwen | keymgr_random | 50.330s | 13.613ms | 50 | 50 | 100.00 |
| keymgr_csr_rw | 2.740s | 104.275us | 18 | 20 | 90.00 | ||
| V2S | sec_cm_lc_ctrl_intersig_mubi | keymgr_lc_disable | 15.190s | 460.172us | 48 | 50 | 96.00 |
| V2S | sec_cm_constants_consistency | keymgr_hwsw_invalid_input | 33.970s | 5.057ms | 50 | 50 | 100.00 |
| V2S | sec_cm_intersig_consistency | keymgr_hwsw_invalid_input | 33.970s | 5.057ms | 50 | 50 | 100.00 |
| V2S | sec_cm_hw_key_sw_noaccess | keymgr_random | 50.330s | 13.613ms | 50 | 50 | 100.00 |
| V2S | sec_cm_output_keys_ctrl_redun | keymgr_sideload_protect | 13.760s | 811.317us | 50 | 50 | 100.00 |
| V2S | sec_cm_ctrl_fsm_sparse | keymgr_sec_cm | 33.060s | 1.612ms | 5 | 5 | 100.00 |
| V2S | sec_cm_data_fsm_sparse | keymgr_sec_cm | 33.060s | 1.612ms | 5 | 5 | 100.00 |
| V2S | sec_cm_ctrl_fsm_local_esc | keymgr_sec_cm | 33.060s | 1.612ms | 5 | 5 | 100.00 |
| V2S | sec_cm_ctrl_fsm_consistency | keymgr_custom_cm | 16.230s | 1.033ms | 50 | 50 | 100.00 |
| V2S | sec_cm_ctrl_fsm_global_esc | keymgr_lc_disable | 15.190s | 460.172us | 48 | 50 | 96.00 |
| V2S | sec_cm_ctrl_ctr_redun | keymgr_sec_cm | 33.060s | 1.612ms | 5 | 5 | 100.00 |
| V2S | sec_cm_kmac_if_fsm_sparse | keymgr_sec_cm | 33.060s | 1.612ms | 5 | 5 | 100.00 |
| V2S | sec_cm_kmac_if_ctr_redun | keymgr_sec_cm | 33.060s | 1.612ms | 5 | 5 | 100.00 |
| V2S | sec_cm_kmac_if_cmd_ctrl_consistency | keymgr_custom_cm | 16.230s | 1.033ms | 50 | 50 | 100.00 |
| V2S | sec_cm_kmac_if_done_ctrl_consistency | keymgr_custom_cm | 16.230s | 1.033ms | 50 | 50 | 100.00 |
| V2S | sec_cm_reseed_ctr_redun | keymgr_sec_cm | 33.060s | 1.612ms | 5 | 5 | 100.00 |
| V2S | sec_cm_side_load_sel_ctrl_consistency | keymgr_custom_cm | 16.230s | 1.033ms | 50 | 50 | 100.00 |
| V2S | sec_cm_sideload_ctrl_fsm_sparse | keymgr_sec_cm | 33.060s | 1.612ms | 5 | 5 | 100.00 |
| V2S | sec_cm_ctrl_key_integrity | keymgr_custom_cm | 16.230s | 1.033ms | 50 | 50 | 100.00 |
| V2S | TOTAL | 127 | 165 | 76.97 | |||
| V3 | stress_all_with_rand_reset | keymgr_stress_all_with_rand_reset | 21.310s | 1.739ms | 26 | 50 | 52.00 |
| V3 | TOTAL | 26 | 50 | 52.00 | |||
| TOTAL | 1022 | 1110 | 92.07 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 97.73 | 99.02 | 98.11 | 98.21 | 100.00 | 99.01 | 98.64 | 91.14 |
UVM_FATAL (alert_receiver_driver.sv:145) [driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q has 28 failures:
1.keymgr_shadow_reg_errors.107661494362343684793611202993322417761436021289223677102639659388608295488309
Line 85, in log /nightly/runs/opentitan/scratch/master/keymgr-sim-vcs/1.keymgr_shadow_reg_errors/latest/run.log
UVM_FATAL @ 19518893 ps: (alert_receiver_driver.sv:145) [uvm_test_top.env.m_alert_agent_fatal_fault_err.driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q
UVM_INFO @ 19518893 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.keymgr_shadow_reg_errors.29314538963853263233109014234170391320155164308192625136006728722468654802726
Line 80, in log /nightly/runs/opentitan/scratch/master/keymgr-sim-vcs/3.keymgr_shadow_reg_errors/latest/run.log
UVM_FATAL @ 33113826 ps: (alert_receiver_driver.sv:145) [uvm_test_top.env.m_alert_agent_fatal_fault_err.driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q
UVM_INFO @ 33113826 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 13 more failures.
1.keymgr_shadow_reg_errors_with_csr_rw.58624149430274328019383565093592389107117069897421875998196664345876687225610
Line 112, in log /nightly/runs/opentitan/scratch/master/keymgr-sim-vcs/1.keymgr_shadow_reg_errors_with_csr_rw/latest/run.log
UVM_FATAL @ 504656059 ps: (alert_receiver_driver.sv:145) [uvm_test_top.env.m_alert_agent_fatal_fault_err.driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q
UVM_INFO @ 504656059 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.keymgr_shadow_reg_errors_with_csr_rw.29920420322851138361119761930203928341128348851657986619807421478153175569572
Line 77, in log /nightly/runs/opentitan/scratch/master/keymgr-sim-vcs/3.keymgr_shadow_reg_errors_with_csr_rw/latest/run.log
UVM_FATAL @ 9817656 ps: (alert_receiver_driver.sv:145) [uvm_test_top.env.m_alert_agent_fatal_fault_err.driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q
UVM_INFO @ 9817656 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 11 more failures.
Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 22 failures:
Test keymgr_shadow_reg_errors_with_csr_rw has 7 failures.
0.keymgr_shadow_reg_errors_with_csr_rw.92297680602251581168421854018760831148578156819201044887366663454822188223031
Line 76, in log /nightly/runs/opentitan/scratch/master/keymgr-sim-vcs/0.keymgr_shadow_reg_errors_with_csr_rw/latest/run.log
Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[7] & 'hffffffff)))'
UVM_ERROR @ 9109831 ps: (keymgr_csr_assert_fpv.sv:401) [ASSERT FAILED] sealing_sw_binding_2_rd_A
UVM_INFO @ 9109831 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.keymgr_shadow_reg_errors_with_csr_rw.31419711936153787567889481201546259423757097059414043277832986157196698190914
Line 75, in log /nightly/runs/opentitan/scratch/master/keymgr-sim-vcs/2.keymgr_shadow_reg_errors_with_csr_rw/latest/run.log
Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[15] & 'hffffffff)))'
UVM_ERROR @ 31104866 ps: (keymgr_csr_assert_fpv.sv:441) [ASSERT FAILED] attest_sw_binding_2_rd_A
UVM_INFO @ 31104866 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 5 more failures.
Test keymgr_csr_aliasing has 3 failures.
0.keymgr_csr_aliasing.5699767491870553863192425692153926140181038077715057009354758677428911741133
Line 75, in log /nightly/runs/opentitan/scratch/master/keymgr-sim-vcs/0.keymgr_csr_aliasing/latest/run.log
Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[8] & 'hffffffff)))'
UVM_ERROR @ 210590545 ps: (keymgr_csr_assert_fpv.sv:406) [ASSERT FAILED] sealing_sw_binding_3_rd_A
UVM_INFO @ 210590545 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.keymgr_csr_aliasing.86257424522676260169635972175846159020641131995808523700806541113143710057929
Line 77, in log /nightly/runs/opentitan/scratch/master/keymgr-sim-vcs/1.keymgr_csr_aliasing/latest/run.log
Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[19] & 'hffffffff)))'
UVM_ERROR @ 1366622147 ps: (keymgr_csr_assert_fpv.sv:461) [ASSERT FAILED] attest_sw_binding_6_rd_A
UVM_INFO @ 1366622147 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Test keymgr_same_csr_outstanding has 5 failures.
0.keymgr_same_csr_outstanding.104785654272592326947427654201796548742370936098572752585461593739613512018032
Line 76, in log /nightly/runs/opentitan/scratch/master/keymgr-sim-vcs/0.keymgr_same_csr_outstanding/latest/run.log
Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[8] & 'hffffffff)))'
UVM_ERROR @ 182904611 ps: (keymgr_csr_assert_fpv.sv:406) [ASSERT FAILED] sealing_sw_binding_3_rd_A
UVM_INFO @ 182904611 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.keymgr_same_csr_outstanding.19798397033412283678119089081260916601678427115434385340334468198776713286775
Line 76, in log /nightly/runs/opentitan/scratch/master/keymgr-sim-vcs/2.keymgr_same_csr_outstanding/latest/run.log
Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[5] & 'hffffffff)))'
UVM_ERROR @ 61942429 ps: (keymgr_csr_assert_fpv.sv:391) [ASSERT FAILED] sealing_sw_binding_0_rd_A
UVM_INFO @ 61942429 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
Test keymgr_csr_rw has 2 failures.
2.keymgr_csr_rw.15677188340708186668711368193449712252890006427098174766025439902514932396216
Line 76, in log /nightly/runs/opentitan/scratch/master/keymgr-sim-vcs/2.keymgr_csr_rw/latest/run.log
Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[8] & 'hffffffff)))'
UVM_ERROR @ 121558623 ps: (keymgr_csr_assert_fpv.sv:406) [ASSERT FAILED] sealing_sw_binding_3_rd_A
UVM_INFO @ 121558623 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
9.keymgr_csr_rw.54094309874640142054860625625477391453733720229030007097387203755393707501443
Line 77, in log /nightly/runs/opentitan/scratch/master/keymgr-sim-vcs/9.keymgr_csr_rw/latest/run.log
Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[8] & 'hffffffff)))'
UVM_ERROR @ 84551354 ps: (keymgr_csr_assert_fpv.sv:406) [ASSERT FAILED] sealing_sw_binding_3_rd_A
UVM_INFO @ 84551354 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test keymgr_tl_intg_err has 3 failures.
3.keymgr_tl_intg_err.114805643903429991039878710717639541966191464167564961292539170211545028903209
Line 161, in log /nightly/runs/opentitan/scratch/master/keymgr-sim-vcs/3.keymgr_tl_intg_err/latest/run.log
Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[7] & 'hffffffff)))'
UVM_ERROR @ 104101571 ps: (keymgr_csr_assert_fpv.sv:401) [ASSERT FAILED] sealing_sw_binding_2_rd_A
UVM_INFO @ 104101571 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.keymgr_tl_intg_err.38881024287925170845922493872992663239985877763096783607304453005122077026811
Line 97, in log /nightly/runs/opentitan/scratch/master/keymgr-sim-vcs/5.keymgr_tl_intg_err/latest/run.log
Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[18] & 'hffffffff)))'
UVM_ERROR @ 65868134 ps: (keymgr_csr_assert_fpv.sv:456) [ASSERT FAILED] attest_sw_binding_5_rd_A
UVM_INFO @ 65868134 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
... and 2 more tests.
UVM_ERROR (cip_base_vseq.sv:890) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 21 failures:
0.keymgr_stress_all_with_rand_reset.81250648064637412681546268282394171594156933203864699957877385410819128395229
Line 406, in log /nightly/runs/opentitan/scratch/master/keymgr-sim-vcs/0.keymgr_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 224037305 ps: (cip_base_vseq.sv:890) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 224037305 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.keymgr_stress_all_with_rand_reset.29979054851298377103547520195596737065796901371791634872541604779615801244810
Line 107, in log /nightly/runs/opentitan/scratch/master/keymgr-sim-vcs/2.keymgr_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 468025472 ps: (cip_base_vseq.sv:890) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 468025472 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 19 more failures.
UVM_ERROR (cip_base_scoreboard.sv:323) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:* has 11 failures:
Test keymgr_stress_all has 7 failures.
0.keymgr_stress_all.19973126288168731419339008423986878294638922561756001922889582690416053659443
Line 1469, in log /nightly/runs/opentitan/scratch/master/keymgr-sim-vcs/0.keymgr_stress_all/latest/run.log
UVM_ERROR @ 5209446528 ps: (cip_base_scoreboard.sv:323) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
UVM_INFO @ 5209446528 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
9.keymgr_stress_all.53229698992384583609719408165562623841583035472247283820614235393773083833240
Line 1512, in log /nightly/runs/opentitan/scratch/master/keymgr-sim-vcs/9.keymgr_stress_all/latest/run.log
UVM_ERROR @ 7192003260 ps: (cip_base_scoreboard.sv:323) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
UVM_INFO @ 7192003260 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 5 more failures.
Test keymgr_cfg_regwen has 1 failures.
3.keymgr_cfg_regwen.16762522202516731205091550433869320506587191171190423755177190053772259476424
Line 413, in log /nightly/runs/opentitan/scratch/master/keymgr-sim-vcs/3.keymgr_cfg_regwen/latest/run.log
UVM_ERROR @ 4365818911 ps: (cip_base_scoreboard.sv:323) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
UVM_INFO @ 4365818911 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test keymgr_lc_disable has 1 failures.
5.keymgr_lc_disable.50038155452442551185092759333364885614849563305168476869692731962367609454339
Line 221, in log /nightly/runs/opentitan/scratch/master/keymgr-sim-vcs/5.keymgr_lc_disable/latest/run.log
UVM_ERROR @ 136104116 ps: (cip_base_scoreboard.sv:323) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
UVM_INFO @ 136104116 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test keymgr_kmac_rsp_err has 1 failures.
8.keymgr_kmac_rsp_err.108362955601498025197860696549990665890465786863863038049519978647812953075637
Line 477, in log /nightly/runs/opentitan/scratch/master/keymgr-sim-vcs/8.keymgr_kmac_rsp_err/latest/run.log
UVM_ERROR @ 64687636 ps: (cip_base_scoreboard.sv:323) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
UVM_INFO @ 64687636 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test keymgr_sw_invalid_input has 1 failures.
21.keymgr_sw_invalid_input.39390778237147845291911041851746428765443561933455060930291433741330601380413
Line 357, in log /nightly/runs/opentitan/scratch/master/keymgr-sim-vcs/21.keymgr_sw_invalid_input/latest/run.log
UVM_ERROR @ 1540657635 ps: (cip_base_scoreboard.sv:323) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
UVM_INFO @ 1540657635 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (keymgr_scoreboard.sv:766) [scoreboard] Check failed item.d_data !=gmv(csr) (* [] vs * []) reg name: keymgr_reg_block.sw_share0_output_*` has 3 failures:
Test keymgr_stress_all_with_rand_reset has 1 failures.
27.keymgr_stress_all_with_rand_reset.65358612217907762151099045183359156882237308089712905043043693190352865115137
Line 2016, in log /nightly/runs/opentitan/scratch/master/keymgr-sim-vcs/27.keymgr_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1148958579 ps: (keymgr_scoreboard.sv:766) [uvm_test_top.env.scoreboard] Check failed item.d_data != `gmv(csr) (2709656849 [0xa1821511] vs 2709656849 [0xa1821511]) reg name: keymgr_reg_block.sw_share0_output_0
UVM_INFO @ 1148958579 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test keymgr_stress_all has 2 failures.
41.keymgr_stress_all.29539385226652058786347118266785752312133184226801693214942254839385474224874
Line 1055, in log /nightly/runs/opentitan/scratch/master/keymgr-sim-vcs/41.keymgr_stress_all/latest/run.log
UVM_ERROR @ 894191352 ps: (keymgr_scoreboard.sv:766) [uvm_test_top.env.scoreboard] Check failed item.d_data != `gmv(csr) (0 [0x0] vs 0 [0x0]) reg name: keymgr_reg_block.sw_share0_output_1
UVM_INFO @ 894191352 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
49.keymgr_stress_all.75719804324241624102293124409402990916243001381865982404801623471535960745662
Line 1727, in log /nightly/runs/opentitan/scratch/master/keymgr-sim-vcs/49.keymgr_stress_all/latest/run.log
UVM_ERROR @ 668153905 ps: (keymgr_scoreboard.sv:766) [uvm_test_top.env.scoreboard] Check failed item.d_data != `gmv(csr) (0 [0x0] vs 0 [0x0]) reg name: keymgr_reg_block.sw_share0_output_5
UVM_INFO @ 668153905 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:794) [keymgr_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 2 failures:
1.keymgr_stress_all_with_rand_reset.6669327878224835249951794179788548069403730625162559574594787659121986393623
Line 1833, in log /nightly/runs/opentitan/scratch/master/keymgr-sim-vcs/1.keymgr_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1936827650 ps: (cip_base_vseq.sv:794) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 1936827650 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
35.keymgr_stress_all_with_rand_reset.73778513586987377531353191628693966986938034704353839247850312422486909242542
Line 373, in log /nightly/runs/opentitan/scratch/master/keymgr-sim-vcs/35.keymgr_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 826159289 ps: (cip_base_vseq.sv:794) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 826159289 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[*], act_key.key[*]} !== keys_a_array[state][cdi][dest] (* [*] vs * [*]) AES key at state StOwnerIntKey for Attestation Aes has 1 failures:
34.keymgr_lc_disable.76514178133665570173569048790278134568397511616526845081647624092077660014362
Line 297, in log /nightly/runs/opentitan/scratch/master/keymgr-sim-vcs/34.keymgr_lc_disable/latest/run.log
UVM_ERROR @ 2760585703 ps: (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[1], act_key.key[0]} !== keys_a_array[state][cdi][dest] (544557302673114948248630586767120015332933705681379283185590068390941308993932593714819638754075197035634130588948860463039458091976962874221880591119137 [0xa65bd9b34da4ec5411736e330dba73617591504317630590e2dc2d7826681ea5bec3820d14937e3441e0c433ee5a4eee9c09c64989ca1ba86d0b49bfa49f321] vs 544557302673114948248630586767120015332933705681379283185590068390941308993932593714819638754075197035634130588948860463039458091976962874221880591119137 [0xa65bd9b34da4ec5411736e330dba73617591504317630590e2dc2d7826681ea5bec3820d14937e3441e0c433ee5a4eee9c09c64989ca1ba86d0b49bfa49f321]) AES key at state StOwnerIntKey for Attestation Aes
UVM_INFO @ 2760585703 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---