KMAC/MASKED Simulation Results

Friday January 24 2025 17:10:00 UTC

GitHub Revision: `002bb67a7c`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.097m	5.334ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	2.140s	22.196us	5	5	100.00
V1	csr_rw	kmac_csr_rw	2.290s	27.592us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	13.930s	8.768ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	7.360s	403.357us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	3.110s	82.108us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	2.290s	27.592us	20	20	100.00
		kmac_csr_aliasing	7.360s	403.357us	5	5	100.00
V1	mem_walk	kmac_mem_walk	1.750s	11.970us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	2.230s	47.771us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	41.810m	445.190ms	50	50	100.00
V2	burst_write	kmac_burst_write	16.603m	57.945ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	29.203m	92.277ms	5	5	100.00
		kmac_test_vectors_sha3_256	19.607m	17.284ms	5	5	100.00
		kmac_test_vectors_sha3_384	21.889m	131.897ms	5	5	100.00
		kmac_test_vectors_sha3_512	12.336m	36.341ms	5	5	100.00
		kmac_test_vectors_shake_128	24.170m	80.392ms	5	5	100.00
		kmac_test_vectors_shake_256	27.654m	342.824ms	5	5	100.00
		kmac_test_vectors_kmac	4.200s	700.712us	5	5	100.00
		kmac_test_vectors_kmac_xof	3.680s	131.151us	5	5	100.00
V2	sideload	kmac_sideload	5.939m	245.746ms	50	50	100.00
V2	app	kmac_app	4.269m	12.966ms	50	50	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	4.677m	71.819ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	4.358m	219.169ms	50	50	100.00
V2	error	kmac_error	5.356m	118.082ms	50	50	100.00
V2	key_error	kmac_key_error	19.070s	6.405ms	50	50	100.00
V2	sideload_invalid	kmac_sideload_invalid	8.450s	1.527ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	33.110s	6.376ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	17.160s	3.483ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.090m	85.480ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	22.870s	1.447ms	50	50	100.00
V2	stress_all	kmac_stress_all	34.326m	417.535ms	50	50	100.00
V2	intr_test	kmac_intr_test	2.070s	36.804us	50	50	100.00
V2	alert_test	kmac_alert_test	2.350s	185.837us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.890s	368.235us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.890s	368.235us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	2.140s	22.196us	5	5	100.00
		kmac_csr_rw	2.290s	27.592us	20	20	100.00
		kmac_csr_aliasing	7.360s	403.357us	5	5	100.00
		kmac_same_csr_outstanding	3.100s	124.740us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	2.140s	22.196us	5	5	100.00
		kmac_csr_rw	2.290s	27.592us	20	20	100.00
		kmac_csr_aliasing	7.360s	403.357us	5	5	100.00
		kmac_same_csr_outstanding	3.100s	124.740us	20	20	100.00
V2		TOTAL			740	740	100.00
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.980s	120.184us	9	20	45.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.980s	120.184us	9	20	45.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.980s	120.184us	9	20	45.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.980s	120.184us	9	20	45.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	7.660s	223.815us	5	20	25.00
V2S	tl_intg_err	kmac_sec_cm	4.311m	4.517ms	5	5	100.00
		kmac_tl_intg_err	9.500s	373.746us	13	20	65.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	9.500s	373.746us	13	20	65.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	22.870s	1.447ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.097m	5.334ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	5.939m	245.746ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.980s	120.184us	9	20	45.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	4.311m	4.517ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	4.311m	4.517ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	4.311m	4.517ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.097m	5.334ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	22.870s	1.447ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	4.311m	4.517ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	4.725m	64.962ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.097m	5.334ms	50	50	100.00
V2S		TOTAL			42	75	56.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	1.613m	13.807ms	6	10	60.00
V3		TOTAL			6	10	60.00
		TOTAL			903	940	96.06

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.34	99.14	94.44	99.89	79.58	97.10	99.38	97.88

Failure Buckets

UVM_FATAL (alert_receiver_driver.sv:145) [driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q

has 18 failures:

Test kmac_shadow_reg_errors_with_csr_rw has 7 failures.

0.kmac_shadow_reg_errors_with_csr_rw.105669531443166779865280022062542058899611997892810016192075011921169394660095
Line 75, in log /nightly/runs/opentitan/scratch/master/kmac_masked-sim-vcs/0.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

  UVM_FATAL @  46905395 ps: (alert_receiver_driver.sv:145) [uvm_test_top.env.m_alert_agent_fatal_fault_err.driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q
  UVM_INFO @  46905395 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.kmac_shadow_reg_errors_with_csr_rw.99634965165057200438799171934962785876080498494967723922005074754355920381557
Line 75, in log /nightly/runs/opentitan/scratch/master/kmac_masked-sim-vcs/4.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

  UVM_FATAL @  85208615 ps: (alert_receiver_driver.sv:145) [uvm_test_top.env.m_alert_agent_fatal_fault_err.driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q
  UVM_INFO @  85208615 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

Test kmac_shadow_reg_errors has 11 failures.

1.kmac_shadow_reg_errors.35763854742784606519935066203677498354688723344950577146041460405784236747153
Line 76, in log /nightly/runs/opentitan/scratch/master/kmac_masked-sim-vcs/1.kmac_shadow_reg_errors/latest/run.log

  UVM_FATAL @ 275066861 ps: (alert_receiver_driver.sv:145) [uvm_test_top.env.m_alert_agent_fatal_fault_err.driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q
  UVM_INFO @ 275066861 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.kmac_shadow_reg_errors.81953782704140228865320584881835874821906805081719195038999898602609387320714
Line 76, in log /nightly/runs/opentitan/scratch/master/kmac_masked-sim-vcs/2.kmac_shadow_reg_errors/latest/run.log

  UVM_FATAL @ 109611364 ps: (alert_receiver_driver.sv:145) [uvm_test_top.env.m_alert_agent_fatal_fault_err.driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q
  UVM_INFO @ 109611364 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 9 more failures.

Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 15 failures:

Test kmac_tl_intg_err has 7 failures.

0.kmac_tl_intg_err.93281339493353937301327021615465385752810428433245505090052788933962357197119
Line 90, in log /nightly/runs/opentitan/scratch/master/kmac_masked-sim-vcs/0.kmac_tl_intg_err/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[40] & 'hffffffff)))'
  UVM_ERROR @  39246237 ps: (kmac_csr_assert_fpv.sv:497) [ASSERT FAILED] prefix_1_rd_A
  UVM_INFO @  39246237 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.kmac_tl_intg_err.91248748960424107578318896475682762324766311112670785870676287887486765986326
Line 82, in log /nightly/runs/opentitan/scratch/master/kmac_masked-sim-vcs/3.kmac_tl_intg_err/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[41] & 'hffffffff)))'
  UVM_ERROR @  13386804 ps: (kmac_csr_assert_fpv.sv:502) [ASSERT FAILED] prefix_2_rd_A
  UVM_INFO @  13386804 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

Test kmac_shadow_reg_errors_with_csr_rw has 8 failures.

1.kmac_shadow_reg_errors_with_csr_rw.108835760091763991322354969798638864407924303764942021971973681608599237391294
Line 76, in log /nightly/runs/opentitan/scratch/master/kmac_masked-sim-vcs/1.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[46] & 'hffffffff)))'
  UVM_ERROR @   8518527 ps: (kmac_csr_assert_fpv.sv:527) [ASSERT FAILED] prefix_7_rd_A
  UVM_INFO @   8518527 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.kmac_shadow_reg_errors_with_csr_rw.98992206255986229698758300634973559813747424187826212604293694817363844829911
Line 76, in log /nightly/runs/opentitan/scratch/master/kmac_masked-sim-vcs/2.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[46] & 'hffffffff)))'
  UVM_ERROR @  52217860 ps: (kmac_csr_assert_fpv.sv:527) [ASSERT FAILED] prefix_7_rd_A
  UVM_INFO @  52217860 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 6 more failures.

UVM_ERROR (kmac_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 4 failures:
- Test kmac_stress_all_with_rand_reset has 4 failures.
  - 1.kmac_stress_all_with_rand_reset.63360927470537629281878133526027561252287474716270784853418398290430092958344
    Line 94, in log /nightly/runs/opentitan/scratch/master/kmac_masked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2766679002 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483768 [0x80000078]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 2766679002 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.kmac_stress_all_with_rand_reset.85916344522546525118362576533757590746764108232619695709904112502988804600247
    Line 84, in log /nightly/runs/opentitan/scratch/master/kmac_masked-sim-vcs/3.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 503850409 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483760 [0x80000070]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 503850409 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.