002bb67a7c| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | kmac_smoke | 44.910s | 3.880ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | kmac_csr_hw_reset | 2.470s | 29.062us | 5 | 5 | 100.00 |
| V1 | csr_rw | kmac_csr_rw | 2.150s | 123.005us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | kmac_csr_bit_bash | 15.440s | 8.454ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | kmac_csr_aliasing | 7.010s | 2.521ms | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | kmac_csr_mem_rw_with_rand_reset | 2.870s | 201.222us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | kmac_csr_rw | 2.150s | 123.005us | 20 | 20 | 100.00 |
| kmac_csr_aliasing | 7.010s | 2.521ms | 5 | 5 | 100.00 | ||
| V1 | mem_walk | kmac_mem_walk | 1.750s | 53.032us | 5 | 5 | 100.00 |
| V1 | mem_partial_access | kmac_mem_partial_access | 1.990s | 128.083us | 5 | 5 | 100.00 |
| V1 | TOTAL | 115 | 115 | 100.00 | |||
| V2 | long_msg_and_output | kmac_long_msg_and_output | 40.283m | 130.788ms | 50 | 50 | 100.00 |
| V2 | burst_write | kmac_burst_write | 12.023m | 74.448ms | 50 | 50 | 100.00 |
| V2 | test_vectors | kmac_test_vectors_sha3_224 | 23.822m | 63.506ms | 5 | 5 | 100.00 |
| kmac_test_vectors_sha3_256 | 21.303m | 228.167ms | 5 | 5 | 100.00 | ||
| kmac_test_vectors_sha3_384 | 18.534m | 68.253ms | 5 | 5 | 100.00 | ||
| kmac_test_vectors_sha3_512 | 13.243m | 202.019ms | 5 | 5 | 100.00 | ||
| kmac_test_vectors_shake_128 | 28.231m | 145.945ms | 5 | 5 | 100.00 | ||
| kmac_test_vectors_shake_256 | 23.799m | 89.970ms | 5 | 5 | 100.00 | ||
| kmac_test_vectors_kmac | 3.930s | 351.647us | 5 | 5 | 100.00 | ||
| kmac_test_vectors_kmac_xof | 3.480s | 405.268us | 5 | 5 | 100.00 | ||
| V2 | sideload | kmac_sideload | 5.034m | 20.538ms | 50 | 50 | 100.00 |
| V2 | app | kmac_app | 3.657m | 32.335ms | 50 | 50 | 100.00 |
| V2 | app_with_partial_data | kmac_app_with_partial_data | 3.118m | 6.460ms | 10 | 10 | 100.00 |
| V2 | entropy_refresh | kmac_entropy_refresh | 4.339m | 193.728ms | 50 | 50 | 100.00 |
| V2 | error | kmac_error | 5.063m | 62.260ms | 49 | 50 | 98.00 |
| V2 | key_error | kmac_key_error | 16.360s | 24.926ms | 50 | 50 | 100.00 |
| V2 | sideload_invalid | kmac_sideload_invalid | 1.923m | 10.074ms | 34 | 50 | 68.00 |
| V2 | edn_timeout_error | kmac_edn_timeout_error | 25.420s | 1.365ms | 20 | 20 | 100.00 |
| V2 | entropy_mode_error | kmac_entropy_mode_error | 29.710s | 10.127ms | 20 | 20 | 100.00 |
| V2 | entropy_ready_error | kmac_entropy_ready_error | 37.020s | 10.037ms | 10 | 10 | 100.00 |
| V2 | lc_escalation | kmac_lc_escalation | 24.260s | 940.233us | 50 | 50 | 100.00 |
| V2 | stress_all | kmac_stress_all | 26.496m | 933.433ms | 50 | 50 | 100.00 |
| V2 | intr_test | kmac_intr_test | 2.050s | 47.176us | 50 | 50 | 100.00 |
| V2 | alert_test | kmac_alert_test | 2.310s | 148.234us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | kmac_tl_errors | 3.920s | 690.141us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | kmac_tl_errors | 3.920s | 690.141us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | kmac_csr_hw_reset | 2.470s | 29.062us | 5 | 5 | 100.00 |
| kmac_csr_rw | 2.150s | 123.005us | 20 | 20 | 100.00 | ||
| kmac_csr_aliasing | 7.010s | 2.521ms | 5 | 5 | 100.00 | ||
| kmac_same_csr_outstanding | 3.250s | 483.552us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | kmac_csr_hw_reset | 2.470s | 29.062us | 5 | 5 | 100.00 |
| kmac_csr_rw | 2.150s | 123.005us | 20 | 20 | 100.00 | ||
| kmac_csr_aliasing | 7.010s | 2.521ms | 5 | 5 | 100.00 | ||
| kmac_same_csr_outstanding | 3.250s | 483.552us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 723 | 740 | 97.70 | |||
| V2S | shadow_reg_update_error | kmac_shadow_reg_errors | 2.950s | 111.532us | 11 | 20 | 55.00 |
| V2S | shadow_reg_read_clear_staged_value | kmac_shadow_reg_errors | 2.950s | 111.532us | 11 | 20 | 55.00 |
| V2S | shadow_reg_storage_error | kmac_shadow_reg_errors | 2.950s | 111.532us | 11 | 20 | 55.00 |
| V2S | shadowed_reset_glitch | kmac_shadow_reg_errors | 2.950s | 111.532us | 11 | 20 | 55.00 |
| V2S | shadow_reg_update_error_with_csr_rw | kmac_shadow_reg_errors_with_csr_rw | 6.490s | 718.058us | 6 | 20 | 30.00 |
| V2S | tl_intg_err | kmac_sec_cm | 4.437m | 3.738ms | 5 | 5 | 100.00 |
| kmac_tl_intg_err | 9.360s | 196.551us | 18 | 20 | 90.00 | ||
| V2S | sec_cm_bus_integrity | kmac_tl_intg_err | 9.360s | 196.551us | 18 | 20 | 90.00 |
| V2S | sec_cm_lc_escalate_en_intersig_mubi | kmac_lc_escalation | 24.260s | 940.233us | 50 | 50 | 100.00 |
| V2S | sec_cm_sw_key_key_masking | kmac_smoke | 44.910s | 3.880ms | 50 | 50 | 100.00 |
| V2S | sec_cm_key_sideload | kmac_sideload | 5.034m | 20.538ms | 50 | 50 | 100.00 |
| V2S | sec_cm_cfg_shadowed_config_shadow | kmac_shadow_reg_errors | 2.950s | 111.532us | 11 | 20 | 55.00 |
| V2S | sec_cm_fsm_sparse | kmac_sec_cm | 4.437m | 3.738ms | 5 | 5 | 100.00 |
| V2S | sec_cm_ctr_redun | kmac_sec_cm | 4.437m | 3.738ms | 5 | 5 | 100.00 |
| V2S | sec_cm_packer_ctr_redun | kmac_sec_cm | 4.437m | 3.738ms | 5 | 5 | 100.00 |
| V2S | sec_cm_cfg_shadowed_config_regwen | kmac_smoke | 44.910s | 3.880ms | 50 | 50 | 100.00 |
| V2S | sec_cm_fsm_global_esc | kmac_lc_escalation | 24.260s | 940.233us | 50 | 50 | 100.00 |
| V2S | sec_cm_fsm_local_esc | kmac_sec_cm | 4.437m | 3.738ms | 5 | 5 | 100.00 |
| V2S | sec_cm_absorbed_ctrl_mubi | kmac_mubi | 3.386m | 67.207ms | 10 | 10 | 100.00 |
| V2S | sec_cm_sw_cmd_ctrl_sparse | kmac_smoke | 44.910s | 3.880ms | 50 | 50 | 100.00 |
| V2S | TOTAL | 50 | 75 | 66.67 | |||
| V3 | stress_all_with_rand_reset | kmac_stress_all_with_rand_reset | 1.660m | 19.610ms | 4 | 10 | 40.00 |
| V3 | TOTAL | 4 | 10 | 40.00 | |||
| TOTAL | 892 | 940 | 94.89 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 93.89 | 97.54 | 94.39 | 100.00 | 73.55 | 95.99 | 99.35 | 96.43 |
UVM_FATAL (alert_receiver_driver.sv:145) [driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q has 15 failures:
0.kmac_shadow_reg_errors.86126235859332645168925237251368136299205116422576633714905644482801781106636
Line 85, in log /nightly/runs/opentitan/scratch/master/kmac_unmasked-sim-vcs/0.kmac_shadow_reg_errors/latest/run.log
UVM_FATAL @ 63475864 ps: (alert_receiver_driver.sv:145) [uvm_test_top.env.m_alert_agent_fatal_fault_err.driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q
UVM_INFO @ 63475864 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.kmac_shadow_reg_errors.40940695353469463303532162091435828168082890741366038189791919351022084862633
Line 85, in log /nightly/runs/opentitan/scratch/master/kmac_unmasked-sim-vcs/1.kmac_shadow_reg_errors/latest/run.log
UVM_FATAL @ 21614075 ps: (alert_receiver_driver.sv:145) [uvm_test_top.env.m_alert_agent_fatal_fault_err.driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q
UVM_INFO @ 21614075 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 7 more failures.
0.kmac_shadow_reg_errors_with_csr_rw.47205634095588433964133591524785482763722936524670991698813204239659921317331
Line 85, in log /nightly/runs/opentitan/scratch/master/kmac_unmasked-sim-vcs/0.kmac_shadow_reg_errors_with_csr_rw/latest/run.log
UVM_FATAL @ 70087024 ps: (alert_receiver_driver.sv:145) [uvm_test_top.env.m_alert_agent_fatal_fault_err.driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q
UVM_INFO @ 70087024 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.kmac_shadow_reg_errors_with_csr_rw.17925317699666623003393896217888243338194167814917333457864905598376970557211
Line 85, in log /nightly/runs/opentitan/scratch/master/kmac_unmasked-sim-vcs/2.kmac_shadow_reg_errors_with_csr_rw/latest/run.log
UVM_FATAL @ 36050599 ps: (alert_receiver_driver.sv:145) [uvm_test_top.env.m_alert_agent_fatal_fault_err.driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q
UVM_INFO @ 36050599 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 10 failures:
Test kmac_tl_intg_err has 2 failures.
2.kmac_tl_intg_err.66640792763103974758176281628405014218344029153774772249597834599873312852726
Line 101, in log /nightly/runs/opentitan/scratch/master/kmac_unmasked-sim-vcs/2.kmac_tl_intg_err/latest/run.log
Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[47] & 'hffffffff)))'
UVM_ERROR @ 136338397 ps: (kmac_csr_assert_fpv.sv:532) [ASSERT FAILED] prefix_8_rd_A
UVM_INFO @ 136338397 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
13.kmac_tl_intg_err.83591451357299612299076102811930832037496398565565107855662097576476866701012
Line 75, in log /nightly/runs/opentitan/scratch/master/kmac_unmasked-sim-vcs/13.kmac_tl_intg_err/latest/run.log
Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[41] & 'hffffffff)))'
UVM_ERROR @ 17533346 ps: (kmac_csr_assert_fpv.sv:502) [ASSERT FAILED] prefix_2_rd_A
UVM_INFO @ 17533346 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test kmac_shadow_reg_errors_with_csr_rw has 8 failures.
7.kmac_shadow_reg_errors_with_csr_rw.18338576841023740083228146032886797523817068301600566161247425143034253162827
Line 86, in log /nightly/runs/opentitan/scratch/master/kmac_unmasked-sim-vcs/7.kmac_shadow_reg_errors_with_csr_rw/latest/run.log
Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[49] & 'hffffffff)))'
UVM_ERROR @ 64264779 ps: (kmac_csr_assert_fpv.sv:542) [ASSERT FAILED] prefix_10_rd_A
UVM_INFO @ 64264779 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
8.kmac_shadow_reg_errors_with_csr_rw.47472902787389987542509685079446053253947104829392996895482340387898308892286
Line 86, in log /nightly/runs/opentitan/scratch/master/kmac_unmasked-sim-vcs/8.kmac_shadow_reg_errors_with_csr_rw/latest/run.log
Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[47] & 'hffffffff)))'
UVM_ERROR @ 420358097 ps: (kmac_csr_assert_fpv.sv:532) [ASSERT FAILED] prefix_8_rd_A
UVM_INFO @ 420358097 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 6 more failures.
UVM_ERROR (kmac_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 6 failures:
0.kmac_stress_all_with_rand_reset.55377196684069294976139366475399811177078878020588820792762710599236470482142
Line 150, in log /nightly/runs/opentitan/scratch/master/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 4937738762 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483760 [0x80000070]) reg name: kmac_reg_block.err_code
UVM_INFO @ 4937738762 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.kmac_stress_all_with_rand_reset.91873584955154191028648062489227959842910288799896325178523803230270522839452
Line 94, in log /nightly/runs/opentitan/scratch/master/kmac_unmasked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1216532802 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483656 [0x80000008]) reg name: kmac_reg_block.err_code
UVM_INFO @ 1216532802 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=2) has 5 failures:
18.kmac_sideload_invalid.112232533408011465762078631646603564897134492970835881473589795195545851312405
Line 73, in log /nightly/runs/opentitan/scratch/master/kmac_unmasked-sim-vcs/18.kmac_sideload_invalid/latest/run.log
UVM_FATAL @ 10040951606 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0x8fa76000, Comparison=CompareOpEq, exp_data=0x1, call_count=2)
UVM_INFO @ 10040951606 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
20.kmac_sideload_invalid.46486544816082800686611474779175762059281761740032012999650089594992888915995
Line 73, in log /nightly/runs/opentitan/scratch/master/kmac_unmasked-sim-vcs/20.kmac_sideload_invalid/latest/run.log
UVM_FATAL @ 10039457917 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0xe90a5000, Comparison=CompareOpEq, exp_data=0x1, call_count=2)
UVM_INFO @ 10039457917 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=5) has 2 failures:
10.kmac_sideload_invalid.90453307695327415311134179077991432767211734374094777908102178660521347829231
Line 77, in log /nightly/runs/opentitan/scratch/master/kmac_unmasked-sim-vcs/10.kmac_sideload_invalid/latest/run.log
UVM_FATAL @ 10030683660 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0x78937000, Comparison=CompareOpEq, exp_data=0x1, call_count=5)
UVM_INFO @ 10030683660 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
38.kmac_sideload_invalid.83379159730374602289216331018266272202031295006244330366679285885083468660082
Line 76, in log /nightly/runs/opentitan/scratch/master/kmac_unmasked-sim-vcs/38.kmac_sideload_invalid/latest/run.log
UVM_FATAL @ 10048506644 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0xda3a6000, Comparison=CompareOpEq, exp_data=0x1, call_count=5)
UVM_INFO @ 10048506644 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) has 2 failures:
23.kmac_sideload_invalid.114780731181904288025379656579764453852181229486719249437363629668144149861827
Line 74, in log /nightly/runs/opentitan/scratch/master/kmac_unmasked-sim-vcs/23.kmac_sideload_invalid/latest/run.log
UVM_FATAL @ 10087456947 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0xd2be9000, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
UVM_INFO @ 10087456947 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
33.kmac_sideload_invalid.5629098110053176609767144531676769055124111985291207536453402007360314889712
Line 74, in log /nightly/runs/opentitan/scratch/master/kmac_unmasked-sim-vcs/33.kmac_sideload_invalid/latest/run.log
UVM_FATAL @ 10049841744 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0x1de38000, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
UVM_INFO @ 10049841744 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=14) has 2 failures:
28.kmac_sideload_invalid.90037256334130086060040467425494439472411323860829662805531316625633590671219
Line 86, in log /nightly/runs/opentitan/scratch/master/kmac_unmasked-sim-vcs/28.kmac_sideload_invalid/latest/run.log
UVM_FATAL @ 10074366996 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0x79f19000, Comparison=CompareOpEq, exp_data=0x1, call_count=14)
UVM_INFO @ 10074366996 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
35.kmac_sideload_invalid.5688585483328074522555484349468768810193647975565044980621626897889087995050
Line 87, in log /nightly/runs/opentitan/scratch/master/kmac_unmasked-sim-vcs/35.kmac_sideload_invalid/latest/run.log
UVM_FATAL @ 10097327952 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0x99fb7000, Comparison=CompareOpEq, exp_data=0x1, call_count=14)
UVM_INFO @ 10097327952 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=7) has 1 failures:
2.kmac_sideload_invalid.105020546128890388951293975689379962833470183259568245727392294887327680683193
Line 80, in log /nightly/runs/opentitan/scratch/master/kmac_unmasked-sim-vcs/2.kmac_sideload_invalid/latest/run.log
UVM_FATAL @ 10087635283 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0xf36c0000, Comparison=CompareOpEq, exp_data=0x1, call_count=7)
UVM_INFO @ 10087635283 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=19) has 1 failures:
8.kmac_sideload_invalid.75107011502478340513522865486267470847910856792120439158862253314463373294675
Line 94, in log /nightly/runs/opentitan/scratch/master/kmac_unmasked-sim-vcs/8.kmac_sideload_invalid/latest/run.log
UVM_FATAL @ 10906232250 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0x994d5000, Comparison=CompareOpEq, exp_data=0x1, call_count=19)
UVM_INFO @ 10906232250 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
20.kmac_error.75309911625407676897731205015988354764190024482758395179907761885592587128037
Line 206, in log /nightly/runs/opentitan/scratch/master/kmac_unmasked-sim-vcs/20.kmac_error/latest/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=8) has 1 failures:
29.kmac_sideload_invalid.63951616794863209672085494675243650501068657271907605577229757120195535563829
Line 80, in log /nightly/runs/opentitan/scratch/master/kmac_unmasked-sim-vcs/29.kmac_sideload_invalid/latest/run.log
UVM_FATAL @ 10265658699 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0xdab91000, Comparison=CompareOpEq, exp_data=0x1, call_count=8)
UVM_INFO @ 10265658699 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=28) has 1 failures:
34.kmac_sideload_invalid.31349119886264841268613180307761691009677278005012254419862995460706368920021
Line 103, in log /nightly/runs/opentitan/scratch/master/kmac_unmasked-sim-vcs/34.kmac_sideload_invalid/latest/run.log
UVM_FATAL @ 10368301458 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0x51f0b000, Comparison=CompareOpEq, exp_data=0x1, call_count=28)
UVM_INFO @ 10368301458 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=13) has 1 failures:
48.kmac_sideload_invalid.18090152632012719986068275101388399170523213017796892443837977321759382792194
Line 84, in log /nightly/runs/opentitan/scratch/master/kmac_unmasked-sim-vcs/48.kmac_sideload_invalid/latest/run.log
UVM_FATAL @ 10109419154 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0xad088000, Comparison=CompareOpEq, exp_data=0x1, call_count=13)
UVM_INFO @ 10109419154 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---