OTBN Simulation Results

Friday January 24 2025 17:10:00 UTC

GitHub Revision: `002bb67a7c`

Branch: master

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	12.000s	139.158us	1	1	100.00
V1	single_binary	otbn_single	1.400m	893.863us	100	100	100.00
V1	csr_hw_reset	otbn_csr_hw_reset	12.000s	35.542us	5	5	100.00
V1	csr_rw	otbn_csr_rw	10.000s	30.060us	20	20	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	11.000s	333.438us	5	5	100.00
V1	csr_aliasing	otbn_csr_aliasing	8.000s	42.099us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	10.000s	38.034us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	10.000s	30.060us	20	20	100.00
		otbn_csr_aliasing	8.000s	42.099us	5	5	100.00
V1	mem_walk	otbn_mem_walk	41.000s	1.865ms	5	5	100.00
V1	mem_partial_access	otbn_mem_partial_access	23.000s	2.676ms	5	5	100.00
V1		TOTAL			166	166	100.00
V2	reset_recovery	otbn_reset	33.000s	117.547us	10	10	100.00
V2	multi_error	otbn_multi_err	45.000s	650.100us	1	1	100.00
V2	back_to_back	otbn_multi	14.083m	5.394ms	10	10	100.00
V2	stress_all	otbn_stress_all	1.517m	451.583us	10	10	100.00
V2	lc_escalation	otbn_escalate	22.000s	289.942us	60	60	100.00
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	10.000s	56.597us	5	5	100.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	24.000s	126.553us	10	10	100.00
V2	alert_test	otbn_alert_test	11.000s	32.116us	50	50	100.00
V2	intr_test	otbn_intr_test	8.000s	32.982us	50	50	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	14.000s	90.700us	20	20	100.00
V2	tl_d_illegal_access	otbn_tl_errors	14.000s	90.700us	20	20	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	12.000s	35.542us	5	5	100.00
		otbn_csr_rw	10.000s	30.060us	20	20	100.00
		otbn_csr_aliasing	8.000s	42.099us	5	5	100.00
		otbn_same_csr_outstanding	10.000s	40.936us	20	20	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	12.000s	35.542us	5	5	100.00
		otbn_csr_rw	10.000s	30.060us	20	20	100.00
		otbn_csr_aliasing	8.000s	42.099us	5	5	100.00
		otbn_same_csr_outstanding	10.000s	40.936us	20	20	100.00
V2		TOTAL			246	246	100.00
V2S	mem_integrity	otbn_imem_err	14.000s	31.861us	10	10	100.00
		otbn_dmem_err	12.000s	41.360us	15	15	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	17.000s	58.993us	5	5	100.00
		otbn_controller_ispr_rdata_err	17.000s	69.770us	5	5	100.00
		otbn_mac_bignum_acc_err	16.000s	40.718us	5	5	100.00
		otbn_urnd_err	8.000s	32.904us	2	2	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	9.000s	17.932us	5	5	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	9.000s	49.090us	2	2	100.00
V2S	otbn_non_sec_partial_wipe	otbn_partial_wipe	14.000s	128.166us	10	10	100.00
V2S	tl_intg_err	otbn_sec_cm	4.267m	1.094ms	3	5	60.00
		otbn_tl_intg_err	46.000s	395.783us	20	20	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	57.000s	370.675us	20	20	100.00
V2S	prim_fsm_check	otbn_sec_cm	4.267m	1.094ms	3	5	60.00
V2S	prim_count_check	otbn_sec_cm	4.267m	1.094ms	3	5	60.00
V2S	sec_cm_mem_scramble	otbn_smoke	12.000s	139.158us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	12.000s	41.360us	15	15	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	14.000s	31.861us	10	10	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	46.000s	395.783us	20	20	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	22.000s	289.942us	60	60	100.00
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	14.000s	31.861us	10	10	100.00
		otbn_dmem_err	12.000s	41.360us	15	15	100.00
		otbn_zero_state_err_urnd	10.000s	56.597us	5	5	100.00
		otbn_illegal_mem_acc	9.000s	17.932us	5	5	100.00
		otbn_sec_cm	4.267m	1.094ms	3	5	60.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	4.267m	1.094ms	3	5	60.00
V2S	sec_cm_scramble_key_sideload	otbn_single	1.400m	893.863us	100	100	100.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	14.000s	31.861us	10	10	100.00
		otbn_dmem_err	12.000s	41.360us	15	15	100.00
		otbn_zero_state_err_urnd	10.000s	56.597us	5	5	100.00
		otbn_illegal_mem_acc	9.000s	17.932us	5	5	100.00
		otbn_sec_cm	4.267m	1.094ms	3	5	60.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	4.267m	1.094ms	3	5	60.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	22.000s	289.942us	60	60	100.00
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	14.000s	31.861us	10	10	100.00
		otbn_dmem_err	12.000s	41.360us	15	15	100.00
		otbn_zero_state_err_urnd	10.000s	56.597us	5	5	100.00
		otbn_illegal_mem_acc	9.000s	17.932us	5	5	100.00
		otbn_sec_cm	4.267m	1.094ms	3	5	60.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	4.267m	1.094ms	3	5	60.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	1.400m	893.863us	100	100	100.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	11.000s	53.141us	12	12	100.00
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	12.000s	24.193us	5	5	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	27.000s	75.641us	5	5	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	27.000s	75.641us	5	5	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	14.000s	21.544us	10	10	100.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	4.267m	1.094ms	3	5	60.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	4.267m	1.094ms	3	5	60.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	18.000s	93.739us	10	10	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	4.267m	1.094ms	3	5	60.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	4.267m	1.094ms	3	5	60.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	15.000s	45.934us	5	5	100.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	15.000s	45.934us	5	5	100.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	15.000s	88.719us	4	7	57.14
V2S	sec_cm_data_mem_sec_wipe	otbn_single	1.400m	893.863us	100	100	100.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	1.400m	893.863us	100	100	100.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	1.400m	893.863us	100	100	100.00
V2S	sec_cm_write_mem_integrity	otbn_multi	14.083m	5.394ms	10	10	100.00
V2S	sec_cm_ctrl_flow_count	otbn_single	1.400m	893.863us	100	100	100.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	1.400m	893.863us	100	100	100.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	16.000s	355.146us	5	5	100.00
V2S	sec_cm_key_sideload	otbn_single	1.400m	893.863us	100	100	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	4.267m	1.094ms	3	5	60.00
V2S		TOTAL			158	163	96.93
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	6.600m	2.704ms	1	10	10.00
V3		TOTAL			1	10	10.00
		TOTAL			571	585	97.61

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
99.06	99.60	95.35	99.70	93.37	93.41	100.00	98.16	99.58

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:891) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 7 failures:
- Test otbn_stress_all_with_rand_reset has 7 failures.
  - 0.otbn_stress_all_with_rand_reset.95127090474387523226404573468186012324870081239108887679788423722052582651322
    Line 394, in log /nightly/runs/opentitan/scratch/master/otbn-sim-xcelium/0.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2703647159 ps: (cip_base_vseq.sv:891) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2703647159 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.otbn_stress_all_with_rand_reset.57277766901655851240217378007864674075903694440398156721956297485464103716212
    Line 152, in log /nightly/runs/opentitan/scratch/master/otbn-sim-xcelium/1.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 112130218 ps: (cip_base_vseq.sv:891) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 112130218 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 5 more failures.

xmsim: *E,ASRTST (/nightly/runs/opentitan/scratch/master/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 3 failures:

Test otbn_sec_wipe_err has 3 failures.

2.otbn_sec_wipe_err.48558727119458668021068288751850350587232216365606110407460693241258242702426
Line 106, in log /nightly/runs/opentitan/scratch/master/otbn-sim-xcelium/2.otbn_sec_wipe_err/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/opentitan/scratch/master/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 86717307 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  86717307 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  86717307 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

5.otbn_sec_wipe_err.88932821609324715589320087603866263041192087161912305385172122331654340157698
Line 113, in log /nightly/runs/opentitan/scratch/master/otbn-sim-xcelium/5.otbn_sec_wipe_err/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/opentitan/scratch/master/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 88719488 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  88719488 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  88719488 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

xmsim: *E,ASRTST (/nightly/runs/opentitan/scratch/master/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_*/rtl/otbn.sv,1383): Assertion ErrBitsKnown_A has failed has 2 failures:

Test otbn_sec_cm has 2 failures.

1.otbn_sec_cm.90934050911567958928800736876095817393133486621596623802687028156648784961738
Line 120, in log /nightly/runs/opentitan/scratch/master/otbn-sim-xcelium/1.otbn_sec_cm/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/opentitan/scratch/master/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1383): (time 160431955 PS) Assertion tb.dut.ErrBitsKnown_A has failed
  xmsim: *E,ASRTST (/nightly/runs/opentitan/scratch/master/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,948): (time 160431955 PS) Assertion tb.dut.u_otbn_core.DoneOKnown_A has failed
  xmsim: *E,ASRTST (/nightly/runs/opentitan/scratch/master/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,949): (time 160431955 PS) Assertion tb.dut.u_otbn_core.ImemReqOKnown_A has failed
  xmsim: *E,ASRTST (/nightly/runs/opentitan/scratch/master/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,950): (time 160431955 PS) Assertion tb.dut.u_otbn_core.ImemAddrOKnown_AKnownEnable has failed
  xmsim: *E,ASRTST (/nightly/runs/opentitan/scratch/master/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 160431955 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed

2.otbn_sec_cm.50380132194642644888001167869304685300275326288323295513564240617840116777297
Line 104, in log /nightly/runs/opentitan/scratch/master/otbn-sim-xcelium/2.otbn_sec_cm/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/opentitan/scratch/master/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1383): (time 23766175 PS) Assertion tb.dut.ErrBitsKnown_A has failed
  xmsim: *E,ASRTST (/nightly/runs/opentitan/scratch/master/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,948): (time 23766175 PS) Assertion tb.dut.u_otbn_core.DoneOKnown_A has failed
  xmsim: *E,ASRTST (/nightly/runs/opentitan/scratch/master/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,949): (time 23766175 PS) Assertion tb.dut.u_otbn_core.ImemReqOKnown_A has failed
  xmsim: *E,ASRTST (/nightly/runs/opentitan/scratch/master/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,950): (time 23766175 PS) Assertion tb.dut.u_otbn_core.ImemAddrOKnown_AKnownEnable has failed
  xmsim: *E,ASRTST (/nightly/runs/opentitan/scratch/master/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 23766175 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed

UVM_FATAL (otbn_base_vseq.sv:348) [otbn_imem_err_vseq] Check failed (!cfg.under_reset) has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 2.otbn_stress_all_with_rand_reset.78183718562387967901050474214603413854776312089402263869892505565895499736106
    Line 169, in log /nightly/runs/opentitan/scratch/master/otbn-sim-xcelium/2.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 661131887 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_imem_err_vseq] Check failed (!cfg.under_reset)
  UVM_INFO @ 661131887 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_base_vseq.sv:348) [otbn_dmem_err_vseq] Check failed (!cfg.under_reset) has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 4.otbn_stress_all_with_rand_reset.55594556236204013874543746760281789045704406878613872367744250820475727124035
    Line 366, in log /nightly/runs/opentitan/scratch/master/otbn-sim-xcelium/4.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 4009357656 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_dmem_err_vseq] Check failed (!cfg.under_reset)
  UVM_INFO @ 4009357656 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```