PATTGEN Simulation Results

Friday January 24 2025 17:10:00 UTC

GitHub Revision: `002bb67a7c`

Branch: master

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	17.000s	17.764us	50	50	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	16.000s	19.100us	5	5	100.00
V1	csr_rw	pattgen_csr_rw	12.000s	11.280us	20	20	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	13.000s	207.829us	5	5	100.00
V1	csr_aliasing	pattgen_csr_aliasing	10.000s	15.633us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	8.000s	26.999us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	12.000s	11.280us	20	20	100.00
		pattgen_csr_aliasing	10.000s	15.633us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	perf	pattgen_perf	1.983m	78.896ms	50	50	100.00
V2	cnt_rollover	cnt_rollover	1.200m	26.292ms	50	50	100.00
V2	error	pattgen_error	17.000s	22.267us	50	50	100.00
V2	stress_all	pattgen_stress_all	2.333m	8.767ms	50	50	100.00
V2	alert_test	pattgen_alert_test	15.000s	45.988us	50	50	100.00
V2	intr_test	pattgen_intr_test	19.000s	21.528us	50	50	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	22.000s	378.287us	20	20	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	22.000s	378.287us	20	20	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	16.000s	19.100us	5	5	100.00
		pattgen_csr_rw	12.000s	11.280us	20	20	100.00
		pattgen_csr_aliasing	10.000s	15.633us	5	5	100.00
		pattgen_same_csr_outstanding	10.000s	15.071us	20	20	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	16.000s	19.100us	5	5	100.00
		pattgen_csr_rw	12.000s	11.280us	20	20	100.00
		pattgen_csr_aliasing	10.000s	15.633us	5	5	100.00
		pattgen_same_csr_outstanding	10.000s	15.071us	20	20	100.00
V2		TOTAL			340	340	100.00
V2S	tl_intg_err	pattgen_tl_intg_err	21.000s	265.074us	20	20	100.00
		pattgen_sec_cm	17.000s	66.662us	5	5	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	21.000s	265.074us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	1.883m	5.011ms	0	50	0.00
V3		TOTAL			0	50	0.00
	Unmapped tests	pattgen_inactive_level	3.533m	10.022ms	45	50	90.00
		TOTAL			515	570	90.35

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.96	100.00	100.00	100.00	99.25	96.61	--	100.00	90.43

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:891) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 50 failures:

Test pattgen_stress_all_with_rand_reset has 50 failures.

0.pattgen_stress_all_with_rand_reset.32294727223577186646633193775460022508437749908939447979456329264661024684182
Line 237, in log /nightly/runs/opentitan/scratch/master/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2430481390 ps: (cip_base_vseq.sv:891) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 2430494104 ps: (cip_base_vseq.sv:795) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 2430494104 ps: (cip_base_vseq.sv:798) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Issuing reset for run 4/5
  UVM_INFO @ 2430639935 ps: (cip_base_vseq.sv:819) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

1.pattgen_stress_all_with_rand_reset.37004641582801619847261464051429873209255269185804681029298331087859695751083
Line 237, in log /nightly/runs/opentitan/scratch/master/pattgen-sim-xcelium/1.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 7796637523 ps: (cip_base_vseq.sv:891) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 7796686446 ps: (cip_base_vseq.sv:795) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 7796686446 ps: (cip_base_vseq.sv:798) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Issuing reset for run 4/5
  UVM_INFO @ 7796786446 ps: (cip_base_vseq.sv:819) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

... and 48 more failures.

UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=4) has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 23.pattgen_inactive_level.99296715564246722033814411577509805901821805096055894613226014623726429132268
    Line 96, in log /nightly/runs/opentitan/scratch/master/pattgen-sim-xcelium/23.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10002890844 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch1 (addr=0x9068b950, Comparison=CompareOpEq, exp_data=0x0, call_count=4)
  UVM_INFO @ 10002890844 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=11) has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 25.pattgen_inactive_level.84687586187534930690982626365822956346762128758571213947672611528189606794311
    Line 96, in log /nightly/runs/opentitan/scratch/master/pattgen-sim-xcelium/25.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10130786771 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x671ba490, Comparison=CompareOpEq, exp_data=0x0, call_count=11)
  UVM_INFO @ 10130786771 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=17) has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 31.pattgen_inactive_level.98568001013110956352757705835454949339260312671461407113126681779221487402069
    Line 96, in log /nightly/runs/opentitan/scratch/master/pattgen-sim-xcelium/31.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10040304344 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x195d3150, Comparison=CompareOpEq, exp_data=0x0, call_count=17)
  UVM_INFO @ 10040304344 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=25) has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 47.pattgen_inactive_level.80420784485597599063695050740125267335866036201842794767065658279986180633048
    Line 96, in log /nightly/runs/opentitan/scratch/master/pattgen-sim-xcelium/47.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10018515868 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x6af03250, Comparison=CompareOpEq, exp_data=0x0, call_count=25)
  UVM_INFO @ 10018515868 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=5) has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 48.pattgen_inactive_level.93054238862955039285823954297902569113614501257825318983944109671171136788130
    Line 96, in log /nightly/runs/opentitan/scratch/master/pattgen-sim-xcelium/48.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10021679404 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x51da4790, Comparison=CompareOpEq, exp_data=0x0, call_count=5)
  UVM_INFO @ 10021679404 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```