PWM Simulation Results

Friday January 24 2025 17:10:00 UTC

GitHub Revision: 002bb67a7c

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pwm_smoke	16.000s	1.059ms	10	10	100.00
V1	csr_hw_reset	pwm_csr_hw_reset	16.000s	101.627us	5	5	100.00
V1	csr_rw	pwm_csr_rw	16.000s	77.831us	20	20	100.00
V1	csr_bit_bash	pwm_csr_bit_bash	17.000s	1.426ms	5	5	100.00
V1	csr_aliasing	pwm_csr_aliasing	12.000s	27.229us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pwm_csr_mem_rw_with_rand_reset	12.000s	21.178us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pwm_csr_rw	16.000s	77.831us	20	20	100.00
		pwm_csr_aliasing	12.000s	27.229us	5	5	100.00
V1		TOTAL			65	65	100.00
V2	dutycycle	pwm_rand_output	46.000s	22.031ms	25	25	100.00
V2	pulse	pwm_rand_output	46.000s	22.031ms	25	25	100.00
V2	blink	pwm_rand_output	46.000s	22.031ms	25	25	100.00
V2	heartbeat	pwm_rand_output	46.000s	22.031ms	25	25	100.00
V2	resolution	pwm_rand_output	46.000s	22.031ms	25	25	100.00
V2	multi_channel	pwm_rand_output	46.000s	22.031ms	25	25	100.00
V2	polarity	pwm_rand_output	46.000s	22.031ms	25	25	100.00
V2	phase	pwm_rand_output	46.000s	22.031ms	25	25	100.00
		pwm_phase	52.000s	21.874ms	25	25	100.00
V2	lowpower	pwm_rand_output	46.000s	22.031ms	25	25	100.00
V2	perf	pwm_perf	49.000s	21.001ms	10	10	100.00
V2	regwen	pwm_regwen	2.700m	43.729ms	1	1	100.00
V2	stress_all	pwm_stress_all	2.650m	218.731ms	6	25	24.00
V2	alert_test	pwm_alert_test	12.000s	24.501us	50	50	100.00
V2	tl_d_oob_addr_access	pwm_tl_errors	18.000s	239.206us	20	20	100.00
V2	tl_d_illegal_access	pwm_tl_errors	18.000s	239.206us	20	20	100.00
V2	tl_d_outstanding_access	pwm_csr_hw_reset	16.000s	101.627us	5	5	100.00
		pwm_csr_rw	16.000s	77.831us	20	20	100.00
		pwm_csr_aliasing	12.000s	27.229us	5	5	100.00
		pwm_same_csr_outstanding	12.000s	23.867us	20	20	100.00
V2	tl_d_partial_access	pwm_csr_hw_reset	16.000s	101.627us	5	5	100.00
		pwm_csr_rw	16.000s	77.831us	20	20	100.00
		pwm_csr_aliasing	12.000s	27.229us	5	5	100.00
		pwm_same_csr_outstanding	12.000s	23.867us	20	20	100.00
V2		TOTAL			157	176	89.20
V2S	tl_intg_err	pwm_tl_intg_err	17.000s	73.704us	20	20	100.00
		pwm_sec_cm	16.000s	65.104us	5	5	100.00
V2S	sec_cm_bus_integrity	pwm_tl_intg_err	17.000s	73.704us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	heartbeat_wrap	pwm_heartbeat_wrap	50.000s	43.746ms	10	10	100.00
V3		TOTAL			10	10	100.00
		TOTAL			257	276	93.12

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
99.02	99.32	98.85	99.47	97.95	96.72	--	100.00	99.34

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:452) [pwm_common_vseq] Check failed (intr_csrs.size() > *) Called intr_test vseq without any interrupt register. has 19 failures:
  • Test pwm_stress_all has 19 failures.

    • 0.pwm_stress_all.84755983223281004747788163479682967219324403342824713488042725872291985994678
      Line 1232, in log /nightly/runs/opentitan/scratch/master/pwm-sim-xcelium/0.pwm_stress_all/latest/run.log

        UVM_ERROR @ 89590642421 ps: (cip_base_vseq.sv:452) [uvm_test_top.env.virtual_sequencer.pwm_common_vseq] Check failed (intr_csrs.size() > 0) Called intr_test vseq without any interrupt register.
        UVM_INFO @ 89590642421 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 2.pwm_stress_all.105161690748595161707932857044670634791252547308723569177133585750042853603553
      Line 86, in log /nightly/runs/opentitan/scratch/master/pwm-sim-xcelium/2.pwm_stress_all/latest/run.log

        UVM_ERROR @ 21423746427 ps: (cip_base_vseq.sv:452) [uvm_test_top.env.virtual_sequencer.pwm_common_vseq] Check failed (intr_csrs.size() > 0) Called intr_test vseq without any interrupt register.
        UVM_INFO @ 21423746427 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 17 more failures.