RV_TIMER Simulation Results

Friday January 24 2025 17:10:00 UTC

GitHub Revision: 002bb67a7c

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	29.435m	135.531ms	200	200	100.00
V1	csr_hw_reset	rv_timer_csr_hw_reset	1.740s	24.049us	5	5	100.00
V1	csr_rw	rv_timer_csr_rw	2.260s	16.360us	20	20	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	3.510s	1.489ms	5	5	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	1.930s	99.158us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	2.590s	34.198us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	2.260s	16.360us	20	20	100.00
		rv_timer_csr_aliasing	1.930s	99.158us	5	5	100.00
V1		TOTAL			255	255	100.00
V2	random_reset	rv_timer_random_reset	19.572m	227.612ms	50	50	100.00
V2	disabled	rv_timer_disabled	4.505m	207.979ms	48	50	96.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	11.297m	1.774s	50	50	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	11.297m	1.774s	50	50	100.00
V2	stress	rv_timer_stress_all	1.350h	2.501s	50	50	100.00
V2	intr_test	rv_timer_intr_test	2.050s	56.114us	50	50	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	3.290s	638.924us	20	20	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	3.290s	638.924us	20	20	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	1.740s	24.049us	5	5	100.00
		rv_timer_csr_rw	2.260s	16.360us	20	20	100.00
		rv_timer_csr_aliasing	1.930s	99.158us	5	5	100.00
		rv_timer_same_csr_outstanding	2.370s	112.744us	20	20	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	1.740s	24.049us	5	5	100.00
		rv_timer_csr_rw	2.260s	16.360us	20	20	100.00
		rv_timer_csr_aliasing	1.930s	99.158us	5	5	100.00
		rv_timer_same_csr_outstanding	2.370s	112.744us	20	20	100.00
V2		TOTAL			288	290	99.31
V2S	tl_intg_err	rv_timer_sec_cm	4.540s	201.781us	5	5	100.00
		rv_timer_tl_intg_err	5.990s	548.376us	20	20	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	5.990s	548.376us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	1.118m	17.880ms	9	50	18.00
V3		TOTAL			9	50	18.00
		TOTAL			577	620	93.06

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.66	99.29	99.36	100.00	--	100.00	100.00	99.32

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:890) [rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 41 failures:
  • Test rv_timer_stress_all_with_rand_reset has 41 failures.

    • 0.rv_timer_stress_all_with_rand_reset.58844826534284282291374440096432879058935666804796760592506803610699755143764
      Line 247, in log /nightly/runs/opentitan/scratch/master/rv_timer-sim-vcs/0.rv_timer_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 14954351184 ps: (cip_base_vseq.sv:890) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited 10052 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 14954351184 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.rv_timer_stress_all_with_rand_reset.20576116699146955272624075867391087393905540307519028713949562545263750212499
      Line 144, in log /nightly/runs/opentitan/scratch/master/rv_timer-sim-vcs/1.rv_timer_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 7150806033 ps: (cip_base_vseq.sv:890) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 7150806033 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 39 more failures.

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
  • Test rv_timer_disabled has 2 failures.

    • 17.rv_timer_disabled.32834602179150058459461632595841769200802138315453360233255158109623490529385
      Line 72, in log /nightly/runs/opentitan/scratch/master/rv_timer-sim-vcs/17.rv_timer_disabled/latest/run.log

        UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 45.rv_timer_disabled.26398156677695524808630439580120672984747209530786069574375308562842701960111
      Line 75, in log /nightly/runs/opentitan/scratch/master/rv_timer-sim-vcs/45.rv_timer_disabled/latest/run.log

        UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---