SPI_HOST Simulation Results

Friday January 24 2025 17:10:00 UTC

GitHub Revision: 002bb67a7c

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	6.333m	13.695ms	50	50	100.00
V1	csr_hw_reset	spi_host_csr_hw_reset	6.000s	45.188us	5	5	100.00
V1	csr_rw	spi_host_csr_rw	6.000s	57.630us	20	20	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	7.000s	298.658us	5	5	100.00
V1	csr_aliasing	spi_host_csr_aliasing	6.000s	18.863us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	6.000s	130.909us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	6.000s	57.630us	20	20	100.00
		spi_host_csr_aliasing	6.000s	18.863us	5	5	100.00
V1	mem_walk	spi_host_mem_walk	6.000s	103.028us	5	5	100.00
V1	mem_partial_access	spi_host_mem_partial_access	6.000s	36.263us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	performance	spi_host_performance	6.000s	61.085us	50	50	100.00
V2	error_event_intr	spi_host_overflow_underflow	2.000m	15.149ms	50	50	100.00
		spi_host_error_cmd	7.000s	35.597us	50	50	100.00
		spi_host_event	9.283m	21.210ms	50	50	100.00
V2	clock_rate	spi_host_speed	17.000s	1.524ms	50	50	100.00
V2	speed	spi_host_speed	17.000s	1.524ms	50	50	100.00
V2	chip_select_timing	spi_host_speed	17.000s	1.524ms	50	50	100.00
V2	sw_reset	spi_host_sw_reset	4.700m	10.003ms	49	50	98.00
V2	passthrough_mode	spi_host_passthrough_mode	7.000s	2.875ms	50	50	100.00
V2	cpol_cpha	spi_host_speed	17.000s	1.524ms	50	50	100.00
V2	full_cycle	spi_host_speed	17.000s	1.524ms	50	50	100.00
V2	duplex	spi_host_smoke	6.333m	13.695ms	50	50	100.00
V2	tx_rx_only	spi_host_smoke	6.333m	13.695ms	50	50	100.00
V2	stress_all	spi_host_stress_all	1.800m	16.170ms	50	50	100.00
V2	spien	spi_host_spien	4.283m	9.175ms	50	50	100.00
V2	stall	spi_host_status_stall	5.033m	10.570ms	47	50	94.00
V2	Idlecsbactive	spi_host_idlecsbactive	33.000s	2.081ms	50	50	100.00
V2	data_fifo_status	spi_host_overflow_underflow	2.000m	15.149ms	50	50	100.00
V2	alert_test	spi_host_alert_test	6.000s	68.456us	50	50	100.00
V2	intr_test	spi_host_intr_test	6.000s	63.199us	50	50	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	7.000s	90.183us	20	20	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	7.000s	90.183us	20	20	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	6.000s	45.188us	5	5	100.00
		spi_host_csr_rw	6.000s	57.630us	20	20	100.00
		spi_host_csr_aliasing	6.000s	18.863us	5	5	100.00
		spi_host_same_csr_outstanding	6.000s	86.122us	20	20	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	6.000s	45.188us	5	5	100.00
		spi_host_csr_rw	6.000s	57.630us	20	20	100.00
		spi_host_csr_aliasing	6.000s	18.863us	5	5	100.00
		spi_host_same_csr_outstanding	6.000s	86.122us	20	20	100.00
V2		TOTAL			686	690	99.42
V2S	tl_intg_err	spi_host_tl_intg_err	10.000s	344.988us	20	20	100.00
		spi_host_sec_cm	8.000s	649.469us	5	5	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	10.000s	344.988us	20	20	100.00
V2S		TOTAL			25	25	100.00
	Unmapped tests	spi_host_upper_range_clkdiv	50.167m	100.001ms	1	10	10.00
		TOTAL			827	840	98.45

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.01	96.83	93.25	98.85	96.28	96.16	100.00	97.40	91.29

Failure Buckets

• UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=2) has 4 failures:

  • Test spi_host_upper_range_clkdiv has 4 failures.

    • 0.spi_host_upper_range_clkdiv.94800058900983094991853456094275544077004176607502451954725006314372200802809
      Line 144, in log /nightly/runs/opentitan/scratch/master/spi_host-sim-xcelium/0.spi_host_upper_range_clkdiv/latest/run.log

        UVM_FATAL @ 100002161695 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x408f1d14, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
        UVM_INFO @ 100002161695 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 3.spi_host_upper_range_clkdiv.101585526826083900770560755281100913503887863052315393576352211033167695952604
      Line 164, in log /nightly/runs/opentitan/scratch/master/spi_host-sim-xcelium/3.spi_host_upper_range_clkdiv/latest/run.log

        UVM_FATAL @ 100004671592 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x1bb4f214, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
        UVM_INFO @ 100004671592 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 2 more failures.

• Job timed out after * minutes has 2 failures:

  • Test spi_host_upper_range_clkdiv has 2 failures.

    • 2.spi_host_upper_range_clkdiv.88480107599190231441955920266960170421980755119113658509913265937763560211419
      Log /nightly/runs/opentitan/scratch/master/spi_host-sim-xcelium/2.spi_host_upper_range_clkdiv/latest/run.log

        Job timed out after 60 minutes
      

    • 5.spi_host_upper_range_clkdiv.27108247990700258762657146710079752808459200967504443085080961751452101490333
      Log /nightly/runs/opentitan/scratch/master/spi_host-sim-xcelium/5.spi_host_upper_range_clkdiv/latest/run.log

        Job timed out after 60 minutes
      

• UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=13) has 2 failures:

  • Test spi_host_upper_range_clkdiv has 2 failures.

    • 7.spi_host_upper_range_clkdiv.54262649591063866438439401492669594309788813263067305092887090534543587778153
      Line 150, in log /nightly/runs/opentitan/scratch/master/spi_host-sim-xcelium/7.spi_host_upper_range_clkdiv/latest/run.log

        UVM_FATAL @ 100006750099 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x1c9576d4, Comparison=CompareOpEq, exp_data=0x0, call_count=13)
        UVM_INFO @ 100006750099 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 9.spi_host_upper_range_clkdiv.69100339188204580761547212399394787043288672084673424808819889230563536024390
      Line 157, in log /nightly/runs/opentitan/scratch/master/spi_host-sim-xcelium/9.spi_host_upper_range_clkdiv/latest/run.log

        UVM_FATAL @ 152568985852 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xda99bb54, Comparison=CompareOpEq, exp_data=0x0, call_count=13)
        UVM_INFO @ 152568985852 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=14) has 1 failures:

  • Test spi_host_sw_reset has 1 failures.

    • 7.spi_host_sw_reset.4958476991061659102592913682299482016230992448665685356933866508968387699140
      Line 172, in log /nightly/runs/opentitan/scratch/master/spi_host-sim-xcelium/7.spi_host_sw_reset/latest/run.log

        UVM_FATAL @ 10003218997 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xe47eeed4, Comparison=CompareOpEq, exp_data=0x0, call_count=14)
        UVM_INFO @ 10003218997 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=10) has 1 failures:

  • Test spi_host_upper_range_clkdiv has 1 failures.

    • 8.spi_host_upper_range_clkdiv.75666358248571801108489906689980004989346247425213633876615771305029082904859
      Line 127, in log /nightly/runs/opentitan/scratch/master/spi_host-sim-xcelium/8.spi_host_upper_range_clkdiv/latest/run.log

        UVM_FATAL @ 100005140304 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x3a6e7854, Comparison=CompareOpEq, exp_data=0x0, call_count=10)
        UVM_INFO @ 100005140304 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=94) has 1 failures:

  • Test spi_host_status_stall has 1 failures.

    • 9.spi_host_status_stall.73251442899420980940275206121228559792070570863784029894230978962957316585126
      Line 777, in log /nightly/runs/opentitan/scratch/master/spi_host-sim-xcelium/9.spi_host_status_stall/latest/run.log

        UVM_FATAL @ 10570215569 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xad81cd94, Comparison=CompareOpEq, exp_data=0x1, call_count=94)
        UVM_INFO @ 10570215569 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=79) has 1 failures:

  • Test spi_host_status_stall has 1 failures.

    • 13.spi_host_status_stall.106005014347704891161411528150903437744407400930929241019811810611531990395540
      Line 698, in log /nightly/runs/opentitan/scratch/master/spi_host-sim-xcelium/13.spi_host_status_stall/latest/run.log

        UVM_FATAL @ 10702135657 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x1fab0714, Comparison=CompareOpEq, exp_data=0x1, call_count=79)
        UVM_INFO @ 10702135657 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=91) has 1 failures:

  • Test spi_host_status_stall has 1 failures.

    • 19.spi_host_status_stall.56677451284284003906509117856977408793899177112747927344620076839733581439558
      Line 767, in log /nightly/runs/opentitan/scratch/master/spi_host-sim-xcelium/19.spi_host_status_stall/latest/run.log

        UVM_FATAL @ 23178695797 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x18979454, Comparison=CompareOpEq, exp_data=0x1, call_count=91)
        UVM_INFO @ 23178695797 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---