UART Simulation Results

Friday January 24 2025 17:10:00 UTC

GitHub Revision: `002bb67a7c`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	22.140s	5.991ms	50	50	100.00
V1	csr_hw_reset	uart_csr_hw_reset	2.170s	1.047ms	5	5	100.00
V1	csr_rw	uart_csr_rw	1.960s	13.877us	20	20	100.00
V1	csr_bit_bash	uart_csr_bit_bash	3.070s	111.928us	5	5	100.00
V1	csr_aliasing	uart_csr_aliasing	2.000s	26.623us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	2.160s	30.377us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	1.960s	13.877us	20	20	100.00
		uart_csr_aliasing	2.000s	26.623us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	base_random_seq	uart_tx_rx	3.049m	142.916ms	50	50	100.00
V2	parity	uart_smoke	22.140s	5.991ms	50	50	100.00
		uart_tx_rx	3.049m	142.916ms	50	50	100.00
V2	parity_error	uart_intr	8.206m	412.514ms	50	50	100.00
		uart_rx_parity_err	4.369m	174.112ms	50	50	100.00
V2	watermark	uart_tx_rx	3.049m	142.916ms	50	50	100.00
		uart_intr	8.206m	412.514ms	50	50	100.00
V2	fifo_full	uart_fifo_full	3.533m	113.072ms	49	50	98.00
V2	fifo_overflow	uart_fifo_overflow	6.973m	85.067ms	50	50	100.00
V2	fifo_reset	uart_fifo_reset	4.800m	124.226ms	300	300	100.00
V2	rx_frame_err	uart_intr	8.206m	412.514ms	50	50	100.00
V2	rx_break_err	uart_intr	8.206m	412.514ms	50	50	100.00
V2	rx_timeout	uart_intr	8.206m	412.514ms	50	50	100.00
V2	perf	uart_perf	14.425m	24.399ms	48	50	96.00
V2	sys_loopback	uart_loopback	19.050s	12.810ms	50	50	100.00
V2	line_loopback	uart_loopback	19.050s	12.810ms	50	50	100.00
V2	rx_noise_filter	uart_noise_filter	2.256m	104.056ms	50	50	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	1.027m	48.327ms	50	50	100.00
V2	tx_overide	uart_tx_ovrd	25.620s	12.842ms	50	50	100.00
V2	rx_oversample	uart_rx_oversample	48.680s	7.211ms	50	50	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	15.197m	134.320ms	50	50	100.00
V2	stress_all	uart_stress_all	13.200m	216.120ms	50	50	100.00
V2	alert_test	uart_alert_test	2.130s	20.628us	50	50	100.00
V2	intr_test	uart_intr_test	2.080s	32.045us	50	50	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	3.250s	443.037us	20	20	100.00
V2	tl_d_illegal_access	uart_tl_errors	3.250s	443.037us	20	20	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	2.170s	1.047ms	5	5	100.00
		uart_csr_rw	1.960s	13.877us	20	20	100.00
		uart_csr_aliasing	2.000s	26.623us	5	5	100.00
		uart_same_csr_outstanding	2.080s	134.778us	20	20	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	2.170s	1.047ms	5	5	100.00
		uart_csr_rw	1.960s	13.877us	20	20	100.00
		uart_csr_aliasing	2.000s	26.623us	5	5	100.00
		uart_same_csr_outstanding	2.080s	134.778us	20	20	100.00
V2		TOTAL			1087	1090	99.72
V2S	tl_intg_err	uart_sec_cm	3.170s	117.039us	5	5	100.00
		uart_tl_intg_err	4.300s	136.833us	20	20	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	4.300s	136.833us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	1.667m	16.598ms	98	100	98.00
V3		TOTAL			98	100	98.00
		TOTAL			1315	1320	99.62

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.76	98.97	97.89	98.02	--	98.14	100.00	99.53

Failure Buckets

UVM_ERROR (uart_scoreboard.sv:447) [scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (* [*] vs * [*]) Interrupt_pin: TxEmpty has 2 failures:

Test uart_perf has 1 failures.

4.uart_perf.53374375557687660267185947497242825465893814720602907614134535826653976746012
Line 69, in log /nightly/runs/opentitan/scratch/master/uart-sim-vcs/4.uart_perf/latest/run.log

  UVM_ERROR @   2659448 ps: (uart_scoreboard.sv:447) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: TxEmpty
  UVM_INFO @ 296129962 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_perf_vseq] finished run 1/9
  UVM_INFO @ 355105608 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_perf_vseq] finished run 2/9
  UVM_INFO @ 1052589824 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_perf_vseq] finished run 3/9
  UVM_INFO @ 1257897778 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_perf_vseq] finished run 4/9

Test uart_stress_all_with_rand_reset has 1 failures.

67.uart_stress_all_with_rand_reset.67003616963811419983525162302378212284711715184978213766243682480795327797226
Line 101, in log /nightly/runs/opentitan/scratch/master/uart-sim-vcs/67.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 156827383 ps: (uart_scoreboard.sv:447) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: TxEmpty
  UVM_ERROR @ 156827383 ps: (uart_scoreboard.sv:447) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: TxWatermark
  UVM_INFO @ 221403076 ps: (cip_base_vseq__tl_errors.svh:290) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 2/818
  UVM_INFO @ 254251528 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 1/5
  UVM_INFO @ 325221154 ps: (cip_base_vseq__tl_errors.svh:290) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 3/818

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test uart_fifo_full has 1 failures.
  - 23.uart_fifo_full.31751583071923317980589370149367483272457276368794113680803146309966038869792
    Line 79, in log /nightly/runs/opentitan/scratch/master/uart-sim-vcs/23.uart_fifo_full/latest/run.log
```
  UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (uart_scoreboard.sv:447) [scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (* [*] vs * [*]) Interrupt_pin: TxWatermark has 1 failures:

Test uart_perf has 1 failures.

38.uart_perf.3963535699039522848453977734884398078999205058601628783315927891314000447430
Line 69, in log /nightly/runs/opentitan/scratch/master/uart-sim-vcs/38.uart_perf/latest/run.log

  UVM_ERROR @   3967727 ps: (uart_scoreboard.sv:447) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: TxWatermark
  UVM_INFO @ 1727902785 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_perf_vseq] finished run 1/9
  UVM_INFO @ 1767940172 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_perf_vseq] finished run 2/9
  UVM_INFO @ 2723364482 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_perf_vseq] finished run 3/9
  UVM_INFO @ 4065958556 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_perf_vseq] finished run 4/9

UVM_ERROR (cip_base_vseq.sv:890) [uart_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

Test uart_stress_all_with_rand_reset has 1 failures.

88.uart_stress_all_with_rand_reset.14578440264462343532131683399402759453743401852408002022369061512373278720403
Line 173, in log /nightly/runs/opentitan/scratch/master/uart-sim-vcs/88.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1793446725 ps: (cip_base_vseq.sv:890) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 1793454759 ps: (cip_base_vseq.sv:794) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 1793454759 ps: (cip_base_vseq.sv:798) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Issuing reset for run 9/10
  UVM_INFO @ 1793456826 ps: (uart_intr_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] finished run 1/1