ADC_CTRL Simulation Results

Saturday February 08 2025 23:09:58 UTC

GitHub Revision: `c12958f63b`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	11.990s	5.971ms	50	50	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	2.850s	940.089us	5	5	100.00
V1	csr_rw	adc_ctrl_csr_rw	2.390s	511.588us	20	20	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	44.950s	40.930ms	5	5	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	3.460s	605.793us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	2.470s	496.732us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	2.390s	511.588us	20	20	100.00
		adc_ctrl_csr_aliasing	3.460s	605.793us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	filters_polled	adc_ctrl_filters_polled	14.044m	483.251ms	50	50	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	14.366m	493.862ms	50	50	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	13.891m	488.297ms	50	50	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	13.926m	491.094ms	50	50	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	17.104m	665.284ms	50	50	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	16.176m	591.498ms	50	50	100.00
V2	filters_both	adc_ctrl_filters_both	14.071m	508.951ms	45	50	90.00
V2	clock_gating	adc_ctrl_clock_gating	14.560m	552.831ms	32	50	64.00
V2	poweron_counter	adc_ctrl_poweron_counter	10.460s	5.390ms	50	50	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	1.257m	45.766ms	50	50	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	3.422m	124.910ms	50	50	100.00
V2	stress_all	adc_ctrl_stress_all	32.372m	10.000s	45	50	90.00
V2	alert_test	adc_ctrl_alert_test	2.810s	518.685us	50	50	100.00
V2	intr_test	adc_ctrl_intr_test	2.390s	517.343us	50	50	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	3.250s	485.664us	20	20	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	3.250s	485.664us	20	20	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	2.850s	940.089us	5	5	100.00
		adc_ctrl_csr_rw	2.390s	511.588us	20	20	100.00
		adc_ctrl_csr_aliasing	3.460s	605.793us	5	5	100.00
		adc_ctrl_same_csr_outstanding	14.840s	4.527ms	20	20	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	2.850s	940.089us	5	5	100.00
		adc_ctrl_csr_rw	2.390s	511.588us	20	20	100.00
		adc_ctrl_csr_aliasing	3.460s	605.793us	5	5	100.00
		adc_ctrl_same_csr_outstanding	14.840s	4.527ms	20	20	100.00
V2		TOTAL			712	740	96.22
V2S	tl_intg_err	adc_ctrl_sec_cm	55.734m	12.686ms	3	5	60.00
		adc_ctrl_tl_intg_err	22.180s	8.666ms	20	20	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	22.180s	8.666ms	20	20	100.00
V2S		TOTAL			23	25	92.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	12.100s	85.001ms	46	50	92.00
V3		TOTAL			46	50	92.00
		TOTAL			886	920	96.30

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.55	99.06	96.45	100.00	100.00	98.77	98.04	90.52

Failure Buckets

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 15 failures:

Test adc_ctrl_filters_both has 2 failures.

0.adc_ctrl_filters_both.68874447915005160221929268535457114230940558650608936555826696368248891984637
Line 178, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/0.adc_ctrl_filters_both/latest/run.log

  UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

29.adc_ctrl_filters_both.70288009039810372758115969821578598557821154785058405082989166045359245473941
Line 178, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/29.adc_ctrl_filters_both/latest/run.log

  UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test adc_ctrl_clock_gating has 9 failures.

1.adc_ctrl_clock_gating.50789580680810328369598677650662258246757597740203280766162048644338166198932
Line 163, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/1.adc_ctrl_clock_gating/latest/run.log

  UVM_FATAL @ 2000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 2000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 2000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

13.adc_ctrl_clock_gating.54977823722168837950555574378740242847374963118856031184368448789005365178079
Line 180, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/13.adc_ctrl_clock_gating/latest/run.log

  UVM_FATAL @ 2000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 2000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 2000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 7 more failures.

Test adc_ctrl_stress_all has 4 failures.

14.adc_ctrl_stress_all.104269136912006873174065633465038925537441318548994166962558110706268470743483
Line 174, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/14.adc_ctrl_stress_all/latest/run.log

  UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

18.adc_ctrl_stress_all.41554842257329373941734685598611612399409933730658237634308127180425645765968
Line 199, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/18.adc_ctrl_stress_all/latest/run.log

  UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

UVM_ERROR (cip_base_scoreboard.sv:249) scoreboard [scoreboard] alert fatal_fault has unexpected timeout error has 12 failures:

Test adc_ctrl_stress_all_with_rand_reset has 3 failures.

9.adc_ctrl_stress_all_with_rand_reset.96957542989329597816595987622194820766283214670321360292673793310775968544012
Line 152, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/9.adc_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 5842923504 ps: (cip_base_scoreboard.sv:249) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
  UVM_INFO @ 5842923504 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

39.adc_ctrl_stress_all_with_rand_reset.87386301103293592643444923875296811932208129832401738446992115668951265846772
Line 188, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/39.adc_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 11590423170 ps: (cip_base_scoreboard.sv:249) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
  UVM_INFO @ 11590423170 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test adc_ctrl_stress_all has 1 failures.

10.adc_ctrl_stress_all.97439198615615612947241926964901719222216820144802722264014587211736085174989
Line 165, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/10.adc_ctrl_stress_all/latest/run.log

  UVM_ERROR @ 204453093267 ps: (cip_base_scoreboard.sv:249) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
  UVM_INFO @ 204453093267 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test adc_ctrl_clock_gating has 8 failures.

11.adc_ctrl_clock_gating.61428982494206565474498626337360798151948390382507060533857515497368100863820
Line 146, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/11.adc_ctrl_clock_gating/latest/run.log

  UVM_ERROR @ 7255738735 ps: (cip_base_scoreboard.sv:249) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
  UVM_INFO @ 7255738735 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

12.adc_ctrl_clock_gating.11226803630461162790448598581972634275193077327216468800052313948038278702735
Line 180, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/12.adc_ctrl_clock_gating/latest/run.log

  UVM_ERROR @ 336717910044 ps: (cip_base_scoreboard.sv:249) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
  UVM_INFO @ 336717910044 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 6 more failures.

UVM_ERROR (adc_ctrl_scoreboard.sv:405) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: adc_ctrl_reg_block.intr_state has 4 failures:

Test adc_ctrl_filters_both has 3 failures.

15.adc_ctrl_filters_both.52869682447763549096116200292636147298491126272839252410768381213767281572635
Line 178, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/15.adc_ctrl_filters_both/latest/run.log

  UVM_ERROR @ 413156898946 ps: (adc_ctrl_scoreboard.sv:405) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
  UVM_INFO @ 413156898946 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

20.adc_ctrl_filters_both.72203625072165591171149834134798484122986359819149840267016311422465189378642
Line 146, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/20.adc_ctrl_filters_both/latest/run.log

  UVM_ERROR @ 180244539199 ps: (adc_ctrl_scoreboard.sv:405) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
  UVM_INFO @ 180244539199 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test adc_ctrl_clock_gating has 1 failures.

48.adc_ctrl_clock_gating.102989267329077869600204836377057016063780512414655206912365941115794310724010
Line 163, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/48.adc_ctrl_clock_gating/latest/run.log

  UVM_ERROR @ 325888896558 ps: (adc_ctrl_scoreboard.sv:405) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
  UVM_INFO @ 325888896558 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (cip_base_vseq.sv:665) [adc_ctrl_common_vseq] timeout wait for alert handshake:fatal_fault has 2 failures:

Test adc_ctrl_sec_cm has 2 failures.

0.adc_ctrl_sec_cm.63553900657558004130548498922281932894195592788367868422661796290987260377567
Line 185, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/0.adc_ctrl_sec_cm/latest/run.log

  UVM_FATAL @ 12399268400 ps: (cip_base_vseq.sv:665) [uvm_test_top.env.virtual_sequencer.adc_ctrl_common_vseq] timeout wait for alert handshake:fatal_fault
  UVM_INFO @ 12399268400 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.adc_ctrl_sec_cm.80396604391431176270703266826555556021371664165364118800187190256049036304683
Line 201, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/1.adc_ctrl_sec_cm/latest/run.log

  UVM_FATAL @ 12686216017 ps: (cip_base_vseq.sv:665) [uvm_test_top.env.virtual_sequencer.adc_ctrl_common_vseq] timeout wait for alert handshake:fatal_fault
  UVM_INFO @ 12686216017 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (adc_ctrl_scoreboard.sv:137) [scoreboard] Check failed m_wakeup == m_expected_wakeup (* [*] vs * [*]) has 1 failures:
- Test adc_ctrl_stress_all_with_rand_reset has 1 failures.
  - 1.adc_ctrl_stress_all_with_rand_reset.52747423248917532014314799305360983911677215246125782744547277091241485974999
    Line 216, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/1.adc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 5527262109 ps: (adc_ctrl_scoreboard.sv:137) [uvm_test_top.env.scoreboard] Check failed m_wakeup == m_expected_wakeup (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 5527262109 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```