AES/MASKED Simulation Results

Saturday February 08 2025 23:09:58 UTC

GitHub Revision: `c12958f63b`

Branch: master

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	24.000s	79.555us	1	1	100.00
V1	smoke	aes_smoke	24.000s	118.860us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	6.000s	84.396us	5	5	100.00
V1	csr_rw	aes_csr_rw	7.000s	98.576us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	10.000s	1.027ms	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	7.000s	166.611us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	7.000s	153.407us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	7.000s	98.576us	20	20	100.00
		aes_csr_aliasing	7.000s	166.611us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	24.000s	118.860us	50	50	100.00
		aes_config_error	34.000s	1.658ms	50	50	100.00
		aes_stress	26.000s	871.722us	50	50	100.00
V2	key_length	aes_smoke	24.000s	118.860us	50	50	100.00
		aes_config_error	34.000s	1.658ms	50	50	100.00
		aes_stress	26.000s	871.722us	50	50	100.00
V2	back2back	aes_stress	26.000s	871.722us	50	50	100.00
		aes_b2b	42.000s	852.133us	50	50	100.00
V2	backpressure	aes_stress	26.000s	871.722us	50	50	100.00
V2	multi_message	aes_smoke	24.000s	118.860us	50	50	100.00
		aes_config_error	34.000s	1.658ms	50	50	100.00
		aes_stress	26.000s	871.722us	50	50	100.00
		aes_alert_reset	42.000s	1.685ms	49	50	98.00
V2	failure_test	aes_man_cfg_err	24.000s	97.532us	50	50	100.00
		aes_config_error	34.000s	1.658ms	50	50	100.00
		aes_alert_reset	42.000s	1.685ms	49	50	98.00
V2	trigger_clear_test	aes_clear	30.000s	1.671ms	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	27.000s	285.932us	1	1	100.00
V2	reset_recovery	aes_alert_reset	42.000s	1.685ms	49	50	98.00
V2	stress	aes_stress	26.000s	871.722us	50	50	100.00
V2	sideload	aes_stress	26.000s	871.722us	50	50	100.00
		aes_sideload	25.000s	83.940us	50	50	100.00
V2	deinitialization	aes_deinit	24.000s	61.699us	50	50	100.00
V2	stress_all	aes_stress_all	1.317m	26.593ms	8	10	80.00
V2	alert_test	aes_alert_test	24.000s	50.704us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	7.000s	294.881us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	7.000s	294.881us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	6.000s	84.396us	5	5	100.00
		aes_csr_rw	7.000s	98.576us	20	20	100.00
		aes_csr_aliasing	7.000s	166.611us	5	5	100.00
		aes_same_csr_outstanding	8.000s	69.254us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	6.000s	84.396us	5	5	100.00
		aes_csr_rw	7.000s	98.576us	20	20	100.00
		aes_csr_aliasing	7.000s	166.611us	5	5	100.00
		aes_same_csr_outstanding	8.000s	69.254us	20	20	100.00
V2		TOTAL			498	501	99.40
V2S	reseeding	aes_reseed	46.000s	2.229ms	50	50	100.00
V2S	fault_inject	aes_fi	38.000s	2.555ms	45	50	90.00
		aes_control_fi	57.000s	10.008ms	276	300	92.00
		aes_cipher_fi	51.000s	10.033ms	343	350	98.00
V2S	shadow_reg_update_error	aes_shadow_reg_errors	9.000s	194.293us	6	20	30.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	9.000s	194.293us	6	20	30.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	9.000s	194.293us	6	20	30.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	9.000s	194.293us	6	20	30.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	12.000s	873.491us	15	20	75.00
V2S	tl_intg_err	aes_sec_cm	44.000s	997.919us	5	5	100.00
		aes_tl_intg_err	38.000s	787.996us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	38.000s	787.996us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	42.000s	1.685ms	49	50	98.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	9.000s	194.293us	6	20	30.00
V2S	sec_cm_main_config_sparse	aes_smoke	24.000s	118.860us	50	50	100.00
		aes_stress	26.000s	871.722us	50	50	100.00
		aes_alert_reset	42.000s	1.685ms	49	50	98.00
		aes_core_fi	52.000s	10.003ms	65	70	92.86
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	9.000s	194.293us	6	20	30.00
V2S	sec_cm_aux_config_regwen	aes_readability	24.000s	62.937us	50	50	100.00
		aes_stress	26.000s	871.722us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	26.000s	871.722us	50	50	100.00
		aes_sideload	25.000s	83.940us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	24.000s	62.937us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	24.000s	62.937us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	24.000s	62.937us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	24.000s	62.937us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	24.000s	62.937us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	26.000s	871.722us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	26.000s	871.722us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	38.000s	2.555ms	45	50	90.00
V2S	sec_cm_main_fsm_redun	aes_fi	38.000s	2.555ms	45	50	90.00
		aes_control_fi	57.000s	10.008ms	276	300	92.00
		aes_cipher_fi	51.000s	10.033ms	343	350	98.00
		aes_ctr_fi	24.000s	93.477us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	38.000s	2.555ms	45	50	90.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	38.000s	2.555ms	45	50	90.00
		aes_control_fi	57.000s	10.008ms	276	300	92.00
		aes_cipher_fi	51.000s	10.033ms	343	350	98.00
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	51.000s	10.033ms	343	350	98.00
V2S	sec_cm_ctr_fsm_sparse	aes_fi	38.000s	2.555ms	45	50	90.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	38.000s	2.555ms	45	50	90.00
		aes_control_fi	57.000s	10.008ms	276	300	92.00
		aes_ctr_fi	24.000s	93.477us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	38.000s	2.555ms	45	50	90.00
		aes_control_fi	57.000s	10.008ms	276	300	92.00
		aes_cipher_fi	51.000s	10.033ms	343	350	98.00
		aes_ctr_fi	24.000s	93.477us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	42.000s	1.685ms	49	50	98.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	38.000s	2.555ms	45	50	90.00
		aes_control_fi	57.000s	10.008ms	276	300	92.00
		aes_cipher_fi	51.000s	10.033ms	343	350	98.00
		aes_ctr_fi	24.000s	93.477us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	38.000s	2.555ms	45	50	90.00
		aes_control_fi	57.000s	10.008ms	276	300	92.00
		aes_cipher_fi	51.000s	10.033ms	343	350	98.00
		aes_ctr_fi	24.000s	93.477us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	38.000s	2.555ms	45	50	90.00
		aes_control_fi	57.000s	10.008ms	276	300	92.00
		aes_ctr_fi	24.000s	93.477us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	38.000s	2.555ms	45	50	90.00
		aes_control_fi	57.000s	10.008ms	276	300	92.00
		aes_cipher_fi	51.000s	10.033ms	343	350	98.00
V2S		TOTAL			925	985	93.91
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	25.000s	500.161us	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1529	1602	95.44

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.39	98.61	96.47	99.42	95.71	98.07	97.04	98.95	98.20

Failure Buckets

UVM_FATAL (alert_receiver_driver.sv:146) [driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q has 26 failures:

Test aes_stress_all has 2 failures.

1.aes_stress_all.99064513545333521064356744452186386697235926568791072164526331498985912152067
Line 939, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/1.aes_stress_all/latest/run.log

  UVM_FATAL @  31027859 ps: (alert_receiver_driver.sv:146) [uvm_test_top.env.m_alert_agent_fatal_fault.driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q
  UVM_INFO @  31027859 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.aes_stress_all.35099846581489100590231704855133893128876988449013401160764918610718894805707
Line 368181, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/2.aes_stress_all/latest/run.log

  UVM_FATAL @ 921254679 ps: (alert_receiver_driver.sv:146) [uvm_test_top.env.m_alert_agent_fatal_fault.driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q
  UVM_INFO @ 921254679 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test aes_stress_all_with_rand_reset has 1 failures.

1.aes_stress_all_with_rand_reset.94142202026311230017484609562079757526770385295720296291446790464759969497366
Line 440, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @ 658900022 ps: (alert_receiver_driver.sv:146) [uvm_test_top.env.m_alert_agent_fatal_fault.driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q
  UVM_INFO @ 658900022 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test aes_shadow_reg_errors has 14 failures.

1.aes_shadow_reg_errors.68678692235749678843514487632332342541815177785426736031439565646489860221711
Line 104, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/1.aes_shadow_reg_errors/latest/run.log

  UVM_FATAL @   7985826 ps: (alert_receiver_driver.sv:146) [uvm_test_top.env.m_alert_agent_fatal_fault.driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q
  UVM_INFO @   7985826 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.aes_shadow_reg_errors.45535492315863663760281016900409545465422494334634090030037108293833165524899
Line 103, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/4.aes_shadow_reg_errors/latest/run.log

  UVM_FATAL @  14662926 ps: (alert_receiver_driver.sv:146) [uvm_test_top.env.m_alert_agent_fatal_fault.driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q
  UVM_INFO @  14662926 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 12 more failures.

Test aes_shadow_reg_errors_with_csr_rw has 5 failures.

1.aes_shadow_reg_errors_with_csr_rw.32303044637706197988530229631889927725986063174676205176299741125230284202223
Line 104, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/1.aes_shadow_reg_errors_with_csr_rw/latest/run.log

  UVM_FATAL @ 177148513 ps: (alert_receiver_driver.sv:146) [uvm_test_top.env.m_alert_agent_fatal_fault.driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q
  UVM_INFO @ 177148513 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.aes_shadow_reg_errors_with_csr_rw.10663864691435133283644321631776656420218410821959283937675879338281383938078
Line 103, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/3.aes_shadow_reg_errors_with_csr_rw/latest/run.log

  UVM_FATAL @  13796240 ps: (alert_receiver_driver.sv:146) [uvm_test_top.env.m_alert_agent_fatal_fault.driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q
  UVM_INFO @  13796240 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

Test aes_fi has 3 failures.

10.aes_fi.41104631715758721569443550235563996212188939534865389451586938453080706724974
Line 1194, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/10.aes_fi/latest/run.log

  UVM_FATAL @ 111893122 ps: (alert_receiver_driver.sv:146) [uvm_test_top.env.m_alert_agent_fatal_fault.driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q
  UVM_INFO @ 111893122 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

18.aes_fi.78099344752362784151887731468150952977551077134660792007048204068819270562028
Line 5282, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/18.aes_fi/latest/run.log

  UVM_FATAL @  17883936 ps: (alert_receiver_driver.sv:146) [uvm_test_top.env.m_alert_agent_fatal_fault.driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q
  UVM_INFO @  17883936 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

... and 1 more tests.

Job timed out after * minutes has 14 failures:
- Test aes_control_fi has 14 failures.
  - 16.aes_control_fi.110954361431988254090990910311172706171634010652267061742185738544699329095656
    Log /nightly/runs/scratch/master/aes_masked-sim-xcelium/16.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 88.aes_control_fi.91428731843736615126302013013609599583286789191035579438359423582754959239449
    Log /nightly/runs/scratch/master/aes_masked-sim-xcelium/88.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 12 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 10 failures:
- Test aes_control_fi has 10 failures.
  - 7.aes_control_fi.94891781915317472283017390024740730082317336872748405020614162977377495785347
    Line 136, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/7.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10013489220 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10013489220 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 80.aes_control_fi.91867318216018291353998028202845257656574960099846892964965974874333133968383
    Line 140, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/80.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10028341485 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10028341485 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 8 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 7 failures:
- Test aes_cipher_fi has 7 failures.
  - 22.aes_cipher_fi.12672892948102341703572530158652662385805172315079262043365789927014527823400
    Line 138, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/22.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10008826014 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10008826014 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 57.aes_cipher_fi.81544496023434672223556383727987270867489486072029290218600678748638780114507
    Line 143, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/57.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10030389877 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10030389877 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 5 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 6 failures:

Test aes_stress_all_with_rand_reset has 6 failures.

3.aes_stress_all_with_rand_reset.45172322465373364724270828404782427559992981302772627383873904936726635304367
Line 226, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/3.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 939851167 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 939851167 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.aes_stress_all_with_rand_reset.92366323022222908011695993997564755059301204974749819016520083073624795331282
Line 659, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/4.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 675277665 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 675277665 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 5 failures:
- Test aes_core_fi has 5 failures.
  - 11.aes_core_fi.78410194995988318598083296770099845174390934895214999841304807111665425128489
    Line 138, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/11.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10028517879 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10028517879 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 12.aes_core_fi.93187723182644363382346521847552185711083074025899612068591646466548877660064
    Line 142, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/12.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10014795167 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10014795167 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.
UVM_FATAL (aes_base_vseq.sv:74) [aes_reseed_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 0.aes_stress_all_with_rand_reset.64890944205093228011491193571185377090556224921286337210749480825859323468785
    Line 146, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 100550734 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 100550734 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_base_vseq.sv:74) [aes_stress_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 2.aes_stress_all_with_rand_reset.22308966750234995252098015461636808476190621538125257044755281422315102535564
    Line 524, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 2065906179 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_stress_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 2065906179 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_base_vseq.sv:74) [aes_alert_reset_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 8.aes_stress_all_with_rand_reset.19795920622184042154824932580887683916161835316478155395270253976810221865429
    Line 389, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/8.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 1009277663 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 1009277663 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_fi_vseq.sv:69) virtual_sequencer [aes_fi_vseq] Was Able to finish without clearing reset has 1 failures:
- Test aes_fi has 1 failures.
  - 24.aes_fi.98190199601782578888239299560281382382929666786052974801612711921395195441156
    Line 56973, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/24.aes_fi/latest/run.log
```
  UVM_FATAL @ 487665439 ps: (aes_fi_vseq.sv:69) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.aes_fi_vseq] Was Able to finish without clearing reset
  UVM_INFO @ 487665439 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

xmsim: *E,ASRTST (/nightly/runs/scratch/master/aes_masked-sim-xcelium/default/src/lowrisc_ip_aes_*/rtl/aes_core.sv,987): Assertion AesSecCmDataRegLocalEscDataOut has failed (* cycles, starting * PS) has 1 failures:

Test aes_fi has 1 failures.

47.aes_fi.58297701892811704930346026711940838013766672391782610331603762798781008608130
Line 885, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/47.aes_fi/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/aes_masked-sim-xcelium/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,987): (time 48134208 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscDataOut has failed (2 cycles, starting 48092541 PS)
        ($past(iv_q) != $past(state_done_transposed, 2) ^ $past(data_in_prev_q, 2)))
                                                                                   |
  xmsim: *E,ASRTST (/nightly/runs/scratch/master/aes_masked-sim-xcelium/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,993): (time 48134208 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscIv has failed (2 cycles, starting 48092541 PS)
  UVM_ERROR @  48134208 ps: (aes_core.sv:987) [ASSERT FAILED] AesSecCmDataRegLocalEscDataOut