AES/UNMASKED Simulation Results

Saturday February 08 2025 23:09:58 UTC

GitHub Revision: `c12958f63b`

Branch: master

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	6.000s	88.972us	1	1	100.00
V1	smoke	aes_smoke	8.000s	204.849us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	5.000s	53.253us	5	5	100.00
V1	csr_rw	aes_csr_rw	6.000s	149.379us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	10.000s	857.410us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	6.000s	89.341us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	6.000s	105.355us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	6.000s	149.379us	20	20	100.00
		aes_csr_aliasing	6.000s	89.341us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	8.000s	204.849us	50	50	100.00
		aes_config_error	7.000s	180.714us	50	50	100.00
		aes_stress	7.000s	120.749us	50	50	100.00
V2	key_length	aes_smoke	8.000s	204.849us	50	50	100.00
		aes_config_error	7.000s	180.714us	50	50	100.00
		aes_stress	7.000s	120.749us	50	50	100.00
V2	back2back	aes_stress	7.000s	120.749us	50	50	100.00
		aes_b2b	9.000s	231.081us	50	50	100.00
V2	backpressure	aes_stress	7.000s	120.749us	50	50	100.00
V2	multi_message	aes_smoke	8.000s	204.849us	50	50	100.00
		aes_config_error	7.000s	180.714us	50	50	100.00
		aes_stress	7.000s	120.749us	50	50	100.00
		aes_alert_reset	7.000s	87.038us	48	50	96.00
V2	failure_test	aes_man_cfg_err	7.000s	97.607us	50	50	100.00
		aes_config_error	7.000s	180.714us	50	50	100.00
		aes_alert_reset	7.000s	87.038us	48	50	96.00
V2	trigger_clear_test	aes_clear	8.000s	168.383us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	8.000s	972.440us	1	1	100.00
V2	reset_recovery	aes_alert_reset	7.000s	87.038us	48	50	96.00
V2	stress	aes_stress	7.000s	120.749us	50	50	100.00
V2	sideload	aes_stress	7.000s	120.749us	50	50	100.00
		aes_sideload	7.000s	105.802us	50	50	100.00
V2	deinitialization	aes_deinit	7.000s	94.989us	50	50	100.00
V2	stress_all	aes_stress_all	26.000s	4.492ms	10	10	100.00
V2	alert_test	aes_alert_test	6.000s	94.615us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	7.000s	98.087us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	7.000s	98.087us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	5.000s	53.253us	5	5	100.00
		aes_csr_rw	6.000s	149.379us	20	20	100.00
		aes_csr_aliasing	6.000s	89.341us	5	5	100.00
		aes_same_csr_outstanding	6.000s	142.885us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	5.000s	53.253us	5	5	100.00
		aes_csr_rw	6.000s	149.379us	20	20	100.00
		aes_csr_aliasing	6.000s	89.341us	5	5	100.00
		aes_same_csr_outstanding	6.000s	142.885us	20	20	100.00
V2		TOTAL			499	501	99.60
V2S	reseeding	aes_reseed	8.000s	268.467us	50	50	100.00
V2S	fault_inject	aes_fi	8.000s	407.729us	45	50	90.00
		aes_control_fi	42.000s	200.000ms	283	300	94.33
		aes_cipher_fi	35.000s	10.006ms	320	350	91.43
V2S	shadow_reg_update_error	aes_shadow_reg_errors	10.000s	259.031us	10	20	50.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	10.000s	259.031us	10	20	50.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	10.000s	259.031us	10	20	50.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	10.000s	259.031us	10	20	50.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	41.000s	1.310ms	12	20	60.00
V2S	tl_intg_err	aes_sec_cm	41.000s	1.291ms	5	5	100.00
		aes_tl_intg_err	25.000s	513.515us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	25.000s	513.515us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	7.000s	87.038us	48	50	96.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	10.000s	259.031us	10	20	50.00
V2S	sec_cm_main_config_sparse	aes_smoke	8.000s	204.849us	50	50	100.00
		aes_stress	7.000s	120.749us	50	50	100.00
		aes_alert_reset	7.000s	87.038us	48	50	96.00
		aes_core_fi	5.950m	10.030ms	61	70	87.14
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	10.000s	259.031us	10	20	50.00
V2S	sec_cm_aux_config_regwen	aes_readability	6.000s	63.493us	50	50	100.00
		aes_stress	7.000s	120.749us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	7.000s	120.749us	50	50	100.00
		aes_sideload	7.000s	105.802us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	6.000s	63.493us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	6.000s	63.493us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	6.000s	63.493us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	6.000s	63.493us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	6.000s	63.493us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	7.000s	120.749us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	7.000s	120.749us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	8.000s	407.729us	45	50	90.00
V2S	sec_cm_main_fsm_redun	aes_fi	8.000s	407.729us	45	50	90.00
		aes_control_fi	42.000s	200.000ms	283	300	94.33
		aes_cipher_fi	35.000s	10.006ms	320	350	91.43
		aes_ctr_fi	10.000s	253.406us	49	50	98.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	8.000s	407.729us	45	50	90.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	8.000s	407.729us	45	50	90.00
		aes_control_fi	42.000s	200.000ms	283	300	94.33
		aes_cipher_fi	35.000s	10.006ms	320	350	91.43
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	35.000s	10.006ms	320	350	91.43
V2S	sec_cm_ctr_fsm_sparse	aes_fi	8.000s	407.729us	45	50	90.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	8.000s	407.729us	45	50	90.00
		aes_control_fi	42.000s	200.000ms	283	300	94.33
		aes_ctr_fi	10.000s	253.406us	49	50	98.00
V2S	sec_cm_ctrl_sparse	aes_fi	8.000s	407.729us	45	50	90.00
		aes_control_fi	42.000s	200.000ms	283	300	94.33
		aes_cipher_fi	35.000s	10.006ms	320	350	91.43
		aes_ctr_fi	10.000s	253.406us	49	50	98.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	7.000s	87.038us	48	50	96.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	8.000s	407.729us	45	50	90.00
		aes_control_fi	42.000s	200.000ms	283	300	94.33
		aes_cipher_fi	35.000s	10.006ms	320	350	91.43
		aes_ctr_fi	10.000s	253.406us	49	50	98.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	8.000s	407.729us	45	50	90.00
		aes_control_fi	42.000s	200.000ms	283	300	94.33
		aes_cipher_fi	35.000s	10.006ms	320	350	91.43
		aes_ctr_fi	10.000s	253.406us	49	50	98.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	8.000s	407.729us	45	50	90.00
		aes_control_fi	42.000s	200.000ms	283	300	94.33
		aes_ctr_fi	10.000s	253.406us	49	50	98.00
V2S	sec_cm_data_reg_local_esc	aes_fi	8.000s	407.729us	45	50	90.00
		aes_control_fi	42.000s	200.000ms	283	300	94.33
		aes_cipher_fi	35.000s	10.006ms	320	350	91.43
V2S		TOTAL			905	985	91.88
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	14.000s	1.172ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1510	1602	94.26

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.23	97.58	94.54	98.71	93.48	98.07	91.11	98.84	98.40

Failure Buckets

Job timed out after * minutes has 31 failures:
- Test aes_cipher_fi has 20 failures.
  - 0.aes_cipher_fi.3727342814472355270260495779737769813018036428121574041151843487131759600068
    Log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/0.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 9.aes_cipher_fi.98035331393176566673857733291190090563712973939690978107103491056169069285212
    Log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/9.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 18 more failures.
- Test aes_control_fi has 10 failures.
  - 7.aes_control_fi.48703265770485841753317262647530391753567906703025893373904504353877519173949
    Log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/7.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 27.aes_control_fi.104413116361001917048378915503359429097588366560339875133390519097982457655575
    Log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/27.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 8 more failures.
- Test aes_ctr_fi has 1 failures.
  - 40.aes_ctr_fi.111926357162969678446614621393642728387377619210007775928953180828480361679676
    Log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/40.aes_ctr_fi/latest/run.log
```
  Job timed out after 1 minutes
```

UVM_FATAL (alert_receiver_driver.sv:146) [driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q has 26 failures:

Test aes_shadow_reg_errors has 10 failures.

0.aes_shadow_reg_errors.70997272745703364539130482311144842255764575522452374560315642858727516874626
Line 103, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/0.aes_shadow_reg_errors/latest/run.log

  UVM_FATAL @  21881493 ps: (alert_receiver_driver.sv:146) [uvm_test_top.env.m_alert_agent_fatal_fault.driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q
  UVM_INFO @  21881493 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

5.aes_shadow_reg_errors.26277704241287882085918750018317478302336865363637782006332161948350270444950
Line 103, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/5.aes_shadow_reg_errors/latest/run.log

  UVM_FATAL @  52646924 ps: (alert_receiver_driver.sv:146) [uvm_test_top.env.m_alert_agent_fatal_fault.driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q
  UVM_INFO @  52646924 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 8 more failures.

Test aes_stress_all_with_rand_reset has 2 failures.

1.aes_stress_all_with_rand_reset.27828818195227024551188934434190754442910085852794470276271398599569461792532
Line 926, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @ 1172403124 ps: (alert_receiver_driver.sv:146) [uvm_test_top.env.m_alert_agent_fatal_fault.driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q
  UVM_INFO @ 1172403124 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.aes_stress_all_with_rand_reset.11784716655032176882237671195850487803944741109968657503239291780147314664674
Line 795, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @ 221982661 ps: (alert_receiver_driver.sv:146) [uvm_test_top.env.m_alert_agent_fatal_fault.driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q
  UVM_INFO @ 221982661 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test aes_shadow_reg_errors_with_csr_rw has 8 failures.

1.aes_shadow_reg_errors_with_csr_rw.19440494348743109213460359445896031333888101590055200980752936440792393589804
Line 103, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/1.aes_shadow_reg_errors_with_csr_rw/latest/run.log

  UVM_FATAL @  66096562 ps: (alert_receiver_driver.sv:146) [uvm_test_top.env.m_alert_agent_fatal_fault.driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q
  UVM_INFO @  66096562 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.aes_shadow_reg_errors_with_csr_rw.78531384495453983285471960330802125535442394373626648144911704723073323224498
Line 103, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/3.aes_shadow_reg_errors_with_csr_rw/latest/run.log

  UVM_FATAL @ 165915636 ps: (alert_receiver_driver.sv:146) [uvm_test_top.env.m_alert_agent_fatal_fault.driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q
  UVM_INFO @ 165915636 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 6 more failures.

Test aes_alert_reset has 2 failures.

3.aes_alert_reset.84441263738039260049408280435216015043529315411129150975128866291289394815760
Line 2554, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/3.aes_alert_reset/latest/run.log

  UVM_FATAL @   9703605 ps: (alert_receiver_driver.sv:146) [uvm_test_top.env.m_alert_agent_fatal_fault.driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q
  UVM_INFO @   9703605 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

13.aes_alert_reset.108827985965633844509243431664290011051768000870757252941739989723678685740917
Line 1454, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/13.aes_alert_reset/latest/run.log

  UVM_FATAL @  14932659 ps: (alert_receiver_driver.sv:146) [uvm_test_top.env.m_alert_agent_fatal_fault.driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q
  UVM_INFO @  14932659 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test aes_fi has 2 failures.

7.aes_fi.101178628864995856956769641121463736893985951840453711354309322184248477631786
Line 1420, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/7.aes_fi/latest/run.log

  UVM_FATAL @  43311003 ps: (alert_receiver_driver.sv:146) [uvm_test_top.env.m_alert_agent_fatal_fault.driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q
  UVM_INFO @  43311003 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

44.aes_fi.63551087938814391312070612868876252513397250861945376657238213304015021419593
Line 1254, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/44.aes_fi/latest/run.log

  UVM_FATAL @  10020013 ps: (alert_receiver_driver.sv:146) [uvm_test_top.env.m_alert_agent_fatal_fault.driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q
  UVM_INFO @  10020013 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more tests.

UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 10 failures:
- Test aes_cipher_fi has 10 failures.
  - 98.aes_cipher_fi.43165100730449490204842864292244430805285445988731940963389584623043197399353
    Line 143, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/98.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10005063382 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10005063382 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 102.aes_cipher_fi.86301153319241696924298210246469972824585945183979665061069743088453527973198
    Line 132, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/102.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10014302644 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10014302644 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 8 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 6 failures:

Test aes_stress_all_with_rand_reset has 6 failures.

0.aes_stress_all_with_rand_reset.76888522408954437123089623811118330836549758961557845813391583848108087868803
Line 526, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1533706928 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1533706928 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.aes_stress_all_with_rand_reset.21358131752020441380661765030078843023188038743929482794468104296450856789903
Line 1196, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/3.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 3080703974 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 3080703974 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 6 failures:
- Test aes_control_fi has 6 failures.
  - 11.aes_control_fi.104860536154187727850892750494138256060569413976822891345593802368196232538949
    Line 141, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/11.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10003250289 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10003250289 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 53.aes_control_fi.19388047535697358817755263575440956767765207805530346796061053349704724893720
    Line 137, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/53.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10004600775 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10004600775 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 4 more failures.
UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 4 failures:
- Test aes_core_fi has 4 failures.
  - 26.aes_core_fi.1403106444722654425092995948644842281636666355319206597619684512521001460509
    Line 138, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/26.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10002626029 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10002626029 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 29.aes_core_fi.15623409628349096549174161880702131214578623895554928355081361338172080511065
    Line 138, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/29.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10010055417 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10010055417 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.
UVM_FATAL (aes_core_fi_vseq.sv:89) [aes_core_fi_vseq] wait timeout occurred! has 3 failures:
- Test aes_core_fi has 3 failures.
  - 8.aes_core_fi.90066324608425492831573819765188661618874522572328008778905788660851740386163
    Line 134, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/8.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10032976934 ps: (aes_core_fi_vseq.sv:89) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10032976934 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 23.aes_core_fi.36513756316725313374623275638715944669858100194960103858019950380694346821397
    Line 138, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/23.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10030230387 ps: (aes_core_fi_vseq.sv:89) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10030230387 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.

xmsim: *E,ASRTST (/nightly/runs/scratch/master/aes_unmasked-sim-xcelium/default/src/lowrisc_ip_aes_*/rtl/aes_core.sv,993): Assertion AesSecCmDataRegLocalEscIv has failed (* cycles, starting * PS) has 2 failures:

Test aes_fi has 2 failures.

10.aes_fi.66892431536541918439868758630878615223292580148835168226621410339761112585867
Line 503, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/10.aes_fi/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/aes_unmasked-sim-xcelium/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,993): (time 30700280 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscIv has failed (2 cycles, starting 30660280 PS)
  UVM_ERROR @  30700280 ps: (aes_core.sv:993) [ASSERT FAILED] AesSecCmDataRegLocalEscIv
  UVM_INFO @  30700280 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

24.aes_fi.107222149255285575346124115572359569747086946177578622633382632086859217900505
Line 295, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/24.aes_fi/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/aes_unmasked-sim-xcelium/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,993): (time 13915267 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscIv has failed (2 cycles, starting 13894859 PS)
  UVM_ERROR @  13915267 ps: (aes_core.sv:993) [ASSERT FAILED] AesSecCmDataRegLocalEscIv
  UVM_INFO @  13915267 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (aes_base_vseq.sv:74) [aes_alert_reset_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 5.aes_stress_all_with_rand_reset.75136438173176016458542726466713779984064093340574777775711231535944656792361
    Line 460, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/5.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 668515602 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 668515602 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_base_vseq.sv:74) [aes_reseed_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 9.aes_stress_all_with_rand_reset.99883080714340890396658029724380935083364499531496914607755797463633888091817
    Line 140, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/9.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @  47538388 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @  47538388 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

xmsim: *E,ASRTST (/nightly/runs/scratch/master/aes_unmasked-sim-xcelium/default/src/lowrisc_ip_aes_*/rtl/aes_core.sv,987): Assertion AesSecCmDataRegLocalEscDataOut has failed (* cycles, starting * PS) has 1 failures:

Test aes_fi has 1 failures.

11.aes_fi.65745309551462097338995268906981961881123797679611444908739935532304239843302
Line 1383, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/11.aes_fi/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/aes_unmasked-sim-xcelium/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,987): (time 8649289 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscDataOut has failed (2 cycles, starting 8631107 PS)
        ($past(iv_q) != $past(state_done_transposed, 2) ^ $past(data_in_prev_q, 2)))
                                                                                   |
  xmsim: *E,ASRTST (/nightly/runs/scratch/master/aes_unmasked-sim-xcelium/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,993): (time 8649289 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscIv has failed (2 cycles, starting 8631107 PS)
  UVM_ERROR @   8649289 ps: (aes_core.sv:987) [ASSERT FAILED] AesSecCmDataRegLocalEscDataOut

UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test aes_control_fi has 1 failures.
  - 212.aes_control_fi.93393359129047359304043396616067875027733299972422751289222712658021183157067
    Line 141, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/212.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```