CSRNG Simulation Results

Saturday February 08 2025 23:09:58 UTC

GitHub Revision: `c12958f63b`

Branch: master

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	9.000s	138.104us	50	50	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	6.000s	16.900us	5	5	100.00
V1	csr_rw	csrng_csr_rw	7.000s	93.493us	20	20	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	23.000s	944.772us	5	5	100.00
V1	csr_aliasing	csrng_csr_aliasing	10.000s	325.251us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	9.000s	354.248us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	7.000s	93.493us	20	20	100.00
		csrng_csr_aliasing	10.000s	325.251us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	interrupts	csrng_intr	4.567m	1.271ms	198	200	99.00
V2	alerts	csrng_alert	1.200m	7.150ms	498	500	99.60
V2	err	csrng_err	13.000s	126.112us	500	500	100.00
V2	cmds	csrng_cmds	6.083m	35.239ms	50	50	100.00
V2	life cycle	csrng_cmds	6.083m	35.239ms	50	50	100.00
V2	stress_all	csrng_stress_all	28.467m	176.228ms	48	50	96.00
V2	intr_test	csrng_intr_test	7.000s	154.040us	50	50	100.00
V2	alert_test	csrng_alert_test	9.000s	39.124us	50	50	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	14.000s	558.510us	20	20	100.00
V2	tl_d_illegal_access	csrng_tl_errors	14.000s	558.510us	20	20	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	6.000s	16.900us	5	5	100.00
		csrng_csr_rw	7.000s	93.493us	20	20	100.00
		csrng_csr_aliasing	10.000s	325.251us	5	5	100.00
		csrng_same_csr_outstanding	10.000s	245.571us	20	20	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	6.000s	16.900us	5	5	100.00
		csrng_csr_rw	7.000s	93.493us	20	20	100.00
		csrng_csr_aliasing	10.000s	325.251us	5	5	100.00
		csrng_same_csr_outstanding	10.000s	245.571us	20	20	100.00
V2		TOTAL			1434	1440	99.58
V2S	tl_intg_err	csrng_sec_cm	15.000s	189.725us	5	5	100.00
		csrng_tl_intg_err	42.600m	10.399ms	19	20	95.00
V2S	sec_cm_config_regwen	csrng_regwen	8.000s	165.240us	50	50	100.00
		csrng_csr_rw	7.000s	93.493us	20	20	100.00
V2S	sec_cm_config_mubi	csrng_alert	1.200m	7.150ms	498	500	99.60
V2S	sec_cm_intersig_mubi	csrng_stress_all	28.467m	176.228ms	48	50	96.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	4.567m	1.271ms	198	200	99.00
		csrng_err	13.000s	126.112us	500	500	100.00
		csrng_sec_cm	15.000s	189.725us	5	5	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	4.567m	1.271ms	198	200	99.00
		csrng_err	13.000s	126.112us	500	500	100.00
		csrng_sec_cm	15.000s	189.725us	5	5	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	4.567m	1.271ms	198	200	99.00
		csrng_err	13.000s	126.112us	500	500	100.00
		csrng_sec_cm	15.000s	189.725us	5	5	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	4.567m	1.271ms	198	200	99.00
		csrng_err	13.000s	126.112us	500	500	100.00
		csrng_sec_cm	15.000s	189.725us	5	5	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	4.567m	1.271ms	198	200	99.00
		csrng_err	13.000s	126.112us	500	500	100.00
		csrng_sec_cm	15.000s	189.725us	5	5	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	4.567m	1.271ms	198	200	99.00
		csrng_err	13.000s	126.112us	500	500	100.00
		csrng_sec_cm	15.000s	189.725us	5	5	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	4.567m	1.271ms	198	200	99.00
		csrng_err	13.000s	126.112us	500	500	100.00
		csrng_sec_cm	15.000s	189.725us	5	5	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	1.200m	7.150ms	498	500	99.60
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	4.567m	1.271ms	198	200	99.00
		csrng_err	13.000s	126.112us	500	500	100.00
V2S	sec_cm_constants_lc_gated	csrng_stress_all	28.467m	176.228ms	48	50	96.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	1.200m	7.150ms	498	500	99.60
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	42.600m	10.399ms	19	20	95.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	4.567m	1.271ms	198	200	99.00
		csrng_err	13.000s	126.112us	500	500	100.00
		csrng_sec_cm	15.000s	189.725us	5	5	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	4.567m	1.271ms	198	200	99.00
		csrng_err	13.000s	126.112us	500	500	100.00
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	4.567m	1.271ms	198	200	99.00
		csrng_err	13.000s	126.112us	500	500	100.00
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	4.567m	1.271ms	198	200	99.00
		csrng_err	13.000s	126.112us	500	500	100.00
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	4.567m	1.271ms	198	200	99.00
		csrng_err	13.000s	126.112us	500	500	100.00
		csrng_sec_cm	15.000s	189.725us	5	5	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	4.567m	1.271ms	198	200	99.00
		csrng_err	13.000s	126.112us	500	500	100.00
V2S		TOTAL			74	75	98.67
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	1.250m	5.624ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1613	1630	98.96

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.78	98.60	96.62	99.94	97.54	92.08	100.00	97.35	91.07

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:891) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 9 failures:
- Test csrng_stress_all_with_rand_reset has 9 failures.
  - 0.csrng_stress_all_with_rand_reset.66370737695208826445550354256066407609130987809179030534358074148863770345924
    Line 105, in log /nightly/runs/scratch/master/csrng-sim-xcelium/0.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 5624448877 ps: (cip_base_vseq.sv:891) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 5624448877 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.csrng_stress_all_with_rand_reset.112513868002497063986218396344444719785147489899847468682968711966300225448549
    Line 104, in log /nightly/runs/scratch/master/csrng-sim-xcelium/2.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1510793144 ps: (cip_base_vseq.sv:891) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1510793144 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 7 more failures.

xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/src/lowrisc_ip_csrng_*/rtl/csrng_cmd_stage.sv,518): Assertion CsrngCmdStageGenbitsFifoPushExpected_A has failed has 2 failures:

Test csrng_intr has 2 failures.

5.csrng_intr.39873691719008939812323902456267448130890169524680640080939402362884713699229
Line 134, in log /nightly/runs/scratch/master/csrng-sim-xcelium/5.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_cmd_stage.sv,518): (time 203276618 PS) Assertion tb.dut.u_csrng_core.gen_cmd_stage[2].u_csrng_cmd_stage.CsrngCmdStageGenbitsFifoPushExpected_A has failed
  UVM_ERROR @ 203276618 ps: (csrng_cmd_stage.sv:518) [ASSERT FAILED] CsrngCmdStageGenbitsFifoPushExpected_A
  UVM_INFO @ 203276618 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

84.csrng_intr.1605675201866832044319818568421497476849822887382148669592953178697521850031
Line 134, in log /nightly/runs/scratch/master/csrng-sim-xcelium/84.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_cmd_stage.sv,518): (time 57930593 PS) Assertion tb.dut.u_csrng_core.gen_cmd_stage[2].u_csrng_cmd_stage.CsrngCmdStageGenbitsFifoPushExpected_A has failed
  UVM_ERROR @  57930593 ps: (csrng_cmd_stage.sv:518) [ASSERT FAILED] CsrngCmdStageGenbitsFifoPushExpected_A
  UVM_INFO @  57930593 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Job timed out after * minutes has 2 failures:
- Test csrng_alert has 2 failures.
  - 28.csrng_alert.73819239368824957429397468894197127461120730308997640673342358203671387885742
    Log /nightly/runs/scratch/master/csrng-sim-xcelium/28.csrng_alert/latest/run.log
```
  Job timed out after 60 minutes
```
  - 454.csrng_alert.92464565663672293407064579814590334753273737652626177339422079232537529350607
    Log /nightly/runs/scratch/master/csrng-sim-xcelium/454.csrng_alert/latest/run.log
```
  Job timed out after 60 minutes
```

UVM_ERROR (csrng_scoreboard.sv:166) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 2 failures:

Test csrng_stress_all has 2 failures.

32.csrng_stress_all.2652297272048819955349889832329999567319670692693594403967375753645889372597
Line 135, in log /nightly/runs/scratch/master/csrng-sim-xcelium/32.csrng_stress_all/latest/run.log

  UVM_ERROR @ 8470910025 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 8470910025 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

40.csrng_stress_all.70931954779593748909752345423999542106462271841631357820344917502812951156521
Line 135, in log /nightly/runs/scratch/master/csrng-sim-xcelium/40.csrng_stress_all/latest/run.log

  UVM_ERROR @ 3035779764 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 3035779764 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL sequencer [SEQ_NOT_DONE] Sequence m_edn_push_seq[*] already started has 1 failures:
- Test csrng_stress_all_with_rand_reset has 1 failures.
  - 1.csrng_stress_all_with_rand_reset.95383123504160130513033389913374138971553387474521900539293145395673897359736
    Line 111, in log /nightly/runs/scratch/master/csrng-sim-xcelium/1.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @  12918170 ps: uvm_test_top.env.m_edn_agent[0].m_cmd_push_agent.sequencer [SEQ_NOT_DONE] Sequence uvm_test_top.env.m_edn_agent[0].m_cmd_push_agent.sequencer.m_edn_push_seq[0] already started
  UVM_INFO @  12918170 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (cip_base_vseq.sv:666) [csrng_common_vseq] timeout wait for alert handshake:fatal_alert has 1 failures:
- Test csrng_tl_intg_err has 1 failures.
  - 2.csrng_tl_intg_err.8877862178143500980040929359029700924402571495806874105050180460401889666494
    Line 158, in log /nightly/runs/scratch/master/csrng-sim-xcelium/2.csrng_tl_intg_err/latest/run.log
```
  UVM_FATAL @ 10399065722 ps: (cip_base_vseq.sv:666) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] timeout wait for alert handshake:fatal_alert
  UVM_INFO @ 10399065722 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```