EDN Simulation Results

Saturday February 08 2025 23:09:58 UTC

GitHub Revision: c12958f63b

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke edn_smoke 1.960s 28.599us 50 50 100.00
V1 csr_hw_reset edn_csr_hw_reset 2.120s 118.632us 5 5 100.00
V1 csr_rw edn_csr_rw 2.090s 38.957us 20 20 100.00
V1 csr_bit_bash edn_csr_bit_bash 4.590s 709.829us 5 5 100.00
V1 csr_aliasing edn_csr_aliasing 2.520s 121.221us 5 5 100.00
V1 csr_mem_rw_with_rand_reset edn_csr_mem_rw_with_rand_reset 2.670s 59.519us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr edn_csr_rw 2.090s 38.957us 20 20 100.00
edn_csr_aliasing 2.520s 121.221us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 firmware edn_genbits 5.720s 762.130us 300 300 100.00
V2 csrng_commands edn_genbits 5.720s 762.130us 300 300 100.00
V2 genbits edn_genbits 5.720s 762.130us 300 300 100.00
V2 interrupts edn_intr 2.470s 20.882us 50 50 100.00
V2 alerts edn_alert 2.370s 215.954us 200 200 100.00
V2 errs edn_err 2.970s 46.755us 100 100 100.00
V2 disable edn_disable 1.910s 15.104us 50 50 100.00
edn_disable_auto_req_mode 2.160s 40.232us 50 50 100.00
V2 stress_all edn_stress_all 4.860s 708.781us 50 50 100.00
V2 intr_test edn_intr_test 2.140s 18.193us 50 50 100.00
V2 alert_test edn_alert_test 2.210s 58.647us 50 50 100.00
V2 tl_d_oob_addr_access edn_tl_errors 3.610s 112.286us 20 20 100.00
V2 tl_d_illegal_access edn_tl_errors 3.610s 112.286us 20 20 100.00
V2 tl_d_outstanding_access edn_csr_hw_reset 2.120s 118.632us 5 5 100.00
edn_csr_rw 2.090s 38.957us 20 20 100.00
edn_csr_aliasing 2.520s 121.221us 5 5 100.00
edn_same_csr_outstanding 2.570s 260.692us 20 20 100.00
V2 tl_d_partial_access edn_csr_hw_reset 2.120s 118.632us 5 5 100.00
edn_csr_rw 2.090s 38.957us 20 20 100.00
edn_csr_aliasing 2.520s 121.221us 5 5 100.00
edn_same_csr_outstanding 2.570s 260.692us 20 20 100.00
V2 TOTAL 940 940 100.00
V2S tl_intg_err edn_sec_cm 28.580s 922.548us 5 5 100.00
edn_tl_intg_err 9.930s 281.359us 20 20 100.00
V2S sec_cm_config_regwen edn_regwen 1.840s 20.829us 10 10 100.00
V2S sec_cm_config_mubi edn_alert 2.370s 215.954us 200 200 100.00
V2S sec_cm_main_sm_fsm_sparse edn_sec_cm 28.580s 922.548us 5 5 100.00
V2S sec_cm_ack_sm_fsm_sparse edn_sec_cm 28.580s 922.548us 5 5 100.00
V2S sec_cm_fifo_ctr_redun edn_sec_cm 28.580s 922.548us 5 5 100.00
V2S sec_cm_ctr_redun edn_sec_cm 28.580s 922.548us 5 5 100.00
V2S sec_cm_main_sm_ctr_local_esc edn_alert 2.370s 215.954us 200 200 100.00
edn_sec_cm 28.580s 922.548us 5 5 100.00
V2S sec_cm_cs_rdata_bus_consistency edn_alert 2.370s 215.954us 200 200 100.00
V2S sec_cm_tile_link_bus_integrity edn_tl_intg_err 9.930s 281.359us 20 20 100.00
V2S TOTAL 35 35 100.00
V3 stress_all_with_rand_reset edn_stress_all_with_rand_reset 1.667m 25.988ms 32 50 64.00
V3 TOTAL 32 50 64.00
TOTAL 1112 1130 98.41

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
95.95 98.21 94.29 97.02 92.44 96.33 99.78 93.56

Failure Buckets