ENTROPY_SRC Simulation Results

Saturday February 08 2025 23:09:58 UTC

GitHub Revision: c12958f63b

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke entropy_src_smoke 19.000s 105.074us 50 50 100.00
V1 csr_hw_reset entropy_src_csr_hw_reset 6.000s 102.078us 5 5 100.00
V1 csr_rw entropy_src_csr_rw 6.000s 15.354us 20 20 100.00
V1 csr_bit_bash entropy_src_csr_bit_bash 14.000s 1.702ms 5 5 100.00
V1 csr_aliasing entropy_src_csr_aliasing 9.000s 892.292us 5 5 100.00
V1 csr_mem_rw_with_rand_reset entropy_src_csr_mem_rw_with_rand_reset 7.000s 145.882us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr entropy_src_csr_rw 6.000s 15.354us 20 20 100.00
entropy_src_csr_aliasing 9.000s 892.292us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 firmware entropy_src_smoke 19.000s 105.074us 50 50 100.00
entropy_src_rng 5.717m 20.039ms 217 300 72.33
entropy_src_fw_ov 6.450m 20.070ms 174 300 58.00
V2 firmware_mode entropy_src_fw_ov 6.450m 20.070ms 174 300 58.00
V2 rng_mode entropy_src_rng 5.717m 20.039ms 217 300 72.33
V2 rng_max_rate entropy_src_rng_max_rate 11.317m 20.058ms 182 400 45.50
V2 health_checks entropy_src_rng 5.717m 20.039ms 217 300 72.33
V2 conditioning entropy_src_rng 5.717m 20.039ms 217 300 72.33
V2 interrupts entropy_src_rng 5.717m 20.039ms 217 300 72.33
entropy_src_intr 15.000s 2.291ms 50 50 100.00
V2 alerts entropy_src_rng 5.717m 20.039ms 217 300 72.33
entropy_src_functional_alerts 10.000s 110.259us 50 50 100.00
V2 stress_all entropy_src_stress_all 4.867m 19.176ms 48 50 96.00
V2 functional_errors entropy_src_functional_errors 16.617m 10.012ms 967 1000 96.70
V2 firmware_ov_read_contiguous_data entropy_src_fw_ov_contiguous 23.000s 1.363ms 50 50 100.00
V2 intr_test entropy_src_intr_test 6.000s 38.660us 50 50 100.00
V2 alert_test entropy_src_alert_test 6.000s 31.871us 50 50 100.00
V2 tl_d_oob_addr_access entropy_src_tl_errors 9.000s 241.988us 20 20 100.00
V2 tl_d_illegal_access entropy_src_tl_errors 9.000s 241.988us 20 20 100.00
V2 tl_d_outstanding_access entropy_src_csr_hw_reset 6.000s 102.078us 5 5 100.00
entropy_src_csr_rw 6.000s 15.354us 20 20 100.00
entropy_src_csr_aliasing 9.000s 892.292us 5 5 100.00
entropy_src_same_csr_outstanding 7.000s 610.527us 20 20 100.00
V2 tl_d_partial_access entropy_src_csr_hw_reset 6.000s 102.078us 5 5 100.00
entropy_src_csr_rw 6.000s 15.354us 20 20 100.00
entropy_src_csr_aliasing 9.000s 892.292us 5 5 100.00
entropy_src_same_csr_outstanding 7.000s 610.527us 20 20 100.00
V2 TOTAL 1878 2340 80.26
V2S tl_intg_err entropy_src_sec_cm 9.000s 147.650us 5 5 100.00
entropy_src_tl_intg_err 16.000s 705.738us 20 20 100.00
V2S sec_cm_config_regwen entropy_src_rng 5.717m 20.039ms 217 300 72.33
entropy_src_cfg_regwen 7.000s 68.769us 50 50 100.00
V2S sec_cm_config_mubi entropy_src_rng 5.717m 20.039ms 217 300 72.33
V2S sec_cm_config_redun entropy_src_rng 5.717m 20.039ms 217 300 72.33
V2S sec_cm_intersig_mubi entropy_src_rng 5.717m 20.039ms 217 300 72.33
entropy_src_fw_ov 6.450m 20.070ms 174 300 58.00
V2S sec_cm_main_sm_fsm_sparse entropy_src_functional_errors 16.617m 10.012ms 967 1000 96.70
entropy_src_sec_cm 9.000s 147.650us 5 5 100.00
V2S sec_cm_ack_sm_fsm_sparse entropy_src_functional_errors 16.617m 10.012ms 967 1000 96.70
entropy_src_sec_cm 9.000s 147.650us 5 5 100.00
V2S sec_cm_rng_bkgn_chk entropy_src_rng 5.717m 20.039ms 217 300 72.33
V2S sec_cm_fifo_ctr_redun entropy_src_functional_errors 16.617m 10.012ms 967 1000 96.70
entropy_src_sec_cm 9.000s 147.650us 5 5 100.00
V2S sec_cm_ctr_redun entropy_src_functional_errors 16.617m 10.012ms 967 1000 96.70
entropy_src_sec_cm 9.000s 147.650us 5 5 100.00
V2S sec_cm_ctr_local_esc entropy_src_functional_errors 16.617m 10.012ms 967 1000 96.70
V2S sec_cm_esfinal_rdata_bus_consistency entropy_src_functional_alerts 10.000s 110.259us 50 50 100.00
V2S sec_cm_tile_link_bus_integrity entropy_src_tl_intg_err 16.000s 705.738us 20 20 100.00
V2S TOTAL 75 75 100.00
V3 external_health_tests entropy_src_rng_with_xht_rsps 5.483m 18.019ms 29 50 58.00
V3 TOTAL 29 50 58.00
TOTAL 2087 2570 81.21

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
97.12 98.15 95.32 98.33 95.59 96.77 96.88 90.95 95.77

Failure Buckets