| V1 |
smoke |
gpio_smoke |
3.160s |
70.572us |
50 |
50 |
100.00 |
|
|
gpio_smoke_no_pullup_pulldown |
3.300s |
631.493us |
50 |
50 |
100.00 |
|
|
gpio_smoke_en_cdc_prim |
3.530s |
144.423us |
50 |
50 |
100.00 |
|
|
gpio_smoke_no_pullup_pulldown_en_cdc_prim |
3.710s |
115.559us |
50 |
50 |
100.00 |
| V1 |
csr_hw_reset |
gpio_csr_hw_reset |
1.620s |
78.389us |
5 |
5 |
100.00 |
| V1 |
csr_rw |
gpio_csr_rw |
1.700s |
11.368us |
20 |
20 |
100.00 |
| V1 |
csr_bit_bash |
gpio_csr_bit_bash |
3.580s |
380.488us |
5 |
5 |
100.00 |
| V1 |
csr_aliasing |
gpio_csr_aliasing |
1.680s |
40.816us |
5 |
5 |
100.00 |
| V1 |
csr_mem_rw_with_rand_reset |
gpio_csr_mem_rw_with_rand_reset |
2.070s |
119.107us |
20 |
20 |
100.00 |
| V1 |
regwen_csr_and_corresponding_lockable_csr |
gpio_csr_rw |
1.700s |
11.368us |
20 |
20 |
100.00 |
|
|
gpio_csr_aliasing |
1.680s |
40.816us |
5 |
5 |
100.00 |
| V1 |
|
TOTAL |
|
|
255 |
255 |
100.00 |
| V2 |
direct_and_masked_out |
gpio_random_dout_din |
3.210s |
219.300us |
50 |
50 |
100.00 |
|
|
gpio_random_dout_din_no_pullup_pulldown |
3.020s |
54.722us |
50 |
50 |
100.00 |
| V2 |
out_in_regs_read_write |
gpio_dout_din_regs_random_rw |
3.060s |
41.130us |
50 |
50 |
100.00 |
| V2 |
gpio_interrupt_programming |
gpio_intr_rand_pgm |
3.220s |
40.949us |
50 |
50 |
100.00 |
| V2 |
random_interrupt_trigger |
gpio_rand_intr_trigger |
3.630s |
108.665us |
50 |
50 |
100.00 |
| V2 |
interrupt_and_noise_filter |
gpio_intr_with_filter_rand_intr_event |
4.150s |
264.601us |
50 |
50 |
100.00 |
| V2 |
noise_filter_stress |
gpio_filter_stress |
18.240s |
3.242ms |
50 |
50 |
100.00 |
| V2 |
regs_long_reads_and_writes |
gpio_random_long_reg_writes_reg_reads |
5.430s |
5.213ms |
50 |
50 |
100.00 |
| V2 |
full_random |
gpio_full_random |
3.000s |
37.964us |
50 |
50 |
100.00 |
| V2 |
stress_all |
gpio_stress_all |
2.509m |
21.375ms |
50 |
50 |
100.00 |
| V2 |
alert_test |
gpio_alert_test |
2.800s |
43.055us |
50 |
50 |
100.00 |
| V2 |
intr_test |
gpio_intr_test |
1.870s |
42.661us |
50 |
50 |
100.00 |
| V2 |
tl_d_oob_addr_access |
gpio_tl_errors |
3.360s |
67.042us |
20 |
20 |
100.00 |
| V2 |
tl_d_illegal_access |
gpio_tl_errors |
3.360s |
67.042us |
20 |
20 |
100.00 |
| V2 |
tl_d_outstanding_access |
gpio_csr_rw |
1.700s |
11.368us |
20 |
20 |
100.00 |
|
|
gpio_same_csr_outstanding |
1.910s |
91.385us |
20 |
20 |
100.00 |
|
|
gpio_csr_aliasing |
1.680s |
40.816us |
5 |
5 |
100.00 |
|
|
gpio_csr_hw_reset |
1.620s |
78.389us |
5 |
5 |
100.00 |
| V2 |
tl_d_partial_access |
gpio_csr_rw |
1.700s |
11.368us |
20 |
20 |
100.00 |
|
|
gpio_same_csr_outstanding |
1.910s |
91.385us |
20 |
20 |
100.00 |
|
|
gpio_csr_aliasing |
1.680s |
40.816us |
5 |
5 |
100.00 |
|
|
gpio_csr_hw_reset |
1.620s |
78.389us |
5 |
5 |
100.00 |
| V2 |
|
TOTAL |
|
|
640 |
640 |
100.00 |
| V2S |
tl_intg_err |
gpio_tl_intg_err |
5.520s |
579.001us |
20 |
20 |
100.00 |
|
|
gpio_sec_cm |
6.150s |
82.445us |
5 |
5 |
100.00 |
| V2S |
sec_cm_bus_integrity |
gpio_tl_intg_err |
5.520s |
579.001us |
20 |
20 |
100.00 |
| V2S |
|
TOTAL |
|
|
25 |
25 |
100.00 |
| V3 |
stress_all_with_rand_reset |
gpio_stress_all_with_rand_reset |
2.756m |
8.012ms |
50 |
50 |
100.00 |
| V3 |
|
TOTAL |
|
|
50 |
50 |
100.00 |
|
|
TOTAL |
|
|
970 |
970 |
100.00 |