HMAC Simulation Results

Saturday February 08 2025 23:09:58 UTC

GitHub Revision: c12958f63b

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	hmac_smoke	11.490s	5.031ms	50	50	100.00
V1	csr_hw_reset	hmac_csr_hw_reset	3.420s	31.826us	5	5	100.00
V1	csr_rw	hmac_csr_rw	3.290s	34.589us	20	20	100.00
V1	csr_bit_bash	hmac_csr_bit_bash	13.550s	1.589ms	5	5	100.00
V1	csr_aliasing	hmac_csr_aliasing	7.780s	1.855ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	hmac_csr_mem_rw_with_rand_reset	8.505m	72.346ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	hmac_csr_rw	3.290s	34.589us	20	20	100.00
		hmac_csr_aliasing	7.780s	1.855ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	long_msg	hmac_long_msg	1.195m	6.807ms	50	50	100.00
V2	back_pressure	hmac_back_pressure	1.154m	12.666ms	50	50	100.00
V2	test_vectors	hmac_test_sha256_vectors	3.384m	29.496ms	25	25	100.00
		hmac_test_sha384_vectors	7.862m	110.098ms	50	50	100.00
		hmac_test_sha512_vectors	7.709m	223.200ms	50	50	100.00
		hmac_test_hmac256_vectors	9.950s	738.008us	50	50	100.00
		hmac_test_hmac384_vectors	12.510s	3.708ms	60	60	100.00
		hmac_test_hmac512_vectors	13.270s	352.529us	75	75	100.00
V2	burst_wr	hmac_burst_wr	21.170s	693.803us	50	50	100.00
V2	datapath_stress	hmac_datapath_stress	20.980m	33.592ms	50	50	100.00
V2	error	hmac_error	1.664m	51.563ms	50	50	100.00
V2	wipe_secret	hmac_wipe_secret	1.419m	16.864ms	50	50	100.00
V2	save_and_restore	hmac_smoke	11.490s	5.031ms	50	50	100.00
		hmac_long_msg	1.195m	6.807ms	50	50	100.00
		hmac_back_pressure	1.154m	12.666ms	50	50	100.00
		hmac_datapath_stress	20.980m	33.592ms	50	50	100.00
		hmac_burst_wr	21.170s	693.803us	50	50	100.00
		hmac_stress_all	1.106h	332.279ms	50	50	100.00
V2	fifo_empty_status_interrupt	hmac_smoke	11.490s	5.031ms	50	50	100.00
		hmac_long_msg	1.195m	6.807ms	50	50	100.00
		hmac_back_pressure	1.154m	12.666ms	50	50	100.00
		hmac_datapath_stress	20.980m	33.592ms	50	50	100.00
		hmac_wipe_secret	1.419m	16.864ms	50	50	100.00
		hmac_test_sha256_vectors	3.384m	29.496ms	25	25	100.00
		hmac_test_sha384_vectors	7.862m	110.098ms	50	50	100.00
		hmac_test_sha512_vectors	7.709m	223.200ms	50	50	100.00
		hmac_test_hmac256_vectors	9.950s	738.008us	50	50	100.00
		hmac_test_hmac384_vectors	12.510s	3.708ms	60	60	100.00
		hmac_test_hmac512_vectors	13.270s	352.529us	75	75	100.00
V2	wide_digest_configurable_key_length	hmac_smoke	11.490s	5.031ms	50	50	100.00
		hmac_long_msg	1.195m	6.807ms	50	50	100.00
		hmac_back_pressure	1.154m	12.666ms	50	50	100.00
		hmac_datapath_stress	20.980m	33.592ms	50	50	100.00
		hmac_burst_wr	21.170s	693.803us	50	50	100.00
		hmac_error	1.664m	51.563ms	50	50	100.00
		hmac_wipe_secret	1.419m	16.864ms	50	50	100.00
		hmac_test_sha256_vectors	3.384m	29.496ms	25	25	100.00
		hmac_test_sha384_vectors	7.862m	110.098ms	50	50	100.00
		hmac_test_sha512_vectors	7.709m	223.200ms	50	50	100.00
		hmac_test_hmac256_vectors	9.950s	738.008us	50	50	100.00
		hmac_test_hmac384_vectors	12.510s	3.708ms	60	60	100.00
		hmac_test_hmac512_vectors	13.270s	352.529us	75	75	100.00
		hmac_stress_all	1.106h	332.279ms	50	50	100.00
V2	stress_all	hmac_stress_all	1.106h	332.279ms	50	50	100.00
V2	alert_test	hmac_alert_test	1.490s	34.204us	50	50	100.00
V2	intr_test	hmac_intr_test	3.130s	33.258us	50	50	100.00
V2	tl_d_oob_addr_access	hmac_tl_errors	4.680s	643.803us	20	20	100.00
V2	tl_d_illegal_access	hmac_tl_errors	4.680s	643.803us	20	20	100.00
V2	tl_d_outstanding_access	hmac_csr_hw_reset	3.420s	31.826us	5	5	100.00
		hmac_csr_rw	3.290s	34.589us	20	20	100.00
		hmac_csr_aliasing	7.780s	1.855ms	5	5	100.00
		hmac_same_csr_outstanding	4.380s	381.865us	20	20	100.00
V2	tl_d_partial_access	hmac_csr_hw_reset	3.420s	31.826us	5	5	100.00
		hmac_csr_rw	3.290s	34.589us	20	20	100.00
		hmac_csr_aliasing	7.780s	1.855ms	5	5	100.00
		hmac_same_csr_outstanding	4.380s	381.865us	20	20	100.00
V2		TOTAL			800	800	100.00
V2S	tl_intg_err	hmac_sec_cm	3.970s	722.121us	5	5	100.00
		hmac_tl_intg_err	10.790s	595.085us	20	20	100.00
V2S	sec_cm_bus_integrity	hmac_tl_intg_err	10.790s	595.085us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	write_config_and_secret_key_during_msg_wr	hmac_smoke	11.490s	5.031ms	50	50	100.00
V3	stress_reset	hmac_stress_reset	6.880s	2.675ms	50	50	100.00
V3	stress_all_with_rand_reset	hmac_stress_all_with_rand_reset	4.346m	12.495ms	10	10	100.00
V3		TOTAL			60	60	100.00
		TOTAL			990	990	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
90.08	96.31	95.93	100.00	94.12	97.90	99.03	47.30