c12958f63b| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | host_smoke | i2c_host_smoke | 1.116m | 4.365ms | 50 | 50 | 100.00 |
| V1 | target_smoke | i2c_target_smoke | 29.520s | 2.774ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | i2c_csr_hw_reset | 1.710s | 61.248us | 5 | 5 | 100.00 |
| V1 | csr_rw | i2c_csr_rw | 1.830s | 22.531us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | i2c_csr_bit_bash | 4.240s | 359.867us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | i2c_csr_aliasing | 2.640s | 456.328us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | i2c_csr_mem_rw_with_rand_reset | 2.170s | 34.639us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | i2c_csr_rw | 1.830s | 22.531us | 20 | 20 | 100.00 |
| i2c_csr_aliasing | 2.640s | 456.328us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 155 | 155 | 100.00 | |||
| V2 | host_error_intr | i2c_host_error_intr | 12.470s | 421.361us | 49 | 50 | 98.00 |
| V2 | host_stress_all | i2c_host_stress_all | 24.102m | 600.000ms | 10 | 50 | 20.00 |
| V2 | host_maxperf | i2c_host_perf | 33.246m | 50.298ms | 48 | 50 | 96.00 |
| V2 | host_override | i2c_host_override | 2.760s | 107.388us | 50 | 50 | 100.00 |
| V2 | host_fifo_watermark | i2c_host_fifo_watermark | 3.519m | 20.721ms | 50 | 50 | 100.00 |
| V2 | host_fifo_overflow | i2c_host_fifo_overflow | 1.884m | 11.565ms | 50 | 50 | 100.00 |
| V2 | host_fifo_reset | i2c_host_fifo_reset_fmt | 2.650s | 155.992us | 50 | 50 | 100.00 |
| i2c_host_fifo_fmt_empty | 15.380s | 1.020ms | 50 | 50 | 100.00 | ||
| i2c_host_fifo_reset_rx | 9.980s | 2.439ms | 50 | 50 | 100.00 | ||
| V2 | host_fifo_full | i2c_host_fifo_full | 2.699m | 13.322ms | 50 | 50 | 100.00 |
| V2 | host_timeout | i2c_host_stretch_timeout | 29.910s | 1.191ms | 50 | 50 | 100.00 |
| V2 | i2c_host_mode_toggle | i2c_host_mode_toggle | 5.000s | 582.728us | 14 | 50 | 28.00 |
| V2 | target_glitch | i2c_target_glitch | 7.620s | 4.040ms | 2 | 2 | 100.00 |
| V2 | target_stress_all | i2c_target_stress_all | 37.459m | 92.699ms | 49 | 50 | 98.00 |
| V2 | target_maxperf | i2c_target_perf | 5.750s | 1.000ms | 50 | 50 | 100.00 |
| V2 | target_fifo_empty | i2c_target_stress_rd | 58.650s | 1.976ms | 50 | 50 | 100.00 |
| i2c_target_intr_smoke | 6.380s | 3.366ms | 50 | 50 | 100.00 | ||
| V2 | target_fifo_reset | i2c_target_fifo_reset_acq | 2.200s | 282.242us | 50 | 50 | 100.00 |
| i2c_target_fifo_reset_tx | 2.230s | 296.324us | 50 | 50 | 100.00 | ||
| V2 | target_fifo_full | i2c_target_stress_wr | 19.313m | 72.105ms | 50 | 50 | 100.00 |
| i2c_target_stress_rd | 58.650s | 1.976ms | 50 | 50 | 100.00 | ||
| i2c_target_intr_stress_wr | 9.180m | 39.016ms | 50 | 50 | 100.00 | ||
| V2 | target_timeout | i2c_target_timeout | 5.750s | 6.037ms | 50 | 50 | 100.00 |
| V2 | target_clock_stretch | i2c_target_stretch | 2.236m | 4.166ms | 46 | 50 | 92.00 |
| V2 | bad_address | i2c_target_bad_addr | 5.890s | 2.817ms | 50 | 50 | 100.00 |
| V2 | target_mode_glitch | i2c_target_hrst | 19.560s | 10.016ms | 29 | 50 | 58.00 |
| V2 | target_fifo_watermark | i2c_target_fifo_watermarks_acq | 3.040s | 2.351ms | 50 | 50 | 100.00 |
| i2c_target_fifo_watermarks_tx | 2.090s | 804.218us | 49 | 50 | 98.00 | ||
| V2 | host_mode_config_perf | i2c_host_perf | 33.246m | 50.298ms | 48 | 50 | 96.00 |
| i2c_host_perf_precise | 12.542m | 24.301ms | 50 | 50 | 100.00 | ||
| V2 | host_mode_clock_stretching | i2c_host_stretch_timeout | 29.910s | 1.191ms | 50 | 50 | 100.00 |
| V2 | target_mode_tx_stretch_ctrl | i2c_target_tx_stretch_ctrl | 23.920s | 2.971ms | 46 | 50 | 92.00 |
| V2 | target_mode_nack_generation | i2c_target_nack_acqfull | 3.060s | 2.546ms | 50 | 50 | 100.00 |
| i2c_target_nack_acqfull_addr | 2.840s | 1.075ms | 50 | 50 | 100.00 | ||
| i2c_target_nack_txstretch | 2.180s | 533.136us | 34 | 50 | 68.00 | ||
| V2 | host_mode_halt_on_nak | i2c_host_may_nack | 19.990s | 719.410us | 50 | 50 | 100.00 |
| V2 | target_mode_smbus_maxlen | i2c_target_smbus_maxlen | 2.660s | 1.692ms | 50 | 50 | 100.00 |
| V2 | alert_test | i2c_alert_test | 1.610s | 122.636us | 50 | 50 | 100.00 |
| V2 | intr_test | i2c_intr_test | 1.840s | 57.906us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | i2c_tl_errors | 2.910s | 159.846us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | i2c_tl_errors | 2.910s | 159.846us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | i2c_csr_hw_reset | 1.710s | 61.248us | 5 | 5 | 100.00 |
| i2c_csr_rw | 1.830s | 22.531us | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 2.640s | 456.328us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 2.110s | 47.082us | 19 | 20 | 95.00 | ||
| V2 | tl_d_partial_access | i2c_csr_hw_reset | 1.710s | 61.248us | 5 | 5 | 100.00 |
| i2c_csr_rw | 1.830s | 22.531us | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 2.640s | 456.328us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 2.110s | 47.082us | 19 | 20 | 95.00 | ||
| V2 | TOTAL | 1665 | 1792 | 92.91 | |||
| V2S | tl_intg_err | i2c_tl_intg_err | 4.340s | 139.003us | 20 | 20 | 100.00 |
| i2c_sec_cm | 2.590s | 71.947us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | i2c_tl_intg_err | 4.340s | 139.003us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | host_stress_all_with_rand_reset | i2c_host_stress_all_with_rand_reset | 14.800s | 927.652us | 0 | 10 | 0.00 |
| V3 | target_error_intr | i2c_target_unexp_stop | 2.370s | 1.444ms | 0 | 50 | 0.00 |
| V3 | target_stress_all_with_rand_reset | i2c_target_stress_all_with_rand_reset | 15.230s | 2.635ms | 0 | 10 | 0.00 |
| V3 | TOTAL | 0 | 70 | 0.00 | |||
| TOTAL | 1845 | 2042 | 90.35 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 88.72 | 97.41 | 89.78 | 77.78 | 73.21 | 94.32 | 98.51 | 90.00 |
UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 53 failures:
0.i2c_host_stress_all.91774025484424634925924892538473188612983708731614417727380578976467036159541
Line 114, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 42514773394 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @6492356
2.i2c_host_stress_all.48883385906400976849737734316346750036897857735445151213845776338181858197087
Line 147, in log /nightly/runs/scratch/master/i2c-sim-vcs/2.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 15149474505 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @6079906
... and 30 more failures.
0.i2c_host_mode_toggle.63511945579250119219521446360307745314019628984175666136710396986708820424468
Line 80, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 80813574 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @14371
1.i2c_host_mode_toggle.43941044001581713123447942165681264769598586323397691285138942056272346007677
Line 80, in log /nightly/runs/scratch/master/i2c-sim-vcs/1.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 143229052 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @33561
... and 19 more failures.
UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 34 failures:
0.i2c_target_unexp_stop.61954424140572130554824059563828849135729947417513186598364051400135459883500
Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 260653261 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 88 [0x58])
UVM_INFO @ 260653261 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.i2c_target_unexp_stop.55839356173290748874401944298067794724418486406768794051101760470342688721163
Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/3.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 216971108 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 68 [0x44])
UVM_INFO @ 216971108 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 30 more failures.
0.i2c_target_stress_all_with_rand_reset.75286728513375019076267390345058691250323561180716347339043844252127708087079
Line 91, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 156700860 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (91 [0x5b] vs 0 [0x0])
UVM_INFO @ 156700860 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
9.i2c_target_stress_all_with_rand_reset.99350565893684877194629664616730008366227109600756784733624115443895678734152
Line 125, in log /nightly/runs/scratch/master/i2c-sim-vcs/9.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 2574460137 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 0 [0x0])
UVM_INFO @ 2574460137 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! has 21 failures:
0.i2c_target_hrst.42926497497059219414285869802529086326490838213537157520501852951508130781759
Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_hrst/latest/run.log
UVM_FATAL @ 10014092489 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
UVM_INFO @ 10014092489 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.i2c_target_hrst.53450719831513712313708196344588300605920947604777372180670801653559420250883
Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/2.i2c_target_hrst/latest/run.log
UVM_FATAL @ 10507941353 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
UVM_INFO @ 10507941353 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 19 more failures.
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.target_nack_count reset value: * has 16 failures:
5.i2c_target_nack_txstretch.113673493198202885065900289035283998070332159762694908635424692524313758453786
Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/5.i2c_target_nack_txstretch/latest/run.log
UVM_ERROR @ 132918206 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
UVM_INFO @ 132918206 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
10.i2c_target_nack_txstretch.50396953789882680078164823949230743860888553783364004646303969939138991269588
Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/10.i2c_target_nack_txstretch/latest/run.log
UVM_ERROR @ 358950398 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
UVM_INFO @ 358950398 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 14 more failures.
UVM_ERROR (cip_base_vseq.sv:890) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 14 failures:
0.i2c_host_stress_all_with_rand_reset.80952111369899560884069911447410085253180677088532609870261072635869950678694
Line 91, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 286112339 ps: (cip_base_vseq.sv:890) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 286112339 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_host_stress_all_with_rand_reset.68311414443879521103283286500168107212009675531860034168173399730580526010572
Line 87, in log /nightly/runs/scratch/master/i2c-sim-vcs/1.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 962320784 ps: (cip_base_vseq.sv:890) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 962320784 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 8 more failures.
4.i2c_target_stress_all_with_rand_reset.51328705732641274603660683156874970363170098593423356421960128227613667603846
Line 97, in log /nightly/runs/scratch/master/i2c-sim-vcs/4.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 2635460062 ps: (cip_base_vseq.sv:890) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2635460062 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.i2c_target_stress_all_with_rand_reset.10939953007212797021699966040440267823454039718439972020413729712041865492846
Line 81, in log /nightly/runs/scratch/master/i2c-sim-vcs/5.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 603688034 ps: (cip_base_vseq.sv:890) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 603688034 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpRead has 12 failures:
9.i2c_host_mode_toggle.20646796501006962445543367220310722671472391276905536183581507735742737667447
Line 82, in log /nightly/runs/scratch/master/i2c-sim-vcs/9.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 93198660 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
--> EXP:
---------------------------------------------------
Name Type Size Value
---------------------------------------------------
13.i2c_host_mode_toggle.15507930443902212761923047757439150391310415922057381558340803068218301055832
Line 82, in log /nightly/runs/scratch/master/i2c-sim-vcs/13.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 114011703 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
--> EXP:
---------------------------------------------------
Name Type Size Value
---------------------------------------------------
... and 10 more failures.
UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [*] vs * [*]) has 9 failures:
1.i2c_target_unexp_stop.66815987768954633016827596604820451162234545736178044748184616297192036541045
Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/1.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 29999636 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
UVM_INFO @ 29999636 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
6.i2c_target_unexp_stop.50448308744121176503155795305627070234018089997046362380644023518717013420714
Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/6.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 98872025 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
UVM_INFO @ 98872025 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 7 more failures.
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))' has 9 failures:
2.i2c_target_unexp_stop.77373278158884336156578971796939057135972403749245469918447740975048530550153
Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/2.i2c_target_unexp_stop/latest/run.log
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
UVM_ERROR @ 137965849 ps: (i2c_fifos.sv:318) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
UVM_INFO @ 137965849 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
16.i2c_target_unexp_stop.69898697095882823920765964606348548784777480388765361128141992064370570114385
Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/16.i2c_target_unexp_stop/latest/run.log
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
UVM_ERROR @ 183050624 ps: (i2c_fifos.sv:318) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
UVM_INFO @ 183050624 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 7 more failures.
UVM_ERROR (i2c_scoreboard.sv:717) [scoreboard] controller_mode_wr_obs_fifo item uncompared: has 6 failures:
1.i2c_host_stress_all.22179218107457424097505918637077840363088379765587570479674237951380038728831
Line 227, in log /nightly/runs/scratch/master/i2c-sim-vcs/1.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 37191599524 ps: (i2c_scoreboard.sv:717) [uvm_test_top.env.scoreboard] controller_mode_wr_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @5387222
5.i2c_host_stress_all.72278225391006153757825989909548625902534807016532284153756967738002408131740
Line 198, in log /nightly/runs/scratch/master/i2c-sim-vcs/5.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 132808752449 ps: (i2c_scoreboard.sv:717) [uvm_test_top.env.scoreboard] controller_mode_wr_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @5999962
... and 4 more failures.
Error-[CNST-CIF] Constraints inconsistency failure has 5 failures:
5.i2c_target_tx_stretch_ctrl.29505321976137375397023581194960895506311481472518364258917158271016997160341
Line 118, in log /nightly/runs/scratch/master/i2c-sim-vcs/5.i2c_target_tx_stretch_ctrl/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 872
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
34.i2c_target_tx_stretch_ctrl.86160491460831150801296413798792044279888218819485940867422800883306006329430
Line 118, in log /nightly/runs/scratch/master/i2c-sim-vcs/34.i2c_target_tx_stretch_ctrl/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 872
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
... and 2 more failures.
47.i2c_target_fifo_watermarks_tx.106973877784786612994892736671788991418866570927120395559472255692667800849583
Line 115, in log /nightly/runs/scratch/master/i2c-sim-vcs/47.i2c_target_fifo_watermarks_tx/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 845
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
UVM_FATAL (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred! has 4 failures:
9.i2c_target_stretch.74450649655718353335879954934377767151422178275024591568059802234906791647025
Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/9.i2c_target_stretch/latest/run.log
UVM_FATAL @ 10003276109 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
UVM_INFO @ 10003276109 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
12.i2c_target_stretch.110532918223710801433948986238946704304218694960752425463429575654686091443781
Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/12.i2c_target_stretch/latest/run.log
UVM_FATAL @ 10067874265 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
UVM_INFO @ 10067874265 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 3 failures:
Test i2c_host_stress_all has 1 failures.
11.i2c_host_stress_all.56088123029641521315473564824725153474752068604848308515940566646709282957391
Line 182, in log /nightly/runs/scratch/master/i2c-sim-vcs/11.i2c_host_stress_all/latest/run.log
UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test i2c_host_perf has 2 failures.
18.i2c_host_perf.44526185796628880838106418421354855474524628601961076811898945226602399353143
Line 75, in log /nightly/runs/scratch/master/i2c-sim-vcs/18.i2c_host_perf/latest/run.log
UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
40.i2c_host_perf.48420075305654979508710727091191246287712237154793563323178525117566495675274
Line 75, in log /nightly/runs/scratch/master/i2c-sim-vcs/40.i2c_host_perf/latest/run.log
UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:794) [i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 2 failures:
2.i2c_target_stress_all_with_rand_reset.86298485085465898814315774050194019369939163444208978427644634907460697369824
Line 79, in log /nightly/runs/scratch/master/i2c-sim-vcs/2.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 220577236 ps: (cip_base_vseq.sv:794) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 220577236 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.i2c_target_stress_all_with_rand_reset.70300304932062807293994056952173505290383936977517035925232534007106470717239
Line 81, in log /nightly/runs/scratch/master/i2c-sim-vcs/3.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 631038766 ps: (cip_base_vseq.sv:794) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 631038766 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) has 2 failures:
3.i2c_host_mode_toggle.102338529956503187114452172441988663980212235397136987857866331629845018603114
Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/3.i2c_host_mode_toggle/latest/run.log
UVM_FATAL @ 173434281 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=0xaff13a94, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
UVM_INFO @ 173434281 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
48.i2c_host_mode_toggle.88186245945847255122409281977751201160781918235729890452664566921614277043527
Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/48.i2c_host_mode_toggle/latest/run.log
UVM_FATAL @ 90845700 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=0x1730d914, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
UVM_INFO @ 90845700 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes has 2 failures:
Test i2c_host_error_intr has 1 failures.
18.i2c_host_error_intr.29250698493226245711036954223812004975988189500343251438059907008476832670068
Log /nightly/runs/scratch/master/i2c-sim-vcs/18.i2c_host_error_intr/latest/run.log
Job timed out after 60 minutes
Test i2c_host_stress_all has 1 failures.
24.i2c_host_stress_all.99908695579232911463823140345309075075326503218827133012485760588945685313669
Log /nightly/runs/scratch/master/i2c-sim-vcs/24.i2c_host_stress_all/latest/run.log
Job timed out after 60 minutes
UVM_ERROR (i2c_base_vseq.sv:760) [i2c_target_timeout_vseq] Check failed (cfg.m_i2c_agent_cfg.rcvd_rd_byte == *) has 1 failures:
1.i2c_target_stress_all_with_rand_reset.70003664386475162610548672257871830920757738615047422102042727978818466416545
Line 116, in log /nightly/runs/scratch/master/i2c-sim-vcs/1.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 4290194484 ps: (i2c_base_vseq.sv:760) [uvm_test_top.env.virtual_sequencer.i2c_target_timeout_vseq] Check failed (cfg.m_i2c_agent_cfg.rcvd_rd_byte == 0)
UVM_INFO @ 4290194484 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:524) [i2c_common_vseq] Check failed data & ~ro_mask == * (* [*] vs * [*]) has 1 failures:
6.i2c_same_csr_outstanding.94273022779024574114973397553451720997452636410934609756740741279220278636060
Line 75, in log /nightly/runs/scratch/master/i2c-sim-vcs/6.i2c_same_csr_outstanding/latest/run.log
UVM_ERROR @ 98285827 ps: (cip_base_vseq.sv:524) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed data & ~ro_mask == 0 (64 [0x40] vs 0 [0x0])
UVM_INFO @ 98285827 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_base_vseq.sv:760) [i2c_target_perf_vseq] Check failed (cfg.m_i2c_agent_cfg.rcvd_rd_byte == *) has 1 failures:
8.i2c_target_stress_all_with_rand_reset.54100938660710443779491749080903063010611550364830998429274755686136384527899
Line 112, in log /nightly/runs/scratch/master/i2c-sim-vcs/8.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 6215231374 ps: (i2c_base_vseq.sv:760) [uvm_test_top.env.virtual_sequencer.i2c_target_perf_vseq] Check failed (cfg.m_i2c_agent_cfg.rcvd_rd_byte == 0)
UVM_INFO @ 6215231374 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred! has 1 failures:
18.i2c_target_stress_all.115361836072600119937061291498432938809948649089932105109681393939559712024790
Line 108, in log /nightly/runs/scratch/master/i2c-sim-vcs/18.i2c_target_stress_all/latest/run.log
UVM_FATAL @ 77977101497 ps: (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred!
UVM_INFO @ 77977101497 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Error-[NOA] Null object access has 1 failures:
26.i2c_host_mode_toggle.34778058299766396991402521581217564842731273274198973105696362590146694654866
Line 81, in log /nightly/runs/scratch/master/i2c-sim-vcs/26.i2c_host_mode_toggle/latest/run.log
Error-[NOA] Null object access
../src/lowrisc_dv_i2c_env_0.1/i2c_reference_model.sv, 584
The object at dereference depth 0 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.