c12958f63b| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | keymgr_smoke | 27.270s | 5.808ms | 50 | 50 | 100.00 |
| V1 | random | keymgr_random | 31.830s | 1.775ms | 49 | 50 | 98.00 |
| V1 | csr_hw_reset | keymgr_csr_hw_reset | 2.280s | 60.462us | 5 | 5 | 100.00 |
| V1 | csr_rw | keymgr_csr_rw | 2.140s | 23.185us | 14 | 20 | 70.00 |
| V1 | csr_bit_bash | keymgr_csr_bit_bash | 8.630s | 994.027us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | keymgr_csr_aliasing | 5.960s | 732.801us | 3 | 5 | 60.00 |
| V1 | csr_mem_rw_with_rand_reset | keymgr_csr_mem_rw_with_rand_reset | 2.850s | 49.357us | 15 | 20 | 75.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | keymgr_csr_rw | 2.140s | 23.185us | 14 | 20 | 70.00 |
| keymgr_csr_aliasing | 5.960s | 732.801us | 3 | 5 | 60.00 | ||
| V1 | TOTAL | 141 | 155 | 90.97 | |||
| V2 | cfgen_during_op | keymgr_cfg_regwen | 57.620s | 3.576ms | 49 | 50 | 98.00 |
| V2 | sideload | keymgr_sideload | 41.420s | 6.049ms | 49 | 50 | 98.00 |
| keymgr_sideload_kmac | 26.910s | 2.264ms | 49 | 50 | 98.00 | ||
| keymgr_sideload_aes | 27.680s | 6.256ms | 50 | 50 | 100.00 | ||
| keymgr_sideload_otbn | 32.450s | 5.217ms | 50 | 50 | 100.00 | ||
| V2 | direct_to_disabled_state | keymgr_direct_to_disabled | 13.310s | 1.785ms | 49 | 50 | 98.00 |
| V2 | lc_disable | keymgr_lc_disable | 38.470s | 2.319ms | 48 | 50 | 96.00 |
| V2 | kmac_error_response | keymgr_kmac_rsp_err | 8.570s | 433.876us | 50 | 50 | 100.00 |
| V2 | invalid_sw_input | keymgr_sw_invalid_input | 35.660s | 16.044ms | 50 | 50 | 100.00 |
| V2 | invalid_hw_input | keymgr_hwsw_invalid_input | 24.260s | 1.093ms | 49 | 50 | 98.00 |
| V2 | sync_async_fault_cross | keymgr_sync_async_fault_cross | 13.680s | 753.920us | 49 | 50 | 98.00 |
| V2 | stress_all | keymgr_stress_all | 2.906m | 28.005ms | 46 | 50 | 92.00 |
| V2 | intr_test | keymgr_intr_test | 2.070s | 10.163us | 50 | 50 | 100.00 |
| V2 | alert_test | keymgr_alert_test | 2.010s | 22.902us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | keymgr_tl_errors | 4.420s | 144.502us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | keymgr_tl_errors | 4.420s | 144.502us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | keymgr_csr_hw_reset | 2.280s | 60.462us | 5 | 5 | 100.00 |
| keymgr_csr_rw | 2.140s | 23.185us | 14 | 20 | 70.00 | ||
| keymgr_csr_aliasing | 5.960s | 732.801us | 3 | 5 | 60.00 | ||
| keymgr_same_csr_outstanding | 3.020s | 97.491us | 12 | 20 | 60.00 | ||
| V2 | tl_d_partial_access | keymgr_csr_hw_reset | 2.280s | 60.462us | 5 | 5 | 100.00 |
| keymgr_csr_rw | 2.140s | 23.185us | 14 | 20 | 70.00 | ||
| keymgr_csr_aliasing | 5.960s | 732.801us | 3 | 5 | 60.00 | ||
| keymgr_same_csr_outstanding | 3.020s | 97.491us | 12 | 20 | 60.00 | ||
| V2 | TOTAL | 720 | 740 | 97.30 | |||
| V2S | sec_cm_additional_check | keymgr_sec_cm | 26.570s | 3.168ms | 5 | 5 | 100.00 |
| V2S | tl_intg_err | keymgr_sec_cm | 26.570s | 3.168ms | 5 | 5 | 100.00 |
| keymgr_tl_intg_err | 14.080s | 2.955ms | 12 | 20 | 60.00 | ||
| V2S | shadow_reg_update_error | keymgr_shadow_reg_errors | 4.380s | 369.891us | 5 | 20 | 25.00 |
| V2S | shadow_reg_read_clear_staged_value | keymgr_shadow_reg_errors | 4.380s | 369.891us | 5 | 20 | 25.00 |
| V2S | shadow_reg_storage_error | keymgr_shadow_reg_errors | 4.380s | 369.891us | 5 | 20 | 25.00 |
| V2S | shadowed_reset_glitch | keymgr_shadow_reg_errors | 4.380s | 369.891us | 5 | 20 | 25.00 |
| V2S | shadow_reg_update_error_with_csr_rw | keymgr_shadow_reg_errors_with_csr_rw | 13.740s | 516.716us | 3 | 20 | 15.00 |
| V2S | prim_count_check | keymgr_sec_cm | 26.570s | 3.168ms | 5 | 5 | 100.00 |
| V2S | prim_fsm_check | keymgr_sec_cm | 26.570s | 3.168ms | 5 | 5 | 100.00 |
| V2S | sec_cm_bus_integrity | keymgr_tl_intg_err | 14.080s | 2.955ms | 12 | 20 | 60.00 |
| V2S | sec_cm_config_shadow | keymgr_shadow_reg_errors | 4.380s | 369.891us | 5 | 20 | 25.00 |
| V2S | sec_cm_op_config_regwen | keymgr_cfg_regwen | 57.620s | 3.576ms | 49 | 50 | 98.00 |
| V2S | sec_cm_reseed_config_regwen | keymgr_random | 31.830s | 1.775ms | 49 | 50 | 98.00 |
| keymgr_csr_rw | 2.140s | 23.185us | 14 | 20 | 70.00 | ||
| V2S | sec_cm_sw_binding_config_regwen | keymgr_random | 31.830s | 1.775ms | 49 | 50 | 98.00 |
| keymgr_csr_rw | 2.140s | 23.185us | 14 | 20 | 70.00 | ||
| V2S | sec_cm_max_key_ver_config_regwen | keymgr_random | 31.830s | 1.775ms | 49 | 50 | 98.00 |
| keymgr_csr_rw | 2.140s | 23.185us | 14 | 20 | 70.00 | ||
| V2S | sec_cm_lc_ctrl_intersig_mubi | keymgr_lc_disable | 38.470s | 2.319ms | 48 | 50 | 96.00 |
| V2S | sec_cm_constants_consistency | keymgr_hwsw_invalid_input | 24.260s | 1.093ms | 49 | 50 | 98.00 |
| V2S | sec_cm_intersig_consistency | keymgr_hwsw_invalid_input | 24.260s | 1.093ms | 49 | 50 | 98.00 |
| V2S | sec_cm_hw_key_sw_noaccess | keymgr_random | 31.830s | 1.775ms | 49 | 50 | 98.00 |
| V2S | sec_cm_output_keys_ctrl_redun | keymgr_sideload_protect | 18.340s | 3.814ms | 49 | 50 | 98.00 |
| V2S | sec_cm_ctrl_fsm_sparse | keymgr_sec_cm | 26.570s | 3.168ms | 5 | 5 | 100.00 |
| V2S | sec_cm_data_fsm_sparse | keymgr_sec_cm | 26.570s | 3.168ms | 5 | 5 | 100.00 |
| V2S | sec_cm_ctrl_fsm_local_esc | keymgr_sec_cm | 26.570s | 3.168ms | 5 | 5 | 100.00 |
| V2S | sec_cm_ctrl_fsm_consistency | keymgr_custom_cm | 20.950s | 506.622us | 50 | 50 | 100.00 |
| V2S | sec_cm_ctrl_fsm_global_esc | keymgr_lc_disable | 38.470s | 2.319ms | 48 | 50 | 96.00 |
| V2S | sec_cm_ctrl_ctr_redun | keymgr_sec_cm | 26.570s | 3.168ms | 5 | 5 | 100.00 |
| V2S | sec_cm_kmac_if_fsm_sparse | keymgr_sec_cm | 26.570s | 3.168ms | 5 | 5 | 100.00 |
| V2S | sec_cm_kmac_if_ctr_redun | keymgr_sec_cm | 26.570s | 3.168ms | 5 | 5 | 100.00 |
| V2S | sec_cm_kmac_if_cmd_ctrl_consistency | keymgr_custom_cm | 20.950s | 506.622us | 50 | 50 | 100.00 |
| V2S | sec_cm_kmac_if_done_ctrl_consistency | keymgr_custom_cm | 20.950s | 506.622us | 50 | 50 | 100.00 |
| V2S | sec_cm_reseed_ctr_redun | keymgr_sec_cm | 26.570s | 3.168ms | 5 | 5 | 100.00 |
| V2S | sec_cm_side_load_sel_ctrl_consistency | keymgr_custom_cm | 20.950s | 506.622us | 50 | 50 | 100.00 |
| V2S | sec_cm_sideload_ctrl_fsm_sparse | keymgr_sec_cm | 26.570s | 3.168ms | 5 | 5 | 100.00 |
| V2S | sec_cm_ctrl_key_integrity | keymgr_custom_cm | 20.950s | 506.622us | 50 | 50 | 100.00 |
| V2S | TOTAL | 124 | 165 | 75.15 | |||
| V3 | stress_all_with_rand_reset | keymgr_stress_all_with_rand_reset | 21.350s | 1.439ms | 24 | 50 | 48.00 |
| V3 | TOTAL | 24 | 50 | 48.00 | |||
| TOTAL | 1009 | 1110 | 90.90 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 97.78 | 99.02 | 98.03 | 98.56 | 100.00 | 99.01 | 98.61 | 91.22 |
Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 38 failures:
Test keymgr_csr_rw has 6 failures.
0.keymgr_csr_rw.48813440411702396981861881573865822476479908251175464610184349833309380620829
Line 76, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_csr_rw/latest/run.log
Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[20] & 'hffffffff)))'
UVM_ERROR @ 7202043 ps: (keymgr_csr_assert_fpv.sv:466) [ASSERT FAILED] attest_sw_binding_7_rd_A
UVM_INFO @ 7202043 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.keymgr_csr_rw.76012939842846978601802174996580799688421375283792842502658521773061582800621
Line 76, in log /nightly/runs/scratch/master/keymgr-sim-vcs/5.keymgr_csr_rw/latest/run.log
Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[7] & 'hffffffff)))'
UVM_ERROR @ 25914386 ps: (keymgr_csr_assert_fpv.sv:401) [ASSERT FAILED] sealing_sw_binding_2_rd_A
UVM_INFO @ 25914386 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
Test keymgr_csr_aliasing has 2 failures.
0.keymgr_csr_aliasing.12288681735809078644574292742573194021472810489309969079119471402559720927249
Line 75, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_csr_aliasing/latest/run.log
Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[18] & 'hffffffff)))'
UVM_ERROR @ 488992116 ps: (keymgr_csr_assert_fpv.sv:456) [ASSERT FAILED] attest_sw_binding_5_rd_A
UVM_INFO @ 488992116 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.keymgr_csr_aliasing.51124347977062341762522720042717734382971175631575389927408808742069345127836
Line 76, in log /nightly/runs/scratch/master/keymgr-sim-vcs/2.keymgr_csr_aliasing/latest/run.log
Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[16] & 'hffffffff)))'
UVM_ERROR @ 178653643 ps: (keymgr_csr_assert_fpv.sv:446) [ASSERT FAILED] attest_sw_binding_3_rd_A
UVM_INFO @ 178653643 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test keymgr_csr_mem_rw_with_rand_reset has 5 failures.
0.keymgr_csr_mem_rw_with_rand_reset.53975306728255202707942267032842586388823242003641994416835005107560400175881
Line 77, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_csr_mem_rw_with_rand_reset/latest/run.log
Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[7] & 'hffffffff)))'
UVM_ERROR @ 17643781 ps: (keymgr_csr_assert_fpv.sv:401) [ASSERT FAILED] sealing_sw_binding_2_rd_A
UVM_INFO @ 17643781 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.keymgr_csr_mem_rw_with_rand_reset.53926924527923253335980953690970371458492323965763893867042022234614609675912
Line 77, in log /nightly/runs/scratch/master/keymgr-sim-vcs/4.keymgr_csr_mem_rw_with_rand_reset/latest/run.log
Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[17] & 'hffffffff)))'
UVM_ERROR @ 23619687 ps: (keymgr_csr_assert_fpv.sv:451) [ASSERT FAILED] attest_sw_binding_4_rd_A
UVM_INFO @ 23619687 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
Test keymgr_tl_intg_err has 8 failures.
1.keymgr_tl_intg_err.1860474074434528383207997534464795635308726619893384783602778088843294970533
Line 90, in log /nightly/runs/scratch/master/keymgr-sim-vcs/1.keymgr_tl_intg_err/latest/run.log
Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[9] & 'hffffffff)))'
UVM_ERROR @ 50396067 ps: (keymgr_csr_assert_fpv.sv:411) [ASSERT FAILED] sealing_sw_binding_4_rd_A
UVM_INFO @ 50396067 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.keymgr_tl_intg_err.96811327568267824342592448446962768056181455028763977814592449170271144345912
Line 93, in log /nightly/runs/scratch/master/keymgr-sim-vcs/3.keymgr_tl_intg_err/latest/run.log
Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[20] & 'hffffffff)))'
UVM_ERROR @ 117797139 ps: (keymgr_csr_assert_fpv.sv:466) [ASSERT FAILED] attest_sw_binding_7_rd_A
UVM_INFO @ 117797139 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 6 more failures.
Test keymgr_same_csr_outstanding has 8 failures.
2.keymgr_same_csr_outstanding.17841558126858016486952530659151103395616947240520787639302522063220735826660
Line 75, in log /nightly/runs/scratch/master/keymgr-sim-vcs/2.keymgr_same_csr_outstanding/latest/run.log
Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[5] & 'hffffffff)))'
UVM_ERROR @ 166727447 ps: (keymgr_csr_assert_fpv.sv:391) [ASSERT FAILED] sealing_sw_binding_0_rd_A
UVM_INFO @ 166727447 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.keymgr_same_csr_outstanding.67293232817405432341577945431798138299854123033989379026641425668802402176979
Line 76, in log /nightly/runs/scratch/master/keymgr-sim-vcs/4.keymgr_same_csr_outstanding/latest/run.log
Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[15] & 'hffffffff)))'
UVM_ERROR @ 83442991 ps: (keymgr_csr_assert_fpv.sv:441) [ASSERT FAILED] attest_sw_binding_2_rd_A
UVM_INFO @ 83442991 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 6 more failures.
... and 1 more tests.
UVM_ERROR (cip_base_vseq.sv:890) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 24 failures:
1.keymgr_stress_all_with_rand_reset.96787991420192180713430063031045962821630205391469961953393877496039202418380
Line 142, in log /nightly/runs/scratch/master/keymgr-sim-vcs/1.keymgr_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 425050024 ps: (cip_base_vseq.sv:890) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 425050024 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.keymgr_stress_all_with_rand_reset.97294083179913972750957683413740023316589540597151968771746882224538257714663
Line 116, in log /nightly/runs/scratch/master/keymgr-sim-vcs/2.keymgr_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 111502584 ps: (cip_base_vseq.sv:890) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 111502584 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 22 more failures.
UVM_FATAL (alert_receiver_driver.sv:145) [driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q has 23 failures:
0.keymgr_shadow_reg_errors.89362114104235348216627363734483341284145340573772091408723327030581948001826
Line 95, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_shadow_reg_errors/latest/run.log
UVM_FATAL @ 50864956 ps: (alert_receiver_driver.sv:145) [uvm_test_top.env.m_alert_agent_fatal_fault_err.driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q
UVM_INFO @ 50864956 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.keymgr_shadow_reg_errors.75764628960301426312290955609460467833453166646456829270727642851116181302123
Line 92, in log /nightly/runs/scratch/master/keymgr-sim-vcs/1.keymgr_shadow_reg_errors/latest/run.log
UVM_FATAL @ 42893962 ps: (alert_receiver_driver.sv:145) [uvm_test_top.env.m_alert_agent_fatal_fault_err.driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q
UVM_INFO @ 42893962 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 13 more failures.
0.keymgr_shadow_reg_errors_with_csr_rw.45446207927201763342938574178196534792707944886537868002872566180197171803734
Line 77, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_shadow_reg_errors_with_csr_rw/latest/run.log
UVM_FATAL @ 39087994 ps: (alert_receiver_driver.sv:145) [uvm_test_top.env.m_alert_agent_fatal_fault_err.driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q
UVM_INFO @ 39087994 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.keymgr_shadow_reg_errors_with_csr_rw.72290262712312960982125957760479554021141895782806185437512889423698274337967
Line 92, in log /nightly/runs/scratch/master/keymgr-sim-vcs/1.keymgr_shadow_reg_errors_with_csr_rw/latest/run.log
UVM_FATAL @ 82892242 ps: (alert_receiver_driver.sv:145) [uvm_test_top.env.m_alert_agent_fatal_fault_err.driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q
UVM_INFO @ 82892242 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 6 more failures.
UVM_ERROR (cip_base_scoreboard.sv:323) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:* has 12 failures:
Test keymgr_lc_disable has 2 failures.
0.keymgr_lc_disable.77045617752859201783590742077014151781387523549162774648185479373935549726302
Line 162, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_lc_disable/latest/run.log
UVM_ERROR @ 24060295 ps: (cip_base_scoreboard.sv:323) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
UVM_INFO @ 24060295 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
23.keymgr_lc_disable.78275502432719660322898932165716368243466207900208319348723493949878371888871
Line 123, in log /nightly/runs/scratch/master/keymgr-sim-vcs/23.keymgr_lc_disable/latest/run.log
UVM_ERROR @ 41938147 ps: (cip_base_scoreboard.sv:323) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:2000
UVM_INFO @ 41938147 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test keymgr_sideload has 1 failures.
14.keymgr_sideload.48204239573319619541189481877127540936117822603070880020682860301429900950802
Line 211, in log /nightly/runs/scratch/master/keymgr-sim-vcs/14.keymgr_sideload/latest/run.log
UVM_ERROR @ 194055134 ps: (cip_base_scoreboard.sv:323) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
UVM_INFO @ 194055134 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test keymgr_hwsw_invalid_input has 1 failures.
14.keymgr_hwsw_invalid_input.11660629923465269660373331961983327599990636599465031679067850615660854699245
Line 496, in log /nightly/runs/scratch/master/keymgr-sim-vcs/14.keymgr_hwsw_invalid_input/latest/run.log
UVM_ERROR @ 1092539371 ps: (cip_base_scoreboard.sv:323) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
UVM_INFO @ 1092539371 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test keymgr_stress_all has 4 failures.
15.keymgr_stress_all.61236649790940901330521058557993583754731329384071835017659445757782530846952
Line 1393, in log /nightly/runs/scratch/master/keymgr-sim-vcs/15.keymgr_stress_all/latest/run.log
UVM_ERROR @ 446090174 ps: (cip_base_scoreboard.sv:323) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:2000
UVM_INFO @ 446090174 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
18.keymgr_stress_all.105256595117807643177620148742103922663663217704669296032727587312010410274779
Line 1199, in log /nightly/runs/scratch/master/keymgr-sim-vcs/18.keymgr_stress_all/latest/run.log
UVM_ERROR @ 11124407549 ps: (cip_base_scoreboard.sv:323) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
UVM_INFO @ 11124407549 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
Test keymgr_random has 1 failures.
24.keymgr_random.32791254128823519483095619460979343293227262618020237670244037547014674906598
Line 305, in log /nightly/runs/scratch/master/keymgr-sim-vcs/24.keymgr_random/latest/run.log
UVM_ERROR @ 398924034 ps: (cip_base_scoreboard.sv:323) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
UVM_INFO @ 398924034 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more tests.
UVM_ERROR (keymgr_sync_async_fault_cross_vseq.sv:38) [keymgr_sync_async_fault_cross_vseq] Check failed act_fault_status[keymgr_pkg::FaultKmacOp] || act_fault_status[keymgr_pkg::FaultKmacOut] == * (* [*] vs * [*]) has 1 failures:
11.keymgr_sync_async_fault_cross.95060625168549910328541957961642233001144416048796309231764346816381144808414
Line 134, in log /nightly/runs/scratch/master/keymgr-sim-vcs/11.keymgr_sync_async_fault_cross/latest/run.log
UVM_ERROR @ 1000926423 ps: (keymgr_sync_async_fault_cross_vseq.sv:38) [uvm_test_top.env.virtual_sequencer.keymgr_sync_async_fault_cross_vseq] Check failed act_fault_status[keymgr_pkg::FaultKmacOp] || act_fault_status[keymgr_pkg::FaultKmacOut] == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 1000926423 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (keymgr_scoreboard.sv:766) [scoreboard] Check failed item.d_data !=gmv(csr) (* [] vs * []) reg name: keymgr_reg_block.sw_share1_output_*` has 1 failures:
19.keymgr_stress_all_with_rand_reset.57429153473371261950208622905651182034097563358603907894295077109814477959287
Line 292, in log /nightly/runs/scratch/master/keymgr-sim-vcs/19.keymgr_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 75056642 ps: (keymgr_scoreboard.sv:766) [uvm_test_top.env.scoreboard] Check failed item.d_data != `gmv(csr) (2839032954 [0xa938347a] vs 2839032954 [0xa938347a]) reg name: keymgr_reg_block.sw_share1_output_6
UVM_INFO @ 75056642 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:249) scoreboard [scoreboard] alert recov_operation_err has unexpected timeout error has 1 failures:
40.keymgr_cfg_regwen.89724415952557695207733223625573480031273486104206101146316185526118097123692
Line 219, in log /nightly/runs/scratch/master/keymgr-sim-vcs/40.keymgr_cfg_regwen/latest/run.log
UVM_ERROR @ 152467511 ps: (cip_base_scoreboard.sv:249) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err has unexpected timeout error
UVM_INFO @ 152467511 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:794) [keymgr_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
46.keymgr_stress_all_with_rand_reset.22374557507411620726253172229121187312098849800340844268687833250742281749073
Line 818, in log /nightly/runs/scratch/master/keymgr-sim-vcs/46.keymgr_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 828557061 ps: (cip_base_vseq.sv:794) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 828557061 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---