KMAC/MASKED Simulation Results

Saturday February 08 2025 23:09:58 UTC

GitHub Revision: `c12958f63b`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	54.920s	8.453ms	49	50	98.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.840s	24.113us	5	5	100.00
V1	csr_rw	kmac_csr_rw	2.010s	20.915us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	10.410s	1.132ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	7.560s	2.456ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.910s	347.230us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	2.010s	20.915us	20	20	100.00
		kmac_csr_aliasing	7.560s	2.456ms	5	5	100.00
V1	mem_walk	kmac_mem_walk	1.610s	21.222us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.990s	40.448us	5	5	100.00
V1		TOTAL			114	115	99.13
V2	long_msg_and_output	kmac_long_msg_and_output	45.005m	556.537ms	50	50	100.00
V2	burst_write	kmac_burst_write	16.122m	74.807ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	26.008m	114.006ms	5	5	100.00
		kmac_test_vectors_sha3_256	25.983m	146.274ms	5	5	100.00
		kmac_test_vectors_sha3_384	18.560m	46.425ms	5	5	100.00
		kmac_test_vectors_sha3_512	15.180m	47.587ms	5	5	100.00
		kmac_test_vectors_shake_128	34.118m	757.663ms	5	5	100.00
		kmac_test_vectors_shake_256	26.097m	175.165ms	5	5	100.00
		kmac_test_vectors_kmac	4.190s	1.011ms	5	5	100.00
		kmac_test_vectors_kmac_xof	2.880s	369.910us	5	5	100.00
V2	sideload	kmac_sideload	5.892m	91.345ms	50	50	100.00
V2	app	kmac_app	4.245m	22.631ms	50	50	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	4.882m	23.612ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	4.406m	18.050ms	50	50	100.00
V2	error	kmac_error	5.488m	65.760ms	50	50	100.00
V2	key_error	kmac_key_error	9.610s	6.666ms	50	50	100.00
V2	sideload_invalid	kmac_sideload_invalid	8.240s	351.404us	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	34.330s	3.525ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	25.220s	2.013ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	48.110s	7.016ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	14.410s	3.762ms	50	50	100.00
V2	stress_all	kmac_stress_all	31.133m	521.062ms	50	50	100.00
V2	intr_test	kmac_intr_test	1.930s	44.342us	50	50	100.00
V2	alert_test	kmac_alert_test	1.640s	29.707us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.510s	685.552us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.510s	685.552us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.840s	24.113us	5	5	100.00
		kmac_csr_rw	2.010s	20.915us	20	20	100.00
		kmac_csr_aliasing	7.560s	2.456ms	5	5	100.00
		kmac_same_csr_outstanding	2.900s	104.047us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.840s	24.113us	5	5	100.00
		kmac_csr_rw	2.010s	20.915us	20	20	100.00
		kmac_csr_aliasing	7.560s	2.456ms	5	5	100.00
		kmac_same_csr_outstanding	2.900s	104.047us	20	20	100.00
V2		TOTAL			740	740	100.00
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.850s	238.086us	8	20	40.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.850s	238.086us	8	20	40.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.850s	238.086us	8	20	40.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.850s	238.086us	8	20	40.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	6.020s	186.880us	6	20	30.00
V2S	tl_intg_err	kmac_sec_cm	6.159m	4.677ms	5	5	100.00
		kmac_tl_intg_err	8.430s	924.533us	14	20	70.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	8.430s	924.533us	14	20	70.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	14.410s	3.762ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	54.920s	8.453ms	49	50	98.00
V2S	sec_cm_key_sideload	kmac_sideload	5.892m	91.345ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.850s	238.086us	8	20	40.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	6.159m	4.677ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	6.159m	4.677ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	6.159m	4.677ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	54.920s	8.453ms	49	50	98.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	14.410s	3.762ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	6.159m	4.677ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	4.636m	35.925ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	54.920s	8.453ms	49	50	98.00
V2S		TOTAL			43	75	57.33
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	1.544m	17.708ms	5	10	50.00
V3		TOTAL			5	10	50.00
		TOTAL			902	940	95.96

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.14	99.14	94.44	99.89	78.17	97.10	99.36	97.88

Failure Buckets

UVM_FATAL (alert_receiver_driver.sv:145) [driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q

has 22 failures:

Test kmac_shadow_reg_errors has 12 failures.

0.kmac_shadow_reg_errors.25891613047714385611610885820588932526813017938546854238967189841380834033937
Line 80, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/0.kmac_shadow_reg_errors/latest/run.log

  UVM_FATAL @  48765992 ps: (alert_receiver_driver.sv:145) [uvm_test_top.env.m_alert_agent_fatal_fault_err.driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q
  UVM_INFO @  48765992 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.kmac_shadow_reg_errors.92463481287999047064867545540159595253460686926001672031839264669518709791800
Line 75, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/1.kmac_shadow_reg_errors/latest/run.log

  UVM_FATAL @   5631940 ps: (alert_receiver_driver.sv:145) [uvm_test_top.env.m_alert_agent_fatal_fault_err.driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q
  UVM_INFO @   5631940 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 10 more failures.

Test kmac_shadow_reg_errors_with_csr_rw has 10 failures.

0.kmac_shadow_reg_errors_with_csr_rw.110722556933008281268344237497600724840564379560069837376915703557242273278758
Line 80, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/0.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

  UVM_FATAL @  36915543 ps: (alert_receiver_driver.sv:145) [uvm_test_top.env.m_alert_agent_fatal_fault_err.driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q
  UVM_INFO @  36915543 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.kmac_shadow_reg_errors_with_csr_rw.8564911005722333556369129302273964685916645115917023044189984732847864970079
Line 81, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/1.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

  UVM_FATAL @ 419834733 ps: (alert_receiver_driver.sv:145) [uvm_test_top.env.m_alert_agent_fatal_fault_err.driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q
  UVM_INFO @ 419834733 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 8 more failures.

Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 10 failures:

Test kmac_tl_intg_err has 6 failures.

3.kmac_tl_intg_err.30069807456332788227588622436848756561031378427758259750975106807487775598564
Line 83, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/3.kmac_tl_intg_err/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[48] & 'hffffffff)))'
  UVM_ERROR @  75845124 ps: (kmac_csr_assert_fpv.sv:537) [ASSERT FAILED] prefix_9_rd_A
  UVM_INFO @  75845124 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.kmac_tl_intg_err.43004642576913736446406509716797786496545980917342581670277153618432076981377
Line 90, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/4.kmac_tl_intg_err/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[39] & 'hffffffff)))'
  UVM_ERROR @  86213599 ps: (kmac_csr_assert_fpv.sv:492) [ASSERT FAILED] prefix_0_rd_A
  UVM_INFO @  86213599 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

Test kmac_shadow_reg_errors_with_csr_rw has 4 failures.

8.kmac_shadow_reg_errors_with_csr_rw.54940044309563147839609694256628396404382635445826688873182265159664454112015
Line 81, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/8.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[41] & 'hffffffff)))'
  UVM_ERROR @ 159798364 ps: (kmac_csr_assert_fpv.sv:502) [ASSERT FAILED] prefix_2_rd_A
  UVM_INFO @ 159798364 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

11.kmac_shadow_reg_errors_with_csr_rw.7503243198826150093530408556722431687769457517459402096205610721036346299556
Line 76, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/11.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[40] & 'hffffffff)))'
  UVM_ERROR @   8120104 ps: (kmac_csr_assert_fpv.sv:497) [ASSERT FAILED] prefix_1_rd_A
  UVM_INFO @   8120104 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

UVM_ERROR (kmac_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 5 failures:
- Test kmac_stress_all_with_rand_reset has 5 failures.
  - 0.kmac_stress_all_with_rand_reset.60881901367434238202012338812993301533268900777713599690701295248640515767224
    Line 87, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 515727154 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483664 [0x80000010]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 515727154 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.kmac_stress_all_with_rand_reset.44290623970123520901998432285725321693797844193197503794740052076187238299388
    Line 210, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 6506420836 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483648 [0x80000000]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 6506420836 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: * has 1 failures:
- Test kmac_smoke has 1 failures.
  - 1.kmac_smoke.88338909581958342900589526719837251233057645247478678131247459319449146180594
    Line 72, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/1.kmac_smoke/latest/run.log
```
  UVM_ERROR @  82880935 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  82880935 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```