OTBN Simulation Results

Saturday February 08 2025 23:09:58 UTC

GitHub Revision: `c12958f63b`

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	41.000s	140.244us	1	1	100.00
V1	single_binary	otbn_single	2.500m	854.905us	100	100	100.00
V1	csr_hw_reset	otbn_csr_hw_reset	8.000s	19.179us	5	5	100.00
V1	csr_rw	otbn_csr_rw	7.000s	36.627us	20	20	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	9.000s	167.116us	5	5	100.00
V1	csr_aliasing	otbn_csr_aliasing	8.000s	19.574us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	12.000s	48.235us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	7.000s	36.627us	20	20	100.00
		otbn_csr_aliasing	8.000s	19.574us	5	5	100.00
V1	mem_walk	otbn_mem_walk	31.000s	1.331ms	5	5	100.00
V1	mem_partial_access	otbn_mem_partial_access	19.000s	1.705ms	5	5	100.00
V1		TOTAL			166	166	100.00
V2	reset_recovery	otbn_reset	3.617m	1.262ms	10	10	100.00
V2	multi_error	otbn_multi_err	42.000s	649.603us	1	1	100.00
V2	back_to_back	otbn_multi	1.900m	535.771us	10	10	100.00
V2	stress_all	otbn_stress_all	1.117m	194.215us	10	10	100.00
V2	lc_escalation	otbn_escalate	26.000s	110.895us	60	60	100.00
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	9.000s	43.737us	5	5	100.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	13.000s	24.201us	10	10	100.00
V2	alert_test	otbn_alert_test	9.000s	20.572us	50	50	100.00
V2	intr_test	otbn_intr_test	10.000s	38.810us	50	50	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	10.000s	1.121ms	20	20	100.00
V2	tl_d_illegal_access	otbn_tl_errors	10.000s	1.121ms	20	20	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	8.000s	19.179us	5	5	100.00
		otbn_csr_rw	7.000s	36.627us	20	20	100.00
		otbn_csr_aliasing	8.000s	19.574us	5	5	100.00
		otbn_same_csr_outstanding	8.000s	17.293us	20	20	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	8.000s	19.179us	5	5	100.00
		otbn_csr_rw	7.000s	36.627us	20	20	100.00
		otbn_csr_aliasing	8.000s	19.574us	5	5	100.00
		otbn_same_csr_outstanding	8.000s	17.293us	20	20	100.00
V2		TOTAL			246	246	100.00
V2S	mem_integrity	otbn_imem_err	17.000s	118.507us	10	10	100.00
		otbn_dmem_err	12.000s	26.002us	15	15	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	14.000s	56.333us	5	5	100.00
		otbn_controller_ispr_rdata_err	15.000s	107.886us	5	5	100.00
		otbn_mac_bignum_acc_err	13.000s	303.369us	5	5	100.00
		otbn_urnd_err	8.000s	21.707us	2	2	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	9.000s	15.473us	5	5	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	11.000s	29.357us	2	2	100.00
V2S	otbn_non_sec_partial_wipe	otbn_partial_wipe	11.000s	75.186us	10	10	100.00
V2S	tl_intg_err	otbn_sec_cm	14.383m	5.067ms	1	5	20.00
		otbn_tl_intg_err	32.000s	190.201us	20	20	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	29.000s	196.268us	20	20	100.00
V2S	prim_fsm_check	otbn_sec_cm	14.383m	5.067ms	1	5	20.00
V2S	prim_count_check	otbn_sec_cm	14.383m	5.067ms	1	5	20.00
V2S	sec_cm_mem_scramble	otbn_smoke	41.000s	140.244us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	12.000s	26.002us	15	15	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	17.000s	118.507us	10	10	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	32.000s	190.201us	20	20	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	26.000s	110.895us	60	60	100.00
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	17.000s	118.507us	10	10	100.00
		otbn_dmem_err	12.000s	26.002us	15	15	100.00
		otbn_zero_state_err_urnd	9.000s	43.737us	5	5	100.00
		otbn_illegal_mem_acc	9.000s	15.473us	5	5	100.00
		otbn_sec_cm	14.383m	5.067ms	1	5	20.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	14.383m	5.067ms	1	5	20.00
V2S	sec_cm_scramble_key_sideload	otbn_single	2.500m	854.905us	100	100	100.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	17.000s	118.507us	10	10	100.00
		otbn_dmem_err	12.000s	26.002us	15	15	100.00
		otbn_zero_state_err_urnd	9.000s	43.737us	5	5	100.00
		otbn_illegal_mem_acc	9.000s	15.473us	5	5	100.00
		otbn_sec_cm	14.383m	5.067ms	1	5	20.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	14.383m	5.067ms	1	5	20.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	26.000s	110.895us	60	60	100.00
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	17.000s	118.507us	10	10	100.00
		otbn_dmem_err	12.000s	26.002us	15	15	100.00
		otbn_zero_state_err_urnd	9.000s	43.737us	5	5	100.00
		otbn_illegal_mem_acc	9.000s	15.473us	5	5	100.00
		otbn_sec_cm	14.383m	5.067ms	1	5	20.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	14.383m	5.067ms	1	5	20.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	2.500m	854.905us	100	100	100.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	11.000s	86.684us	12	12	100.00
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	11.000s	58.960us	5	5	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	1.367m	888.550us	5	5	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	1.367m	888.550us	5	5	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	11.000s	19.038us	10	10	100.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	14.383m	5.067ms	1	5	20.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	14.383m	5.067ms	1	5	20.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	17.000s	79.814us	10	10	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	14.383m	5.067ms	1	5	20.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	14.383m	5.067ms	1	5	20.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	1.250m	1.637ms	5	5	100.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	1.250m	1.637ms	5	5	100.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	11.000s	137.469us	5	7	71.43
V2S	sec_cm_data_mem_sec_wipe	otbn_single	2.500m	854.905us	100	100	100.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	2.500m	854.905us	100	100	100.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	2.500m	854.905us	100	100	100.00
V2S	sec_cm_write_mem_integrity	otbn_multi	1.900m	535.771us	10	10	100.00
V2S	sec_cm_ctrl_flow_count	otbn_single	2.500m	854.905us	100	100	100.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	2.500m	854.905us	100	100	100.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	15.000s	33.632us	5	5	100.00
V2S	sec_cm_key_sideload	otbn_single	2.500m	854.905us	100	100	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	14.383m	5.067ms	1	5	20.00
V2S		TOTAL			157	163	96.32
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	3.933m	2.054ms	3	10	30.00
V3		TOTAL			3	10	30.00
		TOTAL			572	585	97.78

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
99.07	99.60	95.44	99.69	93.43	93.59	100.00	98.16	99.58

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:891) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 6 failures:
- Test otbn_stress_all_with_rand_reset has 6 failures.
  - 0.otbn_stress_all_with_rand_reset.40993485362502247562016857451880737459720538959218439008926199864304807868023
    Line 189, in log /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 926855533 ps: (cip_base_vseq.sv:891) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 926855533 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.otbn_stress_all_with_rand_reset.62985023135175160468656921792609994192831690736132094639789787224297802317374
    Line 408, in log /nightly/runs/scratch/master/otbn-sim-xcelium/2.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1204204257 ps: (cip_base_vseq.sv:891) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1204204257 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 4 more failures.

xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_*/rtl/otbn.sv,1383): Assertion ErrBitsKnown_A has failed has 4 failures:

Test otbn_sec_cm has 4 failures.

1.otbn_sec_cm.56317329910470029143990058408795720027500873049434635956405075119738548299802
Line 91, in log /nightly/runs/scratch/master/otbn-sim-xcelium/1.otbn_sec_cm/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1383): (time 48785552 PS) Assertion tb.dut.ErrBitsKnown_A has failed
  xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,948): (time 48785552 PS) Assertion tb.dut.u_otbn_core.DoneOKnown_A has failed
  xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,949): (time 48785552 PS) Assertion tb.dut.u_otbn_core.ImemReqOKnown_A has failed
  xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,950): (time 48785552 PS) Assertion tb.dut.u_otbn_core.ImemAddrOKnown_AKnownEnable has failed
  xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 48785552 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed

2.otbn_sec_cm.1652292809084394178639720512185760692798915778042245597306625421141202858499
Line 116, in log /nightly/runs/scratch/master/otbn-sim-xcelium/2.otbn_sec_cm/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1383): (time 172496865 PS) Assertion tb.dut.ErrBitsKnown_A has failed
  xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,948): (time 172496865 PS) Assertion tb.dut.u_otbn_core.DoneOKnown_A has failed
  xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,949): (time 172496865 PS) Assertion tb.dut.u_otbn_core.ImemReqOKnown_A has failed
  xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,950): (time 172496865 PS) Assertion tb.dut.u_otbn_core.ImemAddrOKnown_AKnownEnable has failed
  xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 172496865 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed

... and 2 more failures.

xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 2 failures:

Test otbn_sec_wipe_err has 2 failures.

0.otbn_sec_wipe_err.30179258957029318751626940158008657760336684667935668049110127578727711726987
Line 108, in log /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_sec_wipe_err/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 41003929 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  41003929 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  41003929 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.otbn_sec_wipe_err.74174278428014685389449750081860986000539256641373279524538899711743063055225
Line 110, in log /nightly/runs/scratch/master/otbn-sim-xcelium/1.otbn_sec_wipe_err/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 137469274 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @ 137469274 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @ 137469274 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (otbn_base_vseq.sv:348) [otbn_imem_err_vseq] Check failed (!cfg.under_reset) has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 9.otbn_stress_all_with_rand_reset.81601879112804781194000786453434445195012691142595427556753803752561382156278
    Line 258, in log /nightly/runs/scratch/master/otbn-sim-xcelium/9.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 367873974 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_imem_err_vseq] Check failed (!cfg.under_reset)
  UVM_INFO @ 367873974 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```