PATTGEN Simulation Results

Saturday February 08 2025 23:09:58 UTC

GitHub Revision: `c12958f63b`

Branch: master

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	20.000s	48.452us	50	50	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	6.000s	57.797us	5	5	100.00
V1	csr_rw	pattgen_csr_rw	7.000s	13.117us	20	20	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	8.000s	547.763us	5	5	100.00
V1	csr_aliasing	pattgen_csr_aliasing	6.000s	125.966us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	7.000s	79.023us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	7.000s	13.117us	20	20	100.00
		pattgen_csr_aliasing	6.000s	125.966us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	perf	pattgen_perf	1.400m	3.090ms	50	50	100.00
V2	cnt_rollover	cnt_rollover	1.133m	9.747ms	50	50	100.00
V2	error	pattgen_error	20.000s	29.623us	50	50	100.00
V2	stress_all	pattgen_stress_all	1.217m	5.378ms	50	50	100.00
V2	alert_test	pattgen_alert_test	18.000s	21.746us	50	50	100.00
V2	intr_test	pattgen_intr_test	7.000s	13.671us	50	50	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	8.000s	42.256us	20	20	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	8.000s	42.256us	20	20	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	6.000s	57.797us	5	5	100.00
		pattgen_csr_rw	7.000s	13.117us	20	20	100.00
		pattgen_csr_aliasing	6.000s	125.966us	5	5	100.00
		pattgen_same_csr_outstanding	7.000s	27.894us	20	20	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	6.000s	57.797us	5	5	100.00
		pattgen_csr_rw	7.000s	13.117us	20	20	100.00
		pattgen_csr_aliasing	6.000s	125.966us	5	5	100.00
		pattgen_same_csr_outstanding	7.000s	27.894us	20	20	100.00
V2		TOTAL			340	340	100.00
V2S	tl_intg_err	pattgen_tl_intg_err	9.000s	154.528us	20	20	100.00
		pattgen_sec_cm	20.000s	40.187us	5	5	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	9.000s	154.528us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	2.000m	8.984ms	3	50	6.00
V3		TOTAL			3	50	6.00
	Unmapped tests	pattgen_inactive_level	1.767m	10.004ms	48	50	96.00
		TOTAL			521	570	91.40

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.96	100.00	100.00	100.00	99.25	96.61	--	100.00	90.43

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:891) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 45 failures:

Test pattgen_stress_all_with_rand_reset has 45 failures.

1.pattgen_stress_all_with_rand_reset.38190871063584913862723218162422386327720128700750126483656756860044355589688
Line 226, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/1.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 13106940871 ps: (cip_base_vseq.sv:891) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 13106976720 ps: (cip_base_vseq.sv:795) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 13106976720 ps: (cip_base_vseq.sv:798) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Issuing reset for run 4/5
  UVM_INFO @ 13107212016 ps: (cip_base_vseq.sv:819) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

2.pattgen_stress_all_with_rand_reset.113279052239750890671725184998784733130090613869935759089100316682138216395478
Line 131, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/2.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 148000998 ps: (cip_base_vseq.sv:891) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 148001246 ps: (cip_base_vseq.sv:795) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 148001246 ps: (cip_base_vseq.sv:798) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Issuing reset for run 1/10
  UVM_INFO @ 148091246 ps: (cip_base_vseq.sv:819) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

... and 43 more failures.

UVM_ERROR (pattgen_scoreboard.sv:207) scoreboard [scoreboard] has 2 failures:
- Test pattgen_stress_all_with_rand_reset has 2 failures.
  - 0.pattgen_stress_all_with_rand_reset.97352850949580946752082638373055904935619426687018604252801163338817241966067
    Line 188, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2069265049 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 0 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```
  - 6.pattgen_stress_all_with_rand_reset.20681287785797262272583530658088019680408099499516670223608946900945717501721
    Line 204, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/6.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1664006915 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 1 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```
UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 3.pattgen_inactive_level.92008221714931067492197196125876089139110770189793143938394960218269105215423
    Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/3.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10003583105 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xdd5ac210, Comparison=CompareOpEq, exp_data=0x0, call_count=3)
  UVM_INFO @ 10003583105 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=7) has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 25.pattgen_inactive_level.32050441785058742228708769133029433790490174075906320145357121019403996510796
    Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/25.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10004845410 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x3e9f0690, Comparison=CompareOpEq, exp_data=0x0, call_count=7)
  UVM_INFO @ 10004845410 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```