PWM Simulation Results

Saturday February 08 2025 23:09:58 UTC

GitHub Revision: c12958f63b

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pwm_smoke	22.000s	1.025ms	10	10	100.00
V1	csr_hw_reset	pwm_csr_hw_reset	6.000s	45.782us	5	5	100.00
V1	csr_rw	pwm_csr_rw	6.000s	18.659us	20	20	100.00
V1	csr_bit_bash	pwm_csr_bit_bash	9.000s	717.782us	5	5	100.00
V1	csr_aliasing	pwm_csr_aliasing	6.000s	36.243us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pwm_csr_mem_rw_with_rand_reset	6.000s	273.730us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pwm_csr_rw	6.000s	18.659us	20	20	100.00
		pwm_csr_aliasing	6.000s	36.243us	5	5	100.00
V1		TOTAL			65	65	100.00
V2	dutycycle	pwm_rand_output	46.000s	10.945ms	25	25	100.00
V2	pulse	pwm_rand_output	46.000s	10.945ms	25	25	100.00
V2	blink	pwm_rand_output	46.000s	10.945ms	25	25	100.00
V2	heartbeat	pwm_rand_output	46.000s	10.945ms	25	25	100.00
V2	resolution	pwm_rand_output	46.000s	10.945ms	25	25	100.00
V2	multi_channel	pwm_rand_output	46.000s	10.945ms	25	25	100.00
V2	polarity	pwm_rand_output	46.000s	10.945ms	25	25	100.00
V2	phase	pwm_rand_output	46.000s	10.945ms	25	25	100.00
		pwm_phase	45.000s	87.500ms	25	25	100.00
V2	lowpower	pwm_rand_output	46.000s	10.945ms	25	25	100.00
V2	perf	pwm_perf	40.000s	38.893ms	10	10	100.00
V2	regwen	pwm_regwen	2.100m	75.025ms	1	1	100.00
V2	stress_all	pwm_stress_all	1.867m	34.581ms	4	25	16.00
V2	alert_test	pwm_alert_test	6.000s	14.137us	50	50	100.00
V2	tl_d_oob_addr_access	pwm_tl_errors	7.000s	40.032us	20	20	100.00
V2	tl_d_illegal_access	pwm_tl_errors	7.000s	40.032us	20	20	100.00
V2	tl_d_outstanding_access	pwm_csr_hw_reset	6.000s	45.782us	5	5	100.00
		pwm_csr_rw	6.000s	18.659us	20	20	100.00
		pwm_csr_aliasing	6.000s	36.243us	5	5	100.00
		pwm_same_csr_outstanding	6.000s	36.266us	20	20	100.00
V2	tl_d_partial_access	pwm_csr_hw_reset	6.000s	45.782us	5	5	100.00
		pwm_csr_rw	6.000s	18.659us	20	20	100.00
		pwm_csr_aliasing	6.000s	36.243us	5	5	100.00
		pwm_same_csr_outstanding	6.000s	36.266us	20	20	100.00
V2		TOTAL			155	176	88.07
V2S	tl_intg_err	pwm_tl_intg_err	10.000s	444.704us	20	20	100.00
		pwm_sec_cm	6.000s	40.857us	5	5	100.00
V2S	sec_cm_bus_integrity	pwm_tl_intg_err	10.000s	444.704us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	heartbeat_wrap	pwm_heartbeat_wrap	40.000s	10.611ms	10	10	100.00
V3		TOTAL			10	10	100.00
		TOTAL			255	276	92.39

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
99.02	99.32	98.85	99.47	97.95	96.72	--	100.00	99.34

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:452) [pwm_common_vseq] Check failed (intr_csrs.size() > *) Called intr_test vseq without any interrupt register. has 21 failures:
  • Test pwm_stress_all has 21 failures.

    • 2.pwm_stress_all.102701381647271887854920923050307920626495386818272888099486384730831044569908
      Line 87, in log /nightly/runs/scratch/master/pwm-sim-xcelium/2.pwm_stress_all/latest/run.log

        UVM_ERROR @ 91697610139 ps: (cip_base_vseq.sv:452) [uvm_test_top.env.virtual_sequencer.pwm_common_vseq] Check failed (intr_csrs.size() > 0) Called intr_test vseq without any interrupt register.
        UVM_INFO @ 91697610139 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 4.pwm_stress_all.60448793192002464103505396288059213307686127427420399091156672383014811332301
      Line 84, in log /nightly/runs/scratch/master/pwm-sim-xcelium/4.pwm_stress_all/latest/run.log

        UVM_ERROR @ 510644660 ps: (cip_base_vseq.sv:452) [uvm_test_top.env.virtual_sequencer.pwm_common_vseq] Check failed (intr_csrs.size() > 0) Called intr_test vseq without any interrupt register.
        UVM_INFO @ 510644660 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 19 more failures.