RV_TIMER Simulation Results

Saturday February 08 2025 23:09:58 UTC

GitHub Revision: c12958f63b

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	36.614m	2.337s	200	200	100.00
V1	csr_hw_reset	rv_timer_csr_hw_reset	1.440s	53.776us	5	5	100.00
V1	csr_rw	rv_timer_csr_rw	1.540s	17.048us	20	20	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	3.330s	417.405us	5	5	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	1.520s	26.720us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	2.210s	40.743us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	1.540s	17.048us	20	20	100.00
		rv_timer_csr_aliasing	1.520s	26.720us	5	5	100.00
V1		TOTAL			255	255	100.00
V2	random_reset	rv_timer_random_reset	17.086m	85.814ms	49	50	98.00
V2	disabled	rv_timer_disabled	3.353m	689.377ms	48	50	96.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	19.769m	2.138s	50	50	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	19.769m	2.138s	50	50	100.00
V2	stress	rv_timer_stress_all	49.109m	2.460s	50	50	100.00
V2	intr_test	rv_timer_intr_test	1.580s	62.045us	50	50	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	3.260s	3.599ms	20	20	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	3.260s	3.599ms	20	20	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	1.440s	53.776us	5	5	100.00
		rv_timer_csr_rw	1.540s	17.048us	20	20	100.00
		rv_timer_csr_aliasing	1.520s	26.720us	5	5	100.00
		rv_timer_same_csr_outstanding	1.660s	60.244us	20	20	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	1.440s	53.776us	5	5	100.00
		rv_timer_csr_rw	1.540s	17.048us	20	20	100.00
		rv_timer_csr_aliasing	1.520s	26.720us	5	5	100.00
		rv_timer_same_csr_outstanding	1.660s	60.244us	20	20	100.00
V2		TOTAL			287	290	98.97
V2S	tl_intg_err	rv_timer_sec_cm	2.930s	389.949us	5	5	100.00
		rv_timer_tl_intg_err	4.800s	254.496us	20	20	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	4.800s	254.496us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	58.950s	14.418ms	10	50	20.00
V3		TOTAL			10	50	20.00
		TOTAL			577	620	93.06

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.66	99.29	99.36	100.00	--	100.00	100.00	99.32

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:890) [rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 40 failures:
  • Test rv_timer_stress_all_with_rand_reset has 40 failures.

    • 0.rv_timer_stress_all_with_rand_reset.32458649592537313594987771520712012710592505401764596799566469853480145414695
      Line 162, in log /nightly/runs/scratch/master/rv_timer-sim-vcs/0.rv_timer_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1120893930 ps: (cip_base_vseq.sv:890) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 1120893930 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.rv_timer_stress_all_with_rand_reset.4389383549394827048624491855181672002837212739147091261949799544263800361131
      Line 114, in log /nightly/runs/scratch/master/rv_timer-sim-vcs/1.rv_timer_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1538148131 ps: (cip_base_vseq.sv:890) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 1538148131 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 38 more failures.

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 3 failures:

  • Test rv_timer_disabled has 2 failures.

    • 10.rv_timer_disabled.114189067673933703849675913670788613863478452522136122824301252404921290202815
      Line 76, in log /nightly/runs/scratch/master/rv_timer-sim-vcs/10.rv_timer_disabled/latest/run.log

        UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 29.rv_timer_disabled.81086523659124637795780084417487403315304021877099222684248636000199192604397
      Line 77, in log /nightly/runs/scratch/master/rv_timer-sim-vcs/29.rv_timer_disabled/latest/run.log

        UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test rv_timer_random_reset has 1 failures.

    • 33.rv_timer_random_reset.69264512758454253034020336066224216317167365907305788460182713483686966030024
      Line 73, in log /nightly/runs/scratch/master/rv_timer-sim-vcs/33.rv_timer_random_reset/latest/run.log

        UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---