SPI_HOST Simulation Results

Saturday February 08 2025 23:09:58 UTC

GitHub Revision: c12958f63b

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	4.550m	75.878ms	50	50	100.00
V1	csr_hw_reset	spi_host_csr_hw_reset	6.000s	20.983us	5	5	100.00
V1	csr_rw	spi_host_csr_rw	6.000s	35.608us	20	20	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	7.000s	892.371us	5	5	100.00
V1	csr_aliasing	spi_host_csr_aliasing	6.000s	41.017us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	6.000s	42.081us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	6.000s	35.608us	20	20	100.00
		spi_host_csr_aliasing	6.000s	41.017us	5	5	100.00
V1	mem_walk	spi_host_mem_walk	6.000s	14.972us	5	5	100.00
V1	mem_partial_access	spi_host_mem_partial_access	6.000s	25.550us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	performance	spi_host_performance	18.000s	220.241us	50	50	100.00
V2	error_event_intr	spi_host_overflow_underflow	2.400m	67.928ms	50	50	100.00
		spi_host_error_cmd	15.000s	46.868us	50	50	100.00
		spi_host_event	10.167m	96.287ms	50	50	100.00
V2	clock_rate	spi_host_speed	31.000s	505.933us	50	50	100.00
V2	speed	spi_host_speed	31.000s	505.933us	50	50	100.00
V2	chip_select_timing	spi_host_speed	31.000s	505.933us	50	50	100.00
V2	sw_reset	spi_host_sw_reset	4.417m	13.037ms	50	50	100.00
V2	passthrough_mode	spi_host_passthrough_mode	11.000s	980.190us	50	50	100.00
V2	cpol_cpha	spi_host_speed	31.000s	505.933us	50	50	100.00
V2	full_cycle	spi_host_speed	31.000s	505.933us	50	50	100.00
V2	duplex	spi_host_smoke	4.550m	75.878ms	50	50	100.00
V2	tx_rx_only	spi_host_smoke	4.550m	75.878ms	50	50	100.00
V2	stress_all	spi_host_stress_all	1.633m	37.359ms	50	50	100.00
V2	spien	spi_host_spien	4.667m	170.216ms	49	50	98.00
V2	stall	spi_host_status_stall	4.700m	123.267ms	47	50	94.00
V2	Idlecsbactive	spi_host_idlecsbactive	40.000s	6.072ms	49	50	98.00
V2	data_fifo_status	spi_host_overflow_underflow	2.400m	67.928ms	50	50	100.00
V2	alert_test	spi_host_alert_test	7.000s	30.217us	50	50	100.00
V2	intr_test	spi_host_intr_test	6.000s	20.092us	50	50	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	7.000s	114.313us	20	20	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	7.000s	114.313us	20	20	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	6.000s	20.983us	5	5	100.00
		spi_host_csr_rw	6.000s	35.608us	20	20	100.00
		spi_host_csr_aliasing	6.000s	41.017us	5	5	100.00
		spi_host_same_csr_outstanding	6.000s	25.855us	20	20	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	6.000s	20.983us	5	5	100.00
		spi_host_csr_rw	6.000s	35.608us	20	20	100.00
		spi_host_csr_aliasing	6.000s	41.017us	5	5	100.00
		spi_host_same_csr_outstanding	6.000s	25.855us	20	20	100.00
V2		TOTAL			685	690	99.28
V2S	tl_intg_err	spi_host_tl_intg_err	9.000s	543.678us	20	20	100.00
		spi_host_sec_cm	6.000s	64.986us	5	5	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	9.000s	543.678us	20	20	100.00
V2S		TOTAL			25	25	100.00
	Unmapped tests	spi_host_upper_range_clkdiv	36.650m	200.000ms	2	10	20.00
		TOTAL			827	840	98.45

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
96.78	96.72	93.17	98.70	95.71	94.46	100.00	97.44	91.29

Failure Buckets

• UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=2) has 3 failures:

  • Test spi_host_upper_range_clkdiv has 3 failures.

    • 1.spi_host_upper_range_clkdiv.39702269040003188273008603284802995255583939950911194599153656097014503015986
      Line 150, in log /nightly/runs/scratch/master/spi_host-sim-xcelium/1.spi_host_upper_range_clkdiv/latest/run.log

        UVM_FATAL @ 100005387232 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xa39c3954, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
        UVM_INFO @ 100005387232 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 5.spi_host_upper_range_clkdiv.15537662618926970276847400954679014068656764117270008400739990765737314061815
      Line 127, in log /nightly/runs/scratch/master/spi_host-sim-xcelium/5.spi_host_upper_range_clkdiv/latest/run.log

        UVM_FATAL @ 100003675566 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x97eea6d4, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
        UVM_INFO @ 100003675566 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 1 more failures.

• UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=8) has 1 failures:

  • Test spi_host_upper_range_clkdiv has 1 failures.

    • 0.spi_host_upper_range_clkdiv.79589317053671529094419923397817482646238490188271972409535216740919645393780
      Line 123, in log /nightly/runs/scratch/master/spi_host-sim-xcelium/0.spi_host_upper_range_clkdiv/latest/run.log

        UVM_FATAL @ 100003412985 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xda765694, Comparison=CompareOpEq, exp_data=0x0, call_count=8)
        UVM_INFO @ 100003412985 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=16) has 1 failures:

  • Test spi_host_upper_range_clkdiv has 1 failures.

    • 2.spi_host_upper_range_clkdiv.86458444146025360780348072942546153989494103171684064954235674297825574222246
      Line 163, in log /nightly/runs/scratch/master/spi_host-sim-xcelium/2.spi_host_upper_range_clkdiv/latest/run.log

        UVM_FATAL @ 144565995145 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xbc488914, Comparison=CompareOpEq, exp_data=0x0, call_count=16)
        UVM_INFO @ 144565995145 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=9) has 1 failures:

  • Test spi_host_upper_range_clkdiv has 1 failures.

    • 4.spi_host_upper_range_clkdiv.81671129807106800104079900129984828732143608728175029373117662678983219568845
      Line 129, in log /nightly/runs/scratch/master/spi_host-sim-xcelium/4.spi_host_upper_range_clkdiv/latest/run.log

        UVM_FATAL @ 100002579966 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xf24b0714, Comparison=CompareOpEq, exp_data=0x0, call_count=9)
        UVM_INFO @ 100002579966 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Job timed out after * minutes has 1 failures:

  • Test spi_host_upper_range_clkdiv has 1 failures.

    • 6.spi_host_upper_range_clkdiv.35363092889704223698984014121036846880016920762824768277930792985979768972855
      Log /nightly/runs/scratch/master/spi_host-sim-xcelium/6.spi_host_upper_range_clkdiv/latest/run.log

        Job timed out after 60 minutes
      

• UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=12) has 1 failures:

  • Test spi_host_idlecsbactive has 1 failures.

    • 6.spi_host_idlecsbactive.85120059572593653780958066707235231254548294492660264819065130235570203475786
      Line 166, in log /nightly/runs/scratch/master/spi_host-sim-xcelium/6.spi_host_idlecsbactive/latest/run.log

        UVM_FATAL @ 15083147642 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xf7497854, Comparison=CompareOpEq, exp_data=0x0, call_count=12)
        UVM_INFO @ 15083147642 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:

  • Test spi_host_upper_range_clkdiv has 1 failures.

    • 7.spi_host_upper_range_clkdiv.13175780448714863832524953746986196345612492777163537033227612618778536719853
      Line 195, in log /nightly/runs/scratch/master/spi_host-sim-xcelium/7.spi_host_upper_range_clkdiv/latest/run.log

        UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=95) has 1 failures:

  • Test spi_host_status_stall has 1 failures.

    • 15.spi_host_status_stall.96322636906666032894901428389987068448906737802482723274337265544470833358131
      Line 775, in log /nightly/runs/scratch/master/spi_host-sim-xcelium/15.spi_host_status_stall/latest/run.log

        UVM_FATAL @ 12244590800 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x47898c14, Comparison=CompareOpEq, exp_data=0x1, call_count=95)
        UVM_INFO @ 12244590800 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=86) has 1 failures:

  • Test spi_host_status_stall has 1 failures.

    • 18.spi_host_status_stall.70124462393706877038555774395972399864981075259307538044199022908046764445581
      Line 737, in log /nightly/runs/scratch/master/spi_host-sim-xcelium/18.spi_host_status_stall/latest/run.log

        UVM_FATAL @ 10043340672 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x65636814, Comparison=CompareOpEq, exp_data=0x1, call_count=86)
        UVM_INFO @ 10043340672 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=77) has 1 failures:

  • Test spi_host_status_stall has 1 failures.

    • 24.spi_host_status_stall.98220849331448064557414707437648680019713231211531237409067885599497734685755
      Line 683, in log /nightly/runs/scratch/master/spi_host-sim-xcelium/24.spi_host_status_stall/latest/run.log

        UVM_FATAL @ 10195818742 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x2874da14, Comparison=CompareOpEq, exp_data=0x1, call_count=77)
        UVM_INFO @ 10195818742 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxqd (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=54) has 1 failures:

  • Test spi_host_spien has 1 failures.

    • 40.spi_host_spien.64968453333776010994781987234359656793854135573919185734158942182374623801165
      Line 412, in log /nightly/runs/scratch/master/spi_host-sim-xcelium/40.spi_host_spien/latest/run.log

        UVM_FATAL @ 10021063622 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxqd (addr=0x7250814, Comparison=CompareOpEq, exp_data=0x0, call_count=54)
        UVM_INFO @ 10021063622 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---