UART Simulation Results

Saturday February 08 2025 23:09:58 UTC

GitHub Revision: c12958f63b

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	24.920s	5.822ms	50	50	100.00
V1	csr_hw_reset	uart_csr_hw_reset	2.060s	21.497us	5	5	100.00
V1	csr_rw	uart_csr_rw	2.040s	19.060us	20	20	100.00
V1	csr_bit_bash	uart_csr_bit_bash	3.170s	176.753us	5	5	100.00
V1	csr_aliasing	uart_csr_aliasing	2.150s	27.437us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	2.190s	108.861us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	2.040s	19.060us	20	20	100.00
		uart_csr_aliasing	2.150s	27.437us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	base_random_seq	uart_tx_rx	4.493m	157.807ms	50	50	100.00
V2	parity	uart_smoke	24.920s	5.822ms	50	50	100.00
		uart_tx_rx	4.493m	157.807ms	50	50	100.00
V2	parity_error	uart_intr	4.728m	288.769ms	50	50	100.00
		uart_rx_parity_err	6.037m	124.067ms	50	50	100.00
V2	watermark	uart_tx_rx	4.493m	157.807ms	50	50	100.00
		uart_intr	4.728m	288.769ms	50	50	100.00
V2	fifo_full	uart_fifo_full	2.743m	108.996ms	50	50	100.00
V2	fifo_overflow	uart_fifo_overflow	5.431m	186.765ms	49	50	98.00
V2	fifo_reset	uart_fifo_reset	9.491m	90.903ms	300	300	100.00
V2	rx_frame_err	uart_intr	4.728m	288.769ms	50	50	100.00
V2	rx_break_err	uart_intr	4.728m	288.769ms	50	50	100.00
V2	rx_timeout	uart_intr	4.728m	288.769ms	50	50	100.00
V2	perf	uart_perf	12.860m	24.409ms	50	50	100.00
V2	sys_loopback	uart_loopback	18.300s	14.600ms	50	50	100.00
V2	line_loopback	uart_loopback	18.300s	14.600ms	50	50	100.00
V2	rx_noise_filter	uart_noise_filter	2.742m	134.452ms	50	50	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	1.129m	78.875ms	50	50	100.00
V2	tx_overide	uart_tx_ovrd	16.890s	6.513ms	50	50	100.00
V2	rx_oversample	uart_rx_oversample	35.660s	6.505ms	50	50	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	18.979m	174.337ms	50	50	100.00
V2	stress_all	uart_stress_all	17.193m	235.676ms	49	50	98.00
V2	alert_test	uart_alert_test	2.610s	14.561us	50	50	100.00
V2	intr_test	uart_intr_test	2.010s	31.121us	50	50	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.940s	245.173us	20	20	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.940s	245.173us	20	20	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	2.060s	21.497us	5	5	100.00
		uart_csr_rw	2.040s	19.060us	20	20	100.00
		uart_csr_aliasing	2.150s	27.437us	5	5	100.00
		uart_same_csr_outstanding	2.130s	56.508us	20	20	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	2.060s	21.497us	5	5	100.00
		uart_csr_rw	2.040s	19.060us	20	20	100.00
		uart_csr_aliasing	2.150s	27.437us	5	5	100.00
		uart_same_csr_outstanding	2.130s	56.508us	20	20	100.00
V2		TOTAL			1088	1090	99.82
V2S	tl_intg_err	uart_sec_cm	3.290s	64.783us	5	5	100.00
		uart_tl_intg_err	5.110s	1.609ms	20	20	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	5.110s	1.609ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	1.351m	16.736ms	98	100	98.00
V3		TOTAL			98	100	98.00
		TOTAL			1316	1320	99.70

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.83	98.97	98.25	98.02	--	98.14	100.00	99.59

Failure Buckets

• UVM_ERROR (uart_scoreboard.sv:447) [scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (* [*] vs * [*]) Interrupt_pin: TxEmpty has 2 failures:

  • Test uart_stress_all has 1 failures.

    • 30.uart_stress_all.58383152511968481171109671265228169057479452873859712674990133510149571744156
      Line 82, in log /nightly/runs/scratch/master/uart-sim-vcs/30.uart_stress_all/latest/run.log

        UVM_ERROR @ 83967919702 ps: (uart_scoreboard.sv:447) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: TxEmpty
        UVM_INFO @ 84468389703 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_perf_vseq] finished run 1/10
        UVM_INFO @ 84990799702 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_perf_vseq] finished run 2/10
        UVM_INFO @ 85861159702 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_perf_vseq] finished run 3/10
        UVM_INFO @ 85900639702 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_perf_vseq] finished run 4/10
      

  • Test uart_fifo_overflow has 1 failures.

    • 40.uart_fifo_overflow.78600007929019715955199453465423116296845014853047923387773994736193561301385
      Line 69, in log /nightly/runs/scratch/master/uart-sim-vcs/40.uart_fifo_overflow/latest/run.log

        UVM_ERROR @   1207248 ps: (uart_scoreboard.sv:447) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: TxEmpty
        UVM_INFO @ 3219769748 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_overflow_vseq] finished run 1/10
        UVM_INFO @ 3379254123 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_overflow_vseq] finished run 2/10
        UVM_INFO @ 53648863498 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_overflow_vseq] finished run 3/10
        UVM_INFO @ 56218629123 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_overflow_vseq] finished run 4/10
      

• UVM_ERROR (cip_base_vseq.sv:794) [uart_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:

  • Test uart_stress_all_with_rand_reset has 1 failures.

    • 7.uart_stress_all_with_rand_reset.9433181640300577638775277827119546414651814824575621812826393183927034355209
      Line 154, in log /nightly/runs/scratch/master/uart-sim-vcs/7.uart_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 3338629148 ps: (cip_base_vseq.sv:794) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 3338629148 ps: (cip_base_vseq.sv:798) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
        Issuing reset for run 7/10
        UVM_INFO @ 3338629148 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_long_xfer_wo_dly_vseq] finished run 1/6
        UVM_INFO @ 3338749148 ps: (cip_base_vseq.sv:818) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
      

• UVM_ERROR (uart_scoreboard.sv:447) [scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (* [*] vs * [*]) Interrupt_pin: TxWatermark has 1 failures:

  • Test uart_stress_all_with_rand_reset has 1 failures.

    • 91.uart_stress_all_with_rand_reset.17447631122775066097233238489823520943146581670241171356050900841604205718030
      Line 169, in log /nightly/runs/scratch/master/uart-sim-vcs/91.uart_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 11700580747 ps: (uart_scoreboard.sv:447) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: TxWatermark
        UVM_INFO @ 12132340747 ps: (cip_base_vseq__tl_errors.svh:290) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 2/798
        UVM_INFO @ 12346980747 ps: (cip_base_vseq__tl_errors.svh:290) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 3/798
        UVM_INFO @ 12453020747 ps: (cip_base_vseq__tl_errors.svh:290) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 4/798
        UVM_INFO @ 12628820747 ps: (cip_base_vseq__tl_errors.svh:290) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 5/798