ADC_CTRL Simulation Results

Sunday March 23 2025 00:10:17 UTC

GitHub Revision: `27fc640f8d`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	23.180s	6.074ms	50	50	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	6.400s	1.274ms	5	5	100.00
V1	csr_rw	adc_ctrl_csr_rw	4.170s	515.981us	20	20	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	2.502m	50.804ms	5	5	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	6.130s	1.154ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	4.680s	596.833us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	4.170s	515.981us	20	20	100.00
		adc_ctrl_csr_aliasing	6.130s	1.154ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	filters_polled	adc_ctrl_filters_polled	21.889m	493.993ms	50	50	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	22.899m	484.533ms	50	50	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	20.788m	497.126ms	50	50	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	21.313m	480.501ms	50	50	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	24.729m	569.009ms	50	50	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	23.877m	599.552ms	50	50	100.00
V2	filters_both	adc_ctrl_filters_both	24.345m	524.945ms	46	50	92.00
V2	clock_gating	adc_ctrl_clock_gating	21.496m	2.000s	33	50	66.00
V2	poweron_counter	adc_ctrl_poweron_counter	19.690s	5.252ms	50	50	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	2.465m	43.256ms	50	50	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	6.531m	133.919ms	50	50	100.00
V2	stress_all	adc_ctrl_stress_all	56.154m	10.000s	45	50	90.00
V2	alert_test	adc_ctrl_alert_test	3.960s	523.610us	50	50	100.00
V2	intr_test	adc_ctrl_intr_test	3.960s	503.701us	50	50	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	5.470s	544.193us	20	20	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	5.470s	544.193us	20	20	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	6.400s	1.274ms	5	5	100.00
		adc_ctrl_csr_rw	4.170s	515.981us	20	20	100.00
		adc_ctrl_csr_aliasing	6.130s	1.154ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	23.020s	4.301ms	20	20	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	6.400s	1.274ms	5	5	100.00
		adc_ctrl_csr_rw	4.170s	515.981us	20	20	100.00
		adc_ctrl_csr_aliasing	6.130s	1.154ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	23.020s	4.301ms	20	20	100.00
V2		TOTAL			714	740	96.49
V2S	tl_intg_err	adc_ctrl_sec_cm	16.210s	4.263ms	5	5	100.00
		adc_ctrl_tl_intg_err	23.070s	16.114ms	19	20	95.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	23.070s	16.114ms	19	20	95.00
V2S		TOTAL			24	25	96.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	29.474m	10.000s	48	50	96.00
V3		TOTAL			48	50	96.00
		TOTAL			891	920	96.85

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.56	99.11	96.45	100.00	100.00	99.01	98.04	90.33

Failure Buckets

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 15 failures:

Test adc_ctrl_clock_gating has 10 failures.

0.adc_ctrl_clock_gating.39984896108347359353865931584739844770749816373332834372893785678277479959276
Line 146, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/0.adc_ctrl_clock_gating/latest/run.log

  UVM_FATAL @ 2000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 2000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 2000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.adc_ctrl_clock_gating.27152858425443212974526616492864646140260243770598750597460527894217165701950
Line 146, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/1.adc_ctrl_clock_gating/latest/run.log

  UVM_FATAL @ 2000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 2000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 2000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 8 more failures.

Test adc_ctrl_filters_both has 2 failures.

5.adc_ctrl_filters_both.75382823394968385244945076914588641739081866954123651764085579412125913625426
Line 184, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/5.adc_ctrl_filters_both/latest/run.log

  UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

22.adc_ctrl_filters_both.91139214497604032038226466829124887607654527407605923505704306686761096315911
Line 178, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/22.adc_ctrl_filters_both/latest/run.log

  UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test adc_ctrl_stress_all_with_rand_reset has 1 failures.
- 15.adc_ctrl_stress_all_with_rand_reset.13143014887667058554303407851597294329581531480739425631178588086117728167979
  Line 229, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/15.adc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Test adc_ctrl_stress_all has 2 failures.

17.adc_ctrl_stress_all.11871094044022084264371672986593134314227447556062093331338850838604670026934
Line 166, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/17.adc_ctrl_stress_all/latest/run.log

  UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

25.adc_ctrl_stress_all.19179189444493048439484184980776886703510649235894159421828012044183924930987
Line 147, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/25.adc_ctrl_stress_all/latest/run.log

  UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (cip_base_scoreboard.sv:249) scoreboard [scoreboard] alert fatal_fault has unexpected timeout error has 7 failures:

Test adc_ctrl_clock_gating has 5 failures.

3.adc_ctrl_clock_gating.80181298605149828487468202382086485404981677177705636404003296078988250796694
Line 146, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/3.adc_ctrl_clock_gating/latest/run.log

  UVM_ERROR @ 2282142155 ps: (cip_base_scoreboard.sv:249) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
  UVM_INFO @ 2282142155 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

12.adc_ctrl_clock_gating.27677098918177683798456626531195091437171900645688134042372815524733880634049
Line 163, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/12.adc_ctrl_clock_gating/latest/run.log

  UVM_ERROR @ 180386365414 ps: (cip_base_scoreboard.sv:249) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
  UVM_INFO @ 180386365414 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

Test adc_ctrl_stress_all_with_rand_reset has 1 failures.
- 32.adc_ctrl_stress_all_with_rand_reset.15497967296963301729008146128759338720188255572026383344876346058277773997984
  Line 180, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/32.adc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 10029977856 ps: (cip_base_scoreboard.sv:249) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
  UVM_INFO @ 10029977856 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Test adc_ctrl_stress_all has 1 failures.

43.adc_ctrl_stress_all.105209963550037883123482691164150492503703738174696427958978372975504814930690
Line 169, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/43.adc_ctrl_stress_all/latest/run.log

  UVM_ERROR @ 11971735974 ps: (cip_base_scoreboard.sv:249) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
  UVM_INFO @ 11971735974 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (adc_ctrl_scoreboard.sv:405) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: adc_ctrl_reg_block.intr_state has 6 failures:

Test adc_ctrl_filters_both has 2 failures.

14.adc_ctrl_filters_both.76781503512518852406464682034388294818053010200077315123749354193603745690828
Line 162, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/14.adc_ctrl_filters_both/latest/run.log

  UVM_ERROR @ 274494213398 ps: (adc_ctrl_scoreboard.sv:405) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
  UVM_INFO @ 274494213398 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

34.adc_ctrl_filters_both.54302811451474691274210327874494780736476791031400590279654229593565631641778
Line 178, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/34.adc_ctrl_filters_both/latest/run.log

  UVM_ERROR @ 418335245191 ps: (adc_ctrl_scoreboard.sv:405) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
  UVM_INFO @ 418335245191 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test adc_ctrl_stress_all has 2 failures.

40.adc_ctrl_stress_all.98096529047971935368278650657092629591117349661082996623660365779075328791777
Line 186, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/40.adc_ctrl_stress_all/latest/run.log

  UVM_ERROR @ 292391525410 ps: (adc_ctrl_scoreboard.sv:405) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
  UVM_INFO @ 292391525410 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

49.adc_ctrl_stress_all.76499531954565438277910884288765767269708634403311181091741649639732870811111
Line 160, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/49.adc_ctrl_stress_all/latest/run.log

  UVM_ERROR @ 78875285186 ps: (adc_ctrl_scoreboard.sv:405) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
  UVM_INFO @ 78875285186 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test adc_ctrl_clock_gating has 2 failures.

42.adc_ctrl_clock_gating.44525411797239399524088271327504087326532488193426666823268593809863635050359
Line 146, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/42.adc_ctrl_clock_gating/latest/run.log

  UVM_ERROR @ 82995680296 ps: (adc_ctrl_scoreboard.sv:405) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
  UVM_INFO @ 82995680296 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

46.adc_ctrl_clock_gating.21109081708373502763181085070392975393790817116183693770856183037336708827914
Line 146, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/46.adc_ctrl_clock_gating/latest/run.log

  UVM_ERROR @ 82742549323 ps: (adc_ctrl_scoreboard.sv:405) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
  UVM_INFO @ 82742549323 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (cip_base_vseq.sv:665) [adc_ctrl_common_vseq] timeout wait for alert handshake:fatal_fault has 1 failures:
- Test adc_ctrl_tl_intg_err has 1 failures.
  - 18.adc_ctrl_tl_intg_err.14448630415645366274700342915316412596058483262428944040895232133715032569603
    Line 261, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/18.adc_ctrl_tl_intg_err/latest/run.log
```
  UVM_FATAL @ 16113506407 ps: (cip_base_vseq.sv:665) [uvm_test_top.env.virtual_sequencer.adc_ctrl_common_vseq] timeout wait for alert handshake:fatal_fault
  UVM_INFO @ 16113506407 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```