AES/MASKED Simulation Results

Sunday March 23 2025 00:10:17 UTC

GitHub Revision: `27fc640f8d`

Branch: master

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	9.000s	77.878us	1	1	100.00
V1	smoke	aes_smoke	22.000s	1.751ms	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	5.000s	64.196us	5	5	100.00
V1	csr_rw	aes_csr_rw	5.000s	69.718us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	9.000s	1.701ms	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	6.000s	124.252us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	5.000s	128.844us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	5.000s	69.718us	20	20	100.00
		aes_csr_aliasing	6.000s	124.252us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	22.000s	1.751ms	50	50	100.00
		aes_config_error	24.000s	1.169ms	50	50	100.00
		aes_stress	15.000s	213.317us	50	50	100.00
V2	key_length	aes_smoke	22.000s	1.751ms	50	50	100.00
		aes_config_error	24.000s	1.169ms	50	50	100.00
		aes_stress	15.000s	213.317us	50	50	100.00
V2	back2back	aes_stress	15.000s	213.317us	50	50	100.00
		aes_b2b	26.000s	1.204ms	50	50	100.00
V2	backpressure	aes_stress	15.000s	213.317us	50	50	100.00
V2	multi_message	aes_smoke	22.000s	1.751ms	50	50	100.00
		aes_config_error	24.000s	1.169ms	50	50	100.00
		aes_stress	15.000s	213.317us	50	50	100.00
		aes_alert_reset	13.000s	777.243us	47	50	94.00
V2	failure_test	aes_man_cfg_err	7.000s	67.011us	50	50	100.00
		aes_config_error	24.000s	1.169ms	50	50	100.00
		aes_alert_reset	13.000s	777.243us	47	50	94.00
V2	trigger_clear_test	aes_clear	24.000s	2.134ms	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	13.000s	204.006us	1	1	100.00
V2	reset_recovery	aes_alert_reset	13.000s	777.243us	47	50	94.00
V2	stress	aes_stress	15.000s	213.317us	50	50	100.00
V2	sideload	aes_stress	15.000s	213.317us	50	50	100.00
		aes_sideload	22.000s	1.925ms	50	50	100.00
V2	deinitialization	aes_deinit	13.000s	794.495us	50	50	100.00
V2	stress_all	aes_stress_all	1.200m	5.218ms	8	10	80.00
V2	alert_test	aes_alert_test	10.000s	85.926us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	7.000s	1.190ms	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	7.000s	1.190ms	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	5.000s	64.196us	5	5	100.00
		aes_csr_rw	5.000s	69.718us	20	20	100.00
		aes_csr_aliasing	6.000s	124.252us	5	5	100.00
		aes_same_csr_outstanding	6.000s	149.295us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	5.000s	64.196us	5	5	100.00
		aes_csr_rw	5.000s	69.718us	20	20	100.00
		aes_csr_aliasing	6.000s	124.252us	5	5	100.00
		aes_same_csr_outstanding	6.000s	149.295us	20	20	100.00
V2		TOTAL			496	501	99.00
V2S	reseeding	aes_reseed	59.000s	2.325ms	50	50	100.00
V2S	fault_inject	aes_fi	24.000s	3.071ms	49	50	98.00
		aes_control_fi	55.000s	10.006ms	276	300	92.00
		aes_cipher_fi	1.000m	10.013ms	340	350	97.14
V2S	shadow_reg_update_error	aes_shadow_reg_errors	6.000s	87.412us	14	20	70.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	6.000s	87.412us	14	20	70.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	6.000s	87.412us	14	20	70.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	6.000s	87.412us	14	20	70.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	6.000s	300.220us	7	20	35.00
V2S	tl_intg_err	aes_sec_cm	14.000s	1.078ms	5	5	100.00
		aes_tl_intg_err	6.000s	314.057us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	6.000s	314.057us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	13.000s	777.243us	47	50	94.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	6.000s	87.412us	14	20	70.00
V2S	sec_cm_main_config_sparse	aes_smoke	22.000s	1.751ms	50	50	100.00
		aes_stress	15.000s	213.317us	50	50	100.00
		aes_alert_reset	13.000s	777.243us	47	50	94.00
		aes_core_fi	53.000s	10.007ms	68	70	97.14
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	6.000s	87.412us	14	20	70.00
V2S	sec_cm_aux_config_regwen	aes_readability	6.000s	65.772us	50	50	100.00
		aes_stress	15.000s	213.317us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	15.000s	213.317us	50	50	100.00
		aes_sideload	22.000s	1.925ms	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	6.000s	65.772us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	6.000s	65.772us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	6.000s	65.772us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	6.000s	65.772us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	6.000s	65.772us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	15.000s	213.317us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	15.000s	213.317us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	24.000s	3.071ms	49	50	98.00
V2S	sec_cm_main_fsm_redun	aes_fi	24.000s	3.071ms	49	50	98.00
		aes_control_fi	55.000s	10.006ms	276	300	92.00
		aes_cipher_fi	1.000m	10.013ms	340	350	97.14
		aes_ctr_fi	6.000s	53.567us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	24.000s	3.071ms	49	50	98.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	24.000s	3.071ms	49	50	98.00
		aes_control_fi	55.000s	10.006ms	276	300	92.00
		aes_cipher_fi	1.000m	10.013ms	340	350	97.14
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	1.000m	10.013ms	340	350	97.14
V2S	sec_cm_ctr_fsm_sparse	aes_fi	24.000s	3.071ms	49	50	98.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	24.000s	3.071ms	49	50	98.00
		aes_control_fi	55.000s	10.006ms	276	300	92.00
		aes_ctr_fi	6.000s	53.567us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	24.000s	3.071ms	49	50	98.00
		aes_control_fi	55.000s	10.006ms	276	300	92.00
		aes_cipher_fi	1.000m	10.013ms	340	350	97.14
		aes_ctr_fi	6.000s	53.567us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	13.000s	777.243us	47	50	94.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	24.000s	3.071ms	49	50	98.00
		aes_control_fi	55.000s	10.006ms	276	300	92.00
		aes_cipher_fi	1.000m	10.013ms	340	350	97.14
		aes_ctr_fi	6.000s	53.567us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	24.000s	3.071ms	49	50	98.00
		aes_control_fi	55.000s	10.006ms	276	300	92.00
		aes_cipher_fi	1.000m	10.013ms	340	350	97.14
		aes_ctr_fi	6.000s	53.567us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	24.000s	3.071ms	49	50	98.00
		aes_control_fi	55.000s	10.006ms	276	300	92.00
		aes_ctr_fi	6.000s	53.567us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	24.000s	3.071ms	49	50	98.00
		aes_control_fi	55.000s	10.006ms	276	300	92.00
		aes_cipher_fi	1.000m	10.013ms	340	350	97.14
V2S		TOTAL			929	985	94.31
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	38.000s	744.311us	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1531	1602	95.57

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.36	98.56	96.34	99.42	95.60	97.99	97.78	99.10	98.39

Failure Buckets

UVM_FATAL (alert_receiver_driver.sv:146) [driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q has 20 failures:

Test aes_shadow_reg_errors_with_csr_rw has 8 failures.

0.aes_shadow_reg_errors_with_csr_rw.6072904750912262394004301214808292955337756334051753195639762488179274113317
Line 103, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/0.aes_shadow_reg_errors_with_csr_rw/latest/run.log

  UVM_FATAL @  99503637 ps: (alert_receiver_driver.sv:146) [uvm_test_top.env.m_alert_agent_fatal_fault.driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q
  UVM_INFO @  99503637 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.aes_shadow_reg_errors_with_csr_rw.20203202012014894111936836245022453011044072258700821883194873638783692855508
Line 104, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/2.aes_shadow_reg_errors_with_csr_rw/latest/run.log

  UVM_FATAL @ 204435801 ps: (alert_receiver_driver.sv:146) [uvm_test_top.env.m_alert_agent_fatal_fault.driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q
  UVM_INFO @ 204435801 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 6 more failures.

Test aes_shadow_reg_errors has 6 failures.

2.aes_shadow_reg_errors.92161598372478085765269252486985224863518712366558034356860491455485386380429
Line 103, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/2.aes_shadow_reg_errors/latest/run.log

  UVM_FATAL @   6289966 ps: (alert_receiver_driver.sv:146) [uvm_test_top.env.m_alert_agent_fatal_fault.driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q
  UVM_INFO @   6289966 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

5.aes_shadow_reg_errors.3361367974981053429397692100387158675247184643808462266609554935486931842708
Line 104, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/5.aes_shadow_reg_errors/latest/run.log

  UVM_FATAL @  22648153 ps: (alert_receiver_driver.sv:146) [uvm_test_top.env.m_alert_agent_fatal_fault.driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q
  UVM_INFO @  22648153 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

Test aes_fi has 1 failures.

5.aes_fi.2136106272304249146838368737136151817724359156650431200546800788650024435331
Line 526, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/5.aes_fi/latest/run.log

  UVM_FATAL @   7225741 ps: (alert_receiver_driver.sv:146) [uvm_test_top.env.m_alert_agent_fatal_fault.driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q
  UVM_INFO @   7225741 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test aes_stress_all has 2 failures.

6.aes_stress_all.69294592089327643482418619201123244439102183607193930981576441204378424414761
Line 5351, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/6.aes_stress_all/latest/run.log

  UVM_FATAL @ 102250325 ps: (alert_receiver_driver.sv:146) [uvm_test_top.env.m_alert_agent_fatal_fault.driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q
  UVM_INFO @ 102250325 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

7.aes_stress_all.8714080792176609726203492370451645132951931795207972746889975140442763837205
Line 292177, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/7.aes_stress_all/latest/run.log

  UVM_FATAL @ 5218137997 ps: (alert_receiver_driver.sv:146) [uvm_test_top.env.m_alert_agent_fatal_fault.driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q
  UVM_INFO @ 5218137997 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test aes_stress_all_with_rand_reset has 1 failures.

8.aes_stress_all_with_rand_reset.90187038346734129270491344092850227609319674497698612754284262341209509046127
Line 248, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/8.aes_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @ 262938951 ps: (alert_receiver_driver.sv:146) [uvm_test_top.env.m_alert_agent_fatal_fault.driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q
  UVM_INFO @ 262938951 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more tests.

Job timed out after * minutes has 17 failures:
- Test aes_cipher_fi has 2 failures.
  - 5.aes_cipher_fi.10821885924169063012705006254312338754422197525420113685004823337199307340358
    Log /nightly/runs/scratch/master/aes_masked-sim-xcelium/5.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 144.aes_cipher_fi.115339917417105696730253129999206324890626139215378423831098519484476726602419
    Log /nightly/runs/scratch/master/aes_masked-sim-xcelium/144.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
- Test aes_control_fi has 15 failures.
  - 9.aes_control_fi.105413486131336260972521613593115804763657105147010225173492687986956675169097
    Log /nightly/runs/scratch/master/aes_masked-sim-xcelium/9.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 19.aes_control_fi.43160221189437668283309454131168816317073298308173217636678093772016960789320
    Log /nightly/runs/scratch/master/aes_masked-sim-xcelium/19.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 13 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 9 failures:
- Test aes_control_fi has 9 failures.
  - 18.aes_control_fi.36185173980716964969805063105092843095947374861668692704120254837502174944530
    Line 135, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/18.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10027429355 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10027429355 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 27.aes_control_fi.81208550116811211112240571690606364016770557223658290119235328247499553570974
    Line 138, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/27.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10008391591 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10008391591 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 7 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 8 failures:
- Test aes_cipher_fi has 8 failures.
  - 42.aes_cipher_fi.7216071912361571997051641003898970314902356091649237992121130757624866341203
    Line 139, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/42.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10026122515 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10026122515 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 72.aes_cipher_fi.16482440405886560152919761867763684385579204061120919589590103018990899704099
    Line 135, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/72.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10021020971 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10021020971 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 6 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 4 failures:

Test aes_stress_all_with_rand_reset has 4 failures.

1.aes_stress_all_with_rand_reset.19235595164531727694219043710848235667375231039552933984015269387796854094661
Line 1024, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2412084710 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 2412084710 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.aes_stress_all_with_rand_reset.60233650276718789970782227258385907739342903002858525194469974686439865031553
Line 640, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 392600744 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 392600744 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

UVM_ERROR (cip_base_vseq.sv:980) [aes_common_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == * (* [*] vs * [*]) fatal error fatal_fault does not trigger! has 4 failures:
- Test aes_shadow_reg_errors_with_csr_rw has 4 failures.
  - 1.aes_shadow_reg_errors_with_csr_rw.25637898057606288806217460806506083019426827853825861078360680020314961682887
    Line 103, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/1.aes_shadow_reg_errors_with_csr_rw/latest/run.log
```
  UVM_ERROR @ 300219879 ps: (cip_base_vseq.sv:980) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_fault does not trigger!
  UVM_INFO @ 300219879 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 4.aes_shadow_reg_errors_with_csr_rw.45919271678884033767306294344403965025041301440983773180372503612658525610573
    Line 103, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/4.aes_shadow_reg_errors_with_csr_rw/latest/run.log
```
  UVM_ERROR @  66819420 ps: (cip_base_vseq.sv:980) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_fault does not trigger!
  UVM_INFO @  66819420 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 2 more failures.
UVM_ERROR (cip_base_vseq.sv:891) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:
- Test aes_stress_all_with_rand_reset has 2 failures.
  - 0.aes_stress_all_with_rand_reset.82695717095365166070329968455916671013179847246961048240743123265476139869916
    Line 157, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 112348267 ps: (cip_base_vseq.sv:891) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 112348267 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 9.aes_stress_all_with_rand_reset.54422958697984191114158897004750977033880484274302144357804016124303131999545
    Line 168, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/9.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 851698820 ps: (cip_base_vseq.sv:891) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 851698820 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_base_vseq.sv:74) [aes_alert_reset_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 2 failures:
- Test aes_stress_all_with_rand_reset has 2 failures.
  - 3.aes_stress_all_with_rand_reset.67911656437208734614670865882143378489271851529945168693674891194246025095110
    Line 151, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/3.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 109651802 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 109651802 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 4.aes_stress_all_with_rand_reset.30153027449160228516004129567288378837054959084447001912589547890702584048830
    Line 335, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/4.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 1118389806 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 1118389806 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 2 failures:

Test aes_core_fi has 2 failures.

4.aes_core_fi.92066736413301269797522207767066560087716390603989935198806827410048251133387
Line 133, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/4.aes_core_fi/latest/run.log

  UVM_FATAL @ 10020311240 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10020311240 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

45.aes_core_fi.50891959493035445689508838690566661407587080766771648973948141659175181308307
Line 144, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/45.aes_core_fi/latest/run.log

  UVM_FATAL @ 10007011711 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10007011711 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (aes_base_vseq.sv:74) [aes_stress_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 7.aes_stress_all_with_rand_reset.47624401280600711100876264547189608522873233604894199658058523094514069571092
    Line 147, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/7.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @  31577349 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_stress_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @  31577349 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

xmsim: *E,ASRTST (/nightly/runs/scratch/master/aes_masked-sim-xcelium/cover_reg_top/src/lowrisc_ip_aes_*/rtl/aes_cipher_core.sv,876): Assertion AesSecCmKeyMaskingStateShare has failed (* cycles, starting * PS) has 1 failures:

Test aes_shadow_reg_errors_with_csr_rw has 1 failures.

8.aes_shadow_reg_errors_with_csr_rw.102002973030455478629554561914670114316636781933270321038938000673298852227072
Line 105, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/8.aes_shadow_reg_errors_with_csr_rw/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/aes_masked-sim-xcelium/cover_reg_top/src/lowrisc_ip_aes_1.0/rtl/aes_cipher_core.sv,876): (time 25312778 PS) Assertion tb.dut.u_aes_core.u_aes_cipher_core.gen_sec_cm_key_masking_svas.gen_sec_cm_key_masking_share_svas[1].AesSecCmKeyMaskingStateShare has failed (2 cycles, starting 25272778 PS)
  UVM_ERROR @  25312778 ps: (aes_cipher_core.sv:876) [ASSERT FAILED] AesSecCmKeyMaskingStateShare
  UVM_INFO @  25312778 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

xmsim: *E,ASRTST (/nightly/runs/scratch/master/aes_masked-sim-xcelium/default/src/lowrisc_ip_aes_*/rtl/aes_core.sv,993): Assertion AesSecCmDataRegLocalEscIv has failed (* cycles, starting * PS) has 1 failures:

Test aes_alert_reset has 1 failures.

40.aes_alert_reset.40474384484060212287379178857215768173701248736794072113946435241468906452636
Line 3074, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/40.aes_alert_reset/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/aes_masked-sim-xcelium/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,993): (time 10056052 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscIv has failed (2 cycles, starting 10044147 PS)
  UVM_ERROR @  10056052 ps: (aes_core.sv:993) [ASSERT FAILED] AesSecCmDataRegLocalEscIv
  UVM_INFO @  10056052 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---