AES/UNMASKED Simulation Results

Sunday March 23 2025 00:10:17 UTC

GitHub Revision: `27fc640f8d`

Branch: master

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	43.000s	145.376us	1	1	100.00
V1	smoke	aes_smoke	43.000s	73.744us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	5.000s	102.739us	5	5	100.00
V1	csr_rw	aes_csr_rw	5.000s	64.368us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	9.000s	828.353us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	6.000s	87.980us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	5.000s	163.014us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	5.000s	64.368us	20	20	100.00
		aes_csr_aliasing	6.000s	87.980us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	43.000s	73.744us	50	50	100.00
		aes_config_error	43.000s	310.387us	50	50	100.00
		aes_stress	44.000s	66.993us	50	50	100.00
V2	key_length	aes_smoke	43.000s	73.744us	50	50	100.00
		aes_config_error	43.000s	310.387us	50	50	100.00
		aes_stress	44.000s	66.993us	50	50	100.00
V2	back2back	aes_stress	44.000s	66.993us	50	50	100.00
		aes_b2b	44.000s	80.756us	50	50	100.00
V2	backpressure	aes_stress	44.000s	66.993us	50	50	100.00
V2	multi_message	aes_smoke	43.000s	73.744us	50	50	100.00
		aes_config_error	43.000s	310.387us	50	50	100.00
		aes_stress	44.000s	66.993us	50	50	100.00
		aes_alert_reset	43.000s	105.785us	48	50	96.00
V2	failure_test	aes_man_cfg_err	44.000s	429.594us	50	50	100.00
		aes_config_error	43.000s	310.387us	50	50	100.00
		aes_alert_reset	43.000s	105.785us	48	50	96.00
V2	trigger_clear_test	aes_clear	43.000s	84.037us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	44.000s	301.480us	1	1	100.00
V2	reset_recovery	aes_alert_reset	43.000s	105.785us	48	50	96.00
V2	stress	aes_stress	44.000s	66.993us	50	50	100.00
V2	sideload	aes_stress	44.000s	66.993us	50	50	100.00
		aes_sideload	43.000s	117.558us	50	50	100.00
V2	deinitialization	aes_deinit	44.000s	262.328us	50	50	100.00
V2	stress_all	aes_stress_all	43.000s	63.782us	8	10	80.00
V2	alert_test	aes_alert_test	43.000s	99.503us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	6.000s	211.457us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	6.000s	211.457us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	5.000s	102.739us	5	5	100.00
		aes_csr_rw	5.000s	64.368us	20	20	100.00
		aes_csr_aliasing	6.000s	87.980us	5	5	100.00
		aes_same_csr_outstanding	6.000s	102.158us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	5.000s	102.739us	5	5	100.00
		aes_csr_rw	5.000s	64.368us	20	20	100.00
		aes_csr_aliasing	6.000s	87.980us	5	5	100.00
		aes_same_csr_outstanding	6.000s	102.158us	20	20	100.00
V2		TOTAL			497	501	99.20
V2S	reseeding	aes_reseed	44.000s	201.570us	50	50	100.00
V2S	fault_inject	aes_fi	43.000s	214.684us	47	50	94.00
		aes_control_fi	43.000s	55.684us	287	300	95.67
		aes_cipher_fi	43.000s	52.508us	325	350	92.86
V2S	shadow_reg_update_error	aes_shadow_reg_errors	5.000s	110.153us	9	20	45.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	5.000s	110.153us	9	20	45.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	5.000s	110.153us	9	20	45.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	5.000s	110.153us	9	20	45.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	7.000s	331.839us	8	20	40.00
V2S	tl_intg_err	aes_sec_cm	44.000s	431.329us	5	5	100.00
		aes_tl_intg_err	7.000s	2.292ms	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	7.000s	2.292ms	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	43.000s	105.785us	48	50	96.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	5.000s	110.153us	9	20	45.00
V2S	sec_cm_main_config_sparse	aes_smoke	43.000s	73.744us	50	50	100.00
		aes_stress	44.000s	66.993us	50	50	100.00
		aes_alert_reset	43.000s	105.785us	48	50	96.00
		aes_core_fi	4.500m	10.013ms	65	70	92.86
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	5.000s	110.153us	9	20	45.00
V2S	sec_cm_aux_config_regwen	aes_readability	43.000s	55.918us	50	50	100.00
		aes_stress	44.000s	66.993us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	44.000s	66.993us	50	50	100.00
		aes_sideload	43.000s	117.558us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	43.000s	55.918us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	43.000s	55.918us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	43.000s	55.918us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	43.000s	55.918us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	43.000s	55.918us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	44.000s	66.993us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	44.000s	66.993us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	43.000s	214.684us	47	50	94.00
V2S	sec_cm_main_fsm_redun	aes_fi	43.000s	214.684us	47	50	94.00
		aes_control_fi	43.000s	55.684us	287	300	95.67
		aes_cipher_fi	43.000s	52.508us	325	350	92.86
		aes_ctr_fi	43.000s	82.393us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	43.000s	214.684us	47	50	94.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	43.000s	214.684us	47	50	94.00
		aes_control_fi	43.000s	55.684us	287	300	95.67
		aes_cipher_fi	43.000s	52.508us	325	350	92.86
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	43.000s	52.508us	325	350	92.86
V2S	sec_cm_ctr_fsm_sparse	aes_fi	43.000s	214.684us	47	50	94.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	43.000s	214.684us	47	50	94.00
		aes_control_fi	43.000s	55.684us	287	300	95.67
		aes_ctr_fi	43.000s	82.393us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	43.000s	214.684us	47	50	94.00
		aes_control_fi	43.000s	55.684us	287	300	95.67
		aes_cipher_fi	43.000s	52.508us	325	350	92.86
		aes_ctr_fi	43.000s	82.393us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	43.000s	105.785us	48	50	96.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	43.000s	214.684us	47	50	94.00
		aes_control_fi	43.000s	55.684us	287	300	95.67
		aes_cipher_fi	43.000s	52.508us	325	350	92.86
		aes_ctr_fi	43.000s	82.393us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	43.000s	214.684us	47	50	94.00
		aes_control_fi	43.000s	55.684us	287	300	95.67
		aes_cipher_fi	43.000s	52.508us	325	350	92.86
		aes_ctr_fi	43.000s	82.393us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	43.000s	214.684us	47	50	94.00
		aes_control_fi	43.000s	55.684us	287	300	95.67
		aes_ctr_fi	43.000s	82.393us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	43.000s	214.684us	47	50	94.00
		aes_control_fi	43.000s	55.684us	287	300	95.67
		aes_cipher_fi	43.000s	52.508us	325	350	92.86
V2S		TOTAL			916	985	92.99
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	50.000s	2.107ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1519	1602	94.82

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.31	97.67	94.75	98.74	93.60	98.07	91.11	98.84	98.79

Failure Buckets

UVM_FATAL (alert_receiver_driver.sv:146) [driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q has 26 failures:

Test aes_shadow_reg_errors_with_csr_rw has 11 failures.

0.aes_shadow_reg_errors_with_csr_rw.100054339849095264752637163122528832528947655375955202433753714062675411036706
Line 104, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/0.aes_shadow_reg_errors_with_csr_rw/latest/run.log

  UVM_FATAL @  76628127 ps: (alert_receiver_driver.sv:146) [uvm_test_top.env.m_alert_agent_fatal_fault.driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q
  UVM_INFO @  76628127 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.aes_shadow_reg_errors_with_csr_rw.1746521351542175575023418085430419014573131604508142300439099164432376023617
Line 103, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/2.aes_shadow_reg_errors_with_csr_rw/latest/run.log

  UVM_FATAL @  42605190 ps: (alert_receiver_driver.sv:146) [uvm_test_top.env.m_alert_agent_fatal_fault.driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q
  UVM_INFO @  42605190 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 9 more failures.

Test aes_shadow_reg_errors has 10 failures.

2.aes_shadow_reg_errors.86739080597629908328268927266709483123466713769552976669649482665745645668275
Line 103, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/2.aes_shadow_reg_errors/latest/run.log

  UVM_FATAL @  18674307 ps: (alert_receiver_driver.sv:146) [uvm_test_top.env.m_alert_agent_fatal_fault.driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q
  UVM_INFO @  18674307 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.aes_shadow_reg_errors.43006037368980005365602613879104401419952102469967697473040195759634870375898
Line 103, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/4.aes_shadow_reg_errors/latest/run.log

  UVM_FATAL @  64744435 ps: (alert_receiver_driver.sv:146) [uvm_test_top.env.m_alert_agent_fatal_fault.driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q
  UVM_INFO @  64744435 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 8 more failures.

Test aes_stress_all has 1 failures.

5.aes_stress_all.2910109710260658874020713774434949912957393118153313236471600031249844459414
Line 71616, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/5.aes_stress_all/latest/run.log

  UVM_FATAL @ 1344853404 ps: (alert_receiver_driver.sv:146) [uvm_test_top.env.m_alert_agent_fatal_fault.driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q
  UVM_INFO @ 1344853404 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test aes_stress_all_with_rand_reset has 1 failures.

7.aes_stress_all_with_rand_reset.61976112465218939050799030227263292647874436069223011926957467896536010393789
Line 234, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/7.aes_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @ 128848497 ps: (alert_receiver_driver.sv:146) [uvm_test_top.env.m_alert_agent_fatal_fault.driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q
  UVM_INFO @ 128848497 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test aes_fi has 2 failures.

20.aes_fi.60495495335354061179854812204399252094615134826856225983724735144092839034444
Line 408, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/20.aes_fi/latest/run.log

  UVM_FATAL @  12705870 ps: (alert_receiver_driver.sv:146) [uvm_test_top.env.m_alert_agent_fatal_fault.driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q
  UVM_INFO @  12705870 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

22.aes_fi.41424189938869368654011252609301918888480126691860285703649975228000304653093
Line 3342, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/22.aes_fi/latest/run.log

  UVM_FATAL @  41077905 ps: (alert_receiver_driver.sv:146) [uvm_test_top.env.m_alert_agent_fatal_fault.driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q
  UVM_INFO @  41077905 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more tests.

Job timed out after * minutes has 26 failures:
- Test aes_control_fi has 9 failures.
  - 16.aes_control_fi.38498179785242881532258722607403178236043854004168063787818318964804322449051
    Log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/16.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 43.aes_control_fi.111190943252262416835942155431560580366529222943744890289622541241066151350015
    Log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/43.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 7 more failures.
- Test aes_cipher_fi has 17 failures.
  - 26.aes_cipher_fi.58268869481316118506352905925988053099767708484329103387970527237700481667851
    Log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/26.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 30.aes_cipher_fi.55782552471486031712171340393683850328451967365163675593771306801774049833907
    Log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/30.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 15 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 8 failures:

Test aes_stress_all_with_rand_reset has 8 failures.

0.aes_stress_all_with_rand_reset.48566018824221636720646312765314327107814402383196934936396334796436440659236
Line 765, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2106867267 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 2106867267 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.aes_stress_all_with_rand_reset.114339673390829043858903336767357141932001611294861641934988983090798511964149
Line 744, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 436323247 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 436323247 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 6 more failures.

UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 8 failures:
- Test aes_cipher_fi has 8 failures.
  - 2.aes_cipher_fi.36475513468117393738239598440105908014065625996137295192974194309223916305378
    Line 134, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/2.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10005529482 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10005529482 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 28.aes_cipher_fi.5700115568561395217955194760057762596235640590386104233031487054618596808377
    Line 132, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/28.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10006272422 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10006272422 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 6 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 4 failures:
- Test aes_control_fi has 4 failures.
  - 96.aes_control_fi.48364301641071317245059342165953198028729627651120359508669242726773046125652
    Line 143, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/96.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10008103377 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10008103377 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 159.aes_control_fi.47088145757909709807071674914979876345986632224743128631676920675399286705218
    Line 140, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/159.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10003909552 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10003909552 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 2 more failures.
UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 3 failures:
- Test aes_core_fi has 3 failures.
  - 30.aes_core_fi.41902550594276313417743417505590473495689138219365395436724000281261981051958
    Line 138, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/30.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10009289948 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10009289948 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 49.aes_core_fi.58541702860106067819037981255688993703462072119519480324476200416382752873978
    Line 143, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/49.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10019961158 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10019961158 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
UVM_ERROR (cip_base_scoreboard.sv:249) scoreboard [scoreboard] alert fatal_fault has unexpected timeout error has 2 failures:
- Test aes_stress_all has 1 failures.
  - 0.aes_stress_all.58973301905044732939090284174661769065370388119361561203655666343392274186028
    Line 1089, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/0.aes_stress_all/latest/run.log
```
  UVM_ERROR @  63781603 ps: (cip_base_scoreboard.sv:249) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
  UVM_INFO @  63781603 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test aes_alert_reset has 1 failures.
  - 11.aes_alert_reset.83981642509805524648121486966433060769652175760305875590509922367147413681406
    Line 579, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/11.aes_alert_reset/latest/run.log
```
  UVM_ERROR @  32162479 ps: (cip_base_scoreboard.sv:249) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
  UVM_INFO @  32162479 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:980) [aes_common_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == * (* [*] vs * [*]) fatal error fatal_fault does not trigger! has 2 failures:
- Test aes_shadow_reg_errors_with_csr_rw has 1 failures.
  - 4.aes_shadow_reg_errors_with_csr_rw.42129349923731549755490491661185504838647158059417360929858016354330768690209
    Line 104, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/4.aes_shadow_reg_errors_with_csr_rw/latest/run.log
```
  UVM_ERROR @ 331838556 ps: (cip_base_vseq.sv:980) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_fault does not trigger!
  UVM_INFO @ 331838556 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test aes_shadow_reg_errors has 1 failures.
  - 16.aes_shadow_reg_errors.106837714206762377222110768654629560392773528069845423816419464577117658952665
    Line 103, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/16.aes_shadow_reg_errors/latest/run.log
```
  UVM_ERROR @  18738017 ps: (cip_base_vseq.sv:980) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_fault does not trigger!
  UVM_INFO @  18738017 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_base_vseq.sv:74) [aes_alert_reset_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 5.aes_stress_all_with_rand_reset.79780170951054804361386066360806232808821361148157767820661383434545351054605
    Line 141, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/5.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 341656388 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 341656388 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

xmsim: *E,ASRTST (/nightly/runs/scratch/master/aes_unmasked-sim-xcelium/default/src/lowrisc_ip_aes_*/rtl/aes_core.sv,987): Assertion AesSecCmDataRegLocalEscDataOut has failed (* cycles, starting * PS) has 1 failures:

Test aes_fi has 1 failures.

6.aes_fi.98403950298873625434240477812267578786732408858299698066763523950929355955797
Line 428, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/6.aes_fi/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/aes_unmasked-sim-xcelium/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,987): (time 36206415 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscDataOut has failed (2 cycles, starting 36150859 PS)
        ($past(iv_q) != $past(state_done_transposed, 2) ^ $past(data_in_prev_q, 2)))
                                                                                   |
  xmsim: *E,ASRTST (/nightly/runs/scratch/master/aes_unmasked-sim-xcelium/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,993): (time 36206415 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscIv has failed (2 cycles, starting 36150859 PS)
  UVM_ERROR @  36206415 ps: (aes_core.sv:987) [ASSERT FAILED] AesSecCmDataRegLocalEscDataOut

UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=8) has 1 failures:
- Test aes_core_fi has 1 failures.
  - 36.aes_core_fi.76107337464115875082134631908876185692654320624234684533496292024793216663013
    Line 136, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/36.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10009726073 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=0x7dc4e884, Comparison=CompareOpEq, exp_data=0x0, call_count=8)
  UVM_INFO @ 10009726073 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=12) has 1 failures:
- Test aes_core_fi has 1 failures.
  - 51.aes_core_fi.102378156149811841481350351565182958496209472177937057013848713368596264319927
    Line 141, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/51.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10012605560 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=0x461d7f84, Comparison=CompareOpEq, exp_data=0x0, call_count=12)
  UVM_INFO @ 10012605560 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```