AON_TIMER Simulation Results

Sunday March 23 2025 00:10:17 UTC

GitHub Revision: 27fc640f8d

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	aon_timer_smoke	2.540s	589.481us	5	5	100.00
V1	csr_hw_reset	aon_timer_csr_hw_reset	2.750s	783.496us	5	5	100.00
V1	csr_rw	aon_timer_csr_rw	2.590s	519.633us	20	20	100.00
V1	csr_bit_bash	aon_timer_csr_bit_bash	7.680s	14.022ms	5	5	100.00
V1	csr_aliasing	aon_timer_csr_aliasing	2.690s	665.077us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aon_timer_csr_mem_rw_with_rand_reset	2.690s	467.427us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aon_timer_csr_rw	2.590s	519.633us	20	20	100.00
		aon_timer_csr_aliasing	2.690s	665.077us	5	5	100.00
V1	mem_walk	aon_timer_mem_walk	2.300s	455.979us	5	5	100.00
V1	mem_partial_access	aon_timer_mem_partial_access	2.480s	339.637us	5	5	100.00
V1		TOTAL			70	70	100.00
V2	prescaler	aon_timer_prescaler	42.880s	28.241ms	15	15	100.00
V2	jump	aon_timer_jump	2.660s	510.374us	5	5	100.00
V2	stress_all	aon_timer_stress_all	1.624m	153.185ms	15	15	100.00
V2	intr_test	aon_timer_intr_test	2.390s	513.000us	50	50	100.00
V2	tl_d_oob_addr_access	aon_timer_tl_errors	3.510s	539.322us	20	20	100.00
V2	tl_d_illegal_access	aon_timer_tl_errors	3.510s	539.322us	20	20	100.00
V2	tl_d_outstanding_access	aon_timer_csr_hw_reset	2.750s	783.496us	5	5	100.00
		aon_timer_csr_rw	2.590s	519.633us	20	20	100.00
		aon_timer_csr_aliasing	2.690s	665.077us	5	5	100.00
		aon_timer_same_csr_outstanding	9.180s	2.489ms	20	20	100.00
V2	tl_d_partial_access	aon_timer_csr_hw_reset	2.750s	783.496us	5	5	100.00
		aon_timer_csr_rw	2.590s	519.633us	20	20	100.00
		aon_timer_csr_aliasing	2.690s	665.077us	5	5	100.00
		aon_timer_same_csr_outstanding	9.180s	2.489ms	20	20	100.00
V2		TOTAL			125	125	100.00
V2S	tl_intg_err	aon_timer_sec_cm	11.590s	7.823ms	5	5	100.00
		aon_timer_tl_intg_err	6.540s	4.584ms	19	20	95.00
V2S	sec_cm_bus_integrity	aon_timer_tl_intg_err	6.540s	4.584ms	19	20	95.00
V2S		TOTAL			24	25	96.00
V3	max_threshold	aon_timer_smoke_max_thold	2.690s	598.431us	5	5	100.00
V3	min_threshold	aon_timer_smoke_min_thold	3.430s	724.997us	5	5	100.00
V3	wkup_count_hi_cdc	aon_timer_wkup_count_cdc_hi	8.900s	3.633ms	5	5	100.00
V3	custom_intr	aon_timer_custom_intr	3.780s	629.410us	10	10	100.00
V3	alternating_on_off	aon_timer_alternating_enable_on_off	7.510s	4.073ms	5	5	100.00
V3	stress_all_with_rand_reset	aon_timer_stress_all_with_rand_reset	33.930s	10.065ms	15	15	100.00
V3		TOTAL			45	45	100.00
	Unmapped tests	aon_timer_alert_test	2.810s	377.257us	50	50	100.00
		TOTAL			314	315	99.68

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.76	99.92	99.88	74.91	--	99.82	100.00	100.00

Failure Buckets

• UVM_FATAL (cip_base_vseq.sv:665) [aon_timer_common_vseq] timeout wait for alert handshake:fatal_fault has 1 failures:
  • Test aon_timer_tl_intg_err has 1 failures.

    • 18.aon_timer_tl_intg_err.10700012366677182898669537940336969533743326820567087986860000273587241756972
      Line 130, in log /nightly/runs/scratch/master/aon_timer-sim-vcs/18.aon_timer_tl_intg_err/latest/run.log

        UVM_FATAL @ 13366739380 ps: (cip_base_vseq.sv:665) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] timeout wait for alert handshake:fatal_fault
        UVM_INFO @ 13366739380 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---