CSRNG Simulation Results

Sunday March 23 2025 00:10:17 UTC

GitHub Revision: `27fc640f8d`

Branch: master

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	9.000s	278.792us	50	50	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	5.000s	14.813us	5	5	100.00
V1	csr_rw	csrng_csr_rw	7.000s	201.745us	20	20	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	39.000s	2.364ms	5	5	100.00
V1	csr_aliasing	csrng_csr_aliasing	8.000s	81.655us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	7.000s	133.785us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	7.000s	201.745us	20	20	100.00
		csrng_csr_aliasing	8.000s	81.655us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	interrupts	csrng_intr	21.000s	799.236us	199	200	99.50
V2	alerts	csrng_alert	54.900m	200.000ms	497	500	99.40
V2	err	csrng_err	7.000s	73.024us	499	500	99.80
V2	cmds	csrng_cmds	6.467m	36.888ms	50	50	100.00
V2	life cycle	csrng_cmds	6.467m	36.888ms	50	50	100.00
V2	stress_all	csrng_stress_all	55.767m	256.678ms	47	50	94.00
V2	intr_test	csrng_intr_test	6.000s	78.401us	50	50	100.00
V2	alert_test	csrng_alert_test	7.000s	89.189us	50	50	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	15.000s	975.493us	20	20	100.00
V2	tl_d_illegal_access	csrng_tl_errors	15.000s	975.493us	20	20	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	5.000s	14.813us	5	5	100.00
		csrng_csr_rw	7.000s	201.745us	20	20	100.00
		csrng_csr_aliasing	8.000s	81.655us	5	5	100.00
		csrng_same_csr_outstanding	9.000s	376.239us	20	20	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	5.000s	14.813us	5	5	100.00
		csrng_csr_rw	7.000s	201.745us	20	20	100.00
		csrng_csr_aliasing	8.000s	81.655us	5	5	100.00
		csrng_same_csr_outstanding	9.000s	376.239us	20	20	100.00
V2		TOTAL			1432	1440	99.44
V2S	tl_intg_err	csrng_sec_cm	7.000s	304.553us	5	5	100.00
		csrng_tl_intg_err	2.517m	10.076ms	19	20	95.00
V2S	sec_cm_config_regwen	csrng_regwen	7.000s	64.409us	50	50	100.00
		csrng_csr_rw	7.000s	201.745us	20	20	100.00
V2S	sec_cm_config_mubi	csrng_alert	54.900m	200.000ms	497	500	99.40
V2S	sec_cm_intersig_mubi	csrng_stress_all	55.767m	256.678ms	47	50	94.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	21.000s	799.236us	199	200	99.50
		csrng_err	7.000s	73.024us	499	500	99.80
		csrng_sec_cm	7.000s	304.553us	5	5	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	21.000s	799.236us	199	200	99.50
		csrng_err	7.000s	73.024us	499	500	99.80
		csrng_sec_cm	7.000s	304.553us	5	5	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	21.000s	799.236us	199	200	99.50
		csrng_err	7.000s	73.024us	499	500	99.80
		csrng_sec_cm	7.000s	304.553us	5	5	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	21.000s	799.236us	199	200	99.50
		csrng_err	7.000s	73.024us	499	500	99.80
		csrng_sec_cm	7.000s	304.553us	5	5	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	21.000s	799.236us	199	200	99.50
		csrng_err	7.000s	73.024us	499	500	99.80
		csrng_sec_cm	7.000s	304.553us	5	5	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	21.000s	799.236us	199	200	99.50
		csrng_err	7.000s	73.024us	499	500	99.80
		csrng_sec_cm	7.000s	304.553us	5	5	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	21.000s	799.236us	199	200	99.50
		csrng_err	7.000s	73.024us	499	500	99.80
		csrng_sec_cm	7.000s	304.553us	5	5	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	54.900m	200.000ms	497	500	99.40
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	21.000s	799.236us	199	200	99.50
		csrng_err	7.000s	73.024us	499	500	99.80
V2S	sec_cm_constants_lc_gated	csrng_stress_all	55.767m	256.678ms	47	50	94.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	54.900m	200.000ms	497	500	99.40
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	2.517m	10.076ms	19	20	95.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	21.000s	799.236us	199	200	99.50
		csrng_err	7.000s	73.024us	499	500	99.80
		csrng_sec_cm	7.000s	304.553us	5	5	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	21.000s	799.236us	199	200	99.50
		csrng_err	7.000s	73.024us	499	500	99.80
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	21.000s	799.236us	199	200	99.50
		csrng_err	7.000s	73.024us	499	500	99.80
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	21.000s	799.236us	199	200	99.50
		csrng_err	7.000s	73.024us	499	500	99.80
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	21.000s	799.236us	199	200	99.50
		csrng_err	7.000s	73.024us	499	500	99.80
		csrng_sec_cm	7.000s	304.553us	5	5	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	21.000s	799.236us	199	200	99.50
		csrng_err	7.000s	73.024us	499	500	99.80
V2S		TOTAL			74	75	98.67
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	1.583m	2.298ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1611	1630	98.83

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.79	98.63	96.68	99.97	97.42	92.15	100.00	97.35	90.82

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:891) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 9 failures:
- Test csrng_stress_all_with_rand_reset has 9 failures.
  - 0.csrng_stress_all_with_rand_reset.68416444490987668328930213691084034590248537673975472429632437280362493644390
    Line 104, in log /nightly/runs/scratch/master/csrng-sim-xcelium/0.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2083881281 ps: (cip_base_vseq.sv:891) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2083881281 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.csrng_stress_all_with_rand_reset.22153188471698230832253065417782841746889522548825517459836653469787776246578
    Line 103, in log /nightly/runs/scratch/master/csrng-sim-xcelium/1.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 5064979277 ps: (cip_base_vseq.sv:891) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 5064979277 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 7 more failures.

UVM_ERROR (csrng_scoreboard.sv:166) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 3 failures:

Test csrng_stress_all has 3 failures.

17.csrng_stress_all.69816671862991542655579040179611927376853544366718966722607057674209439880372
Line 164, in log /nightly/runs/scratch/master/csrng-sim-xcelium/17.csrng_stress_all/latest/run.log

  UVM_ERROR @ 3751339344 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 3751339344 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

18.csrng_stress_all.34310004115346882837958982741960895513291808472776010047599223395696369115741
Line 154, in log /nightly/runs/scratch/master/csrng-sim-xcelium/18.csrng_stress_all/latest/run.log

  UVM_ERROR @ 1999057845 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 1999057845 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Job timed out after * minutes has 2 failures:
- Test csrng_alert has 2 failures.
  - 41.csrng_alert.86183905808853501362419132417108071596059100554263620002705244483153363891790
    Log /nightly/runs/scratch/master/csrng-sim-xcelium/41.csrng_alert/latest/run.log
```
  Job timed out after 60 minutes
```
  - 359.csrng_alert.47628458863029981910690217524809229776489354938862232636652884341190068580286
    Log /nightly/runs/scratch/master/csrng-sim-xcelium/359.csrng_alert/latest/run.log
```
  Job timed out after 60 minutes
```
UVM_FATAL sequencer [SEQ_NOT_DONE] Sequence m_edn_push_seq[*] already started has 1 failures:
- Test csrng_stress_all_with_rand_reset has 1 failures.
  - 9.csrng_stress_all_with_rand_reset.88307655781528944481235305856395594963036739107391259344355207682011301262160
    Line 106, in log /nightly/runs/scratch/master/csrng-sim-xcelium/9.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @  27010100 ps: uvm_test_top.env.m_edn_agent[1].m_cmd_push_agent.sequencer [SEQ_NOT_DONE] Sequence uvm_test_top.env.m_edn_agent[1].m_cmd_push_agent.sequencer.m_edn_push_seq[1] already started
  UVM_INFO @  27010100 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (cip_base_vseq.sv:666) [csrng_common_vseq] timeout wait for alert handshake:fatal_alert has 1 failures:
- Test csrng_tl_intg_err has 1 failures.
  - 15.csrng_tl_intg_err.94109356197866537216840938299220240772972808168670385930350782416285156208925
    Line 121, in log /nightly/runs/scratch/master/csrng-sim-xcelium/15.csrng_tl_intg_err/latest/run.log
```
  UVM_FATAL @ 10075667034 ps: (cip_base_vseq.sv:666) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] timeout wait for alert handshake:fatal_alert
  UVM_INFO @ 10075667034 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/src/lowrisc_ip_csrng_*/rtl/csrng_cmd_stage.sv,518): Assertion CsrngCmdStageGenbitsFifoPushExpected_A has failed has 1 failures:

Test csrng_intr has 1 failures.

89.csrng_intr.32244589435137307141824033788570411192673752146097735163813863409022331234324
Line 134, in log /nightly/runs/scratch/master/csrng-sim-xcelium/89.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_cmd_stage.sv,518): (time 198411784 PS) Assertion tb.dut.u_csrng_core.gen_cmd_stage[2].u_csrng_cmd_stage.CsrngCmdStageGenbitsFifoPushExpected_A has failed
  UVM_ERROR @ 198411784 ps: (csrng_cmd_stage.sv:518) [ASSERT FAILED] CsrngCmdStageGenbitsFifoPushExpected_A
  UVM_INFO @ 198411784 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (csr_utils_pkg.sv:468) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: csrng_reg_block.err_code.cmd_gen_cnt_err reset value: * has 1 failures:
- Test csrng_err has 1 failures.
  - 202.csrng_err.65429895123093005370598969851533794905325051254602520127359254792012032565604
    Line 134, in log /nightly/runs/scratch/master/csrng-sim-xcelium/202.csrng_err/latest/run.log
```
  UVM_ERROR @   5907278 ps: (csr_utils_pkg.sv:468) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: csrng_reg_block.err_code.cmd_gen_cnt_err reset value: 0x0
  UVM_INFO @   5907278 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test csrng_alert has 1 failures.
  - 361.csrng_alert.34495683165112323299711590374107011062334293018256591125150074808925994354604
    Line 128, in log /nightly/runs/scratch/master/csrng-sim-xcelium/361.csrng_alert/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```