EDN Simulation Results

Sunday March 23 2025 00:10:17 UTC

GitHub Revision: 27fc640f8d

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	2.640s	20.451us	50	50	100.00
V1	csr_hw_reset	edn_csr_hw_reset	2.570s	24.828us	5	5	100.00
V1	csr_rw	edn_csr_rw	2.400s	44.224us	20	20	100.00
V1	csr_bit_bash	edn_csr_bit_bash	6.140s	169.509us	5	5	100.00
V1	csr_aliasing	edn_csr_aliasing	2.790s	164.469us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	3.370s	469.092us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	2.400s	44.224us	20	20	100.00
		edn_csr_aliasing	2.790s	164.469us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	firmware	edn_genbits	1.536m	8.764ms	300	300	100.00
V2	csrng_commands	edn_genbits	1.536m	8.764ms	300	300	100.00
V2	genbits	edn_genbits	1.536m	8.764ms	300	300	100.00
V2	interrupts	edn_intr	2.710s	21.395us	50	50	100.00
V2	alerts	edn_alert	3.000s	147.466us	200	200	100.00
V2	errs	edn_err	2.940s	45.846us	100	100	100.00
V2	disable	edn_disable	2.600s	17.435us	50	50	100.00
		edn_disable_auto_req_mode	3.110s	103.917us	49	50	98.00
V2	stress_all	edn_stress_all	9.280s	350.016us	50	50	100.00
V2	intr_test	edn_intr_test	2.540s	26.895us	50	50	100.00
V2	alert_test	edn_alert_test	2.600s	18.409us	50	50	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	5.030s	133.653us	20	20	100.00
V2	tl_d_illegal_access	edn_tl_errors	5.030s	133.653us	20	20	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	2.570s	24.828us	5	5	100.00
		edn_csr_rw	2.400s	44.224us	20	20	100.00
		edn_csr_aliasing	2.790s	164.469us	5	5	100.00
		edn_same_csr_outstanding	2.870s	128.906us	20	20	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	2.570s	24.828us	5	5	100.00
		edn_csr_rw	2.400s	44.224us	20	20	100.00
		edn_csr_aliasing	2.790s	164.469us	5	5	100.00
		edn_same_csr_outstanding	2.870s	128.906us	20	20	100.00
V2		TOTAL			939	940	99.89
V2S	tl_intg_err	edn_sec_cm	11.750s	993.797us	4	5	80.00
		edn_tl_intg_err	4.290s	250.096us	20	20	100.00
V2S	sec_cm_config_regwen	edn_regwen	2.530s	17.723us	10	10	100.00
V2S	sec_cm_config_mubi	edn_alert	3.000s	147.466us	200	200	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	11.750s	993.797us	4	5	80.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	11.750s	993.797us	4	5	80.00
V2S	sec_cm_fifo_ctr_redun	edn_sec_cm	11.750s	993.797us	4	5	80.00
V2S	sec_cm_ctr_redun	edn_sec_cm	11.750s	993.797us	4	5	80.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	3.000s	147.466us	200	200	100.00
		edn_sec_cm	11.750s	993.797us	4	5	80.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	3.000s	147.466us	200	200	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	4.290s	250.096us	20	20	100.00
V2S		TOTAL			34	35	97.14
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	2.863h	10.000s	30	50	60.00
V3		TOTAL			30	50	60.00
		TOTAL			1108	1130	98.05

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.84	98.32	94.23	97.02	91.86	96.33	99.78	93.32

Failure Buckets

• Job timed out after * minutes has 19 failures:

  • Test edn_stress_all_with_rand_reset has 19 failures.

    • 2.edn_stress_all_with_rand_reset.101919693152963917222558601113407441248806798050296986205818826842675223565185
      Log /nightly/runs/scratch/master/edn-sim-vcs/2.edn_stress_all_with_rand_reset/latest/run.log

        Job timed out after 180 minutes
      

    • 5.edn_stress_all_with_rand_reset.14239894875796790459180259121593200664357037862703064151282454438871682035601
      Log /nightly/runs/scratch/master/edn-sim-vcs/5.edn_stress_all_with_rand_reset/latest/run.log

        Job timed out after 180 minutes
      

    • ... and 17 more failures.

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:

  • Test edn_stress_all_with_rand_reset has 1 failures.

    • 3.edn_stress_all_with_rand_reset.109619288440376772773369543060570614916502617654830259326503983816497197377445
      Line 237, in log /nightly/runs/scratch/master/edn-sim-vcs/3.edn_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test edn_disable_auto_req_mode has 1 failures.

    • 46.edn_disable_auto_req_mode.92604757095108969408005899637810866522200137029493505637057941493348475078497
      Line 85, in log /nightly/runs/scratch/master/edn-sim-vcs/46.edn_disable_auto_req_mode/latest/run.log

        UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (alert_receiver_driver.sv:145) [driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q has 1 failures:

  • Test edn_sec_cm has 1 failures.

    • 1.edn_sec_cm.9360086857048334088390301565946523019180788779086137576133139062690774243774
      Line 509, in log /nightly/runs/scratch/master/edn-sim-vcs/1.edn_sec_cm/latest/run.log

        UVM_FATAL @ 157595758 ps: (alert_receiver_driver.sv:145) [uvm_test_top.env.m_alert_agent_fatal_alert.driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q
        UVM_INFO @ 157595758 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---