ENTROPY_SRC Simulation Results

Sunday March 23 2025 00:10:17 UTC

GitHub Revision: 27fc640f8d

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke entropy_src_smoke 35.000s 89.365us 50 50 100.00
V1 csr_hw_reset entropy_src_csr_hw_reset 5.000s 25.053us 5 5 100.00
V1 csr_rw entropy_src_csr_rw 10.000s 66.671us 20 20 100.00
V1 csr_bit_bash entropy_src_csr_bit_bash 16.000s 3.204ms 5 5 100.00
V1 csr_aliasing entropy_src_csr_aliasing 9.000s 276.088us 5 5 100.00
V1 csr_mem_rw_with_rand_reset entropy_src_csr_mem_rw_with_rand_reset 6.000s 30.534us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr entropy_src_csr_rw 10.000s 66.671us 20 20 100.00
entropy_src_csr_aliasing 9.000s 276.088us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 firmware entropy_src_smoke 35.000s 89.365us 50 50 100.00
entropy_src_rng 10.533m 20.031ms 199 300 66.33
entropy_src_fw_ov 9.300m 20.089ms 135 300 45.00
V2 firmware_mode entropy_src_fw_ov 9.300m 20.089ms 135 300 45.00
V2 rng_mode entropy_src_rng 10.533m 20.031ms 199 300 66.33
V2 rng_max_rate entropy_src_rng_max_rate 15.367m 20.040ms 180 400 45.00
V2 health_checks entropy_src_rng 10.533m 20.031ms 199 300 66.33
V2 conditioning entropy_src_rng 10.533m 20.031ms 199 300 66.33
V2 interrupts entropy_src_rng 10.533m 20.031ms 199 300 66.33
entropy_src_intr 53.000s 5.063ms 50 50 100.00
V2 alerts entropy_src_rng 10.533m 20.031ms 199 300 66.33
entropy_src_functional_alerts 33.000s 214.682us 50 50 100.00
V2 stress_all entropy_src_stress_all 7.383m 15.225ms 48 50 96.00
V2 functional_errors entropy_src_functional_errors 8.750m 10.012ms 961 1000 96.10
V2 firmware_ov_read_contiguous_data entropy_src_fw_ov_contiguous 44.000s 661.530us 50 50 100.00
V2 intr_test entropy_src_intr_test 5.000s 46.821us 50 50 100.00
V2 alert_test entropy_src_alert_test 12.000s 37.684us 50 50 100.00
V2 tl_d_oob_addr_access entropy_src_tl_errors 8.000s 134.789us 20 20 100.00
V2 tl_d_illegal_access entropy_src_tl_errors 8.000s 134.789us 20 20 100.00
V2 tl_d_outstanding_access entropy_src_csr_hw_reset 5.000s 25.053us 5 5 100.00
entropy_src_csr_rw 10.000s 66.671us 20 20 100.00
entropy_src_csr_aliasing 9.000s 276.088us 5 5 100.00
entropy_src_same_csr_outstanding 6.000s 130.126us 20 20 100.00
V2 tl_d_partial_access entropy_src_csr_hw_reset 5.000s 25.053us 5 5 100.00
entropy_src_csr_rw 10.000s 66.671us 20 20 100.00
entropy_src_csr_aliasing 9.000s 276.088us 5 5 100.00
entropy_src_same_csr_outstanding 6.000s 130.126us 20 20 100.00
V2 TOTAL 1813 2340 77.48
V2S tl_intg_err entropy_src_sec_cm 22.000s 71.652us 5 5 100.00
entropy_src_tl_intg_err 8.000s 450.274us 20 20 100.00
V2S sec_cm_config_regwen entropy_src_rng 10.533m 20.031ms 199 300 66.33
entropy_src_cfg_regwen 29.000s 15.305us 50 50 100.00
V2S sec_cm_config_mubi entropy_src_rng 10.533m 20.031ms 199 300 66.33
V2S sec_cm_config_redun entropy_src_rng 10.533m 20.031ms 199 300 66.33
V2S sec_cm_intersig_mubi entropy_src_rng 10.533m 20.031ms 199 300 66.33
entropy_src_fw_ov 9.300m 20.089ms 135 300 45.00
V2S sec_cm_main_sm_fsm_sparse entropy_src_functional_errors 8.750m 10.012ms 961 1000 96.10
entropy_src_sec_cm 22.000s 71.652us 5 5 100.00
V2S sec_cm_ack_sm_fsm_sparse entropy_src_functional_errors 8.750m 10.012ms 961 1000 96.10
entropy_src_sec_cm 22.000s 71.652us 5 5 100.00
V2S sec_cm_rng_bkgn_chk entropy_src_rng 10.533m 20.031ms 199 300 66.33
V2S sec_cm_fifo_ctr_redun entropy_src_functional_errors 8.750m 10.012ms 961 1000 96.10
entropy_src_sec_cm 22.000s 71.652us 5 5 100.00
V2S sec_cm_ctr_redun entropy_src_functional_errors 8.750m 10.012ms 961 1000 96.10
entropy_src_sec_cm 22.000s 71.652us 5 5 100.00
V2S sec_cm_ctr_local_esc entropy_src_functional_errors 8.750m 10.012ms 961 1000 96.10
V2S sec_cm_esfinal_rdata_bus_consistency entropy_src_functional_alerts 33.000s 214.682us 50 50 100.00
V2S sec_cm_tile_link_bus_integrity entropy_src_tl_intg_err 8.000s 450.274us 20 20 100.00
V2S TOTAL 75 75 100.00
V3 external_health_tests entropy_src_rng_with_xht_rsps 10.083m 20.017ms 36 50 72.00
V3 TOTAL 36 50 72.00
TOTAL 2029 2570 78.95

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
97.12 98.15 95.32 98.33 95.50 96.77 96.88 90.95 95.84

Failure Buckets