HMAC Simulation Results

Sunday March 23 2025 00:10:17 UTC

GitHub Revision: 27fc640f8d

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	hmac_smoke	14.720s	888.409us	50	50	100.00
V1	csr_hw_reset	hmac_csr_hw_reset	2.170s	41.618us	5	5	100.00
V1	csr_rw	hmac_csr_rw	2.460s	37.520us	20	20	100.00
V1	csr_bit_bash	hmac_csr_bit_bash	17.890s	1.895ms	5	5	100.00
V1	csr_aliasing	hmac_csr_aliasing	9.310s	151.666us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	hmac_csr_mem_rw_with_rand_reset	14.680m	203.856ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	hmac_csr_rw	2.460s	37.520us	20	20	100.00
		hmac_csr_aliasing	9.310s	151.666us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	long_msg	hmac_long_msg	1.483m	6.053ms	50	50	100.00
V2	back_pressure	hmac_back_pressure	1.641m	6.640ms	50	50	100.00
V2	test_vectors	hmac_test_sha256_vectors	3.264m	22.331ms	30	30	100.00
		hmac_test_sha384_vectors	8.030m	11.861ms	75	75	100.00
		hmac_test_sha512_vectors	6.436m	44.880ms	75	75	100.00
		hmac_test_hmac256_vectors	11.610s	517.753us	50	50	100.00
		hmac_test_hmac384_vectors	13.970s	1.230ms	60	60	100.00
		hmac_test_hmac512_vectors	16.490s	2.694ms	75	75	100.00
V2	burst_wr	hmac_burst_wr	37.380s	680.937us	50	50	100.00
V2	datapath_stress	hmac_datapath_stress	19.936m	6.896ms	50	50	100.00
V2	error	hmac_error	2.018m	16.310ms	50	50	100.00
V2	wipe_secret	hmac_wipe_secret	1.985m	19.876ms	49	50	98.00
V2	save_and_restore	hmac_smoke	14.720s	888.409us	50	50	100.00
		hmac_long_msg	1.483m	6.053ms	50	50	100.00
		hmac_back_pressure	1.641m	6.640ms	50	50	100.00
		hmac_datapath_stress	19.936m	6.896ms	50	50	100.00
		hmac_burst_wr	37.380s	680.937us	50	50	100.00
		hmac_stress_all	28.542m	12.278ms	50	50	100.00
V2	fifo_empty_status_interrupt	hmac_smoke	14.720s	888.409us	50	50	100.00
		hmac_long_msg	1.483m	6.053ms	50	50	100.00
		hmac_back_pressure	1.641m	6.640ms	50	50	100.00
		hmac_datapath_stress	19.936m	6.896ms	50	50	100.00
		hmac_wipe_secret	1.985m	19.876ms	49	50	98.00
		hmac_test_sha256_vectors	3.264m	22.331ms	30	30	100.00
		hmac_test_sha384_vectors	8.030m	11.861ms	75	75	100.00
		hmac_test_sha512_vectors	6.436m	44.880ms	75	75	100.00
		hmac_test_hmac256_vectors	11.610s	517.753us	50	50	100.00
		hmac_test_hmac384_vectors	13.970s	1.230ms	60	60	100.00
		hmac_test_hmac512_vectors	16.490s	2.694ms	75	75	100.00
V2	wide_digest_configurable_key_length	hmac_smoke	14.720s	888.409us	50	50	100.00
		hmac_long_msg	1.483m	6.053ms	50	50	100.00
		hmac_back_pressure	1.641m	6.640ms	50	50	100.00
		hmac_datapath_stress	19.936m	6.896ms	50	50	100.00
		hmac_burst_wr	37.380s	680.937us	50	50	100.00
		hmac_error	2.018m	16.310ms	50	50	100.00
		hmac_wipe_secret	1.985m	19.876ms	49	50	98.00
		hmac_test_sha256_vectors	3.264m	22.331ms	30	30	100.00
		hmac_test_sha384_vectors	8.030m	11.861ms	75	75	100.00
		hmac_test_sha512_vectors	6.436m	44.880ms	75	75	100.00
		hmac_test_hmac256_vectors	11.610s	517.753us	50	50	100.00
		hmac_test_hmac384_vectors	13.970s	1.230ms	60	60	100.00
		hmac_test_hmac512_vectors	16.490s	2.694ms	75	75	100.00
		hmac_stress_all	28.542m	12.278ms	50	50	100.00
V2	stress_all	hmac_stress_all	28.542m	12.278ms	50	50	100.00
V2	alert_test	hmac_alert_test	2.130s	14.651us	50	50	100.00
V2	intr_test	hmac_intr_test	2.130s	108.841us	50	50	100.00
V2	tl_d_oob_addr_access	hmac_tl_errors	5.380s	166.502us	20	20	100.00
V2	tl_d_illegal_access	hmac_tl_errors	5.380s	166.502us	20	20	100.00
V2	tl_d_outstanding_access	hmac_csr_hw_reset	2.170s	41.618us	5	5	100.00
		hmac_csr_rw	2.460s	37.520us	20	20	100.00
		hmac_csr_aliasing	9.310s	151.666us	5	5	100.00
		hmac_same_csr_outstanding	3.910s	501.475us	20	20	100.00
V2	tl_d_partial_access	hmac_csr_hw_reset	2.170s	41.618us	5	5	100.00
		hmac_csr_rw	2.460s	37.520us	20	20	100.00
		hmac_csr_aliasing	9.310s	151.666us	5	5	100.00
		hmac_same_csr_outstanding	3.910s	501.475us	20	20	100.00
V2		TOTAL			854	855	99.88
V2S	tl_intg_err	hmac_sec_cm	2.600s	1.755ms	5	5	100.00
		hmac_tl_intg_err	5.400s	294.213us	20	20	100.00
V2S	sec_cm_bus_integrity	hmac_tl_intg_err	5.400s	294.213us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	write_config_and_secret_key_during_msg_wr	hmac_smoke	14.720s	888.409us	50	50	100.00
V3	stress_reset	hmac_stress_reset	8.080s	832.638us	50	50	100.00
V3	stress_all_with_rand_reset	hmac_stress_all_with_rand_reset	6.478m	8.761ms	25	25	100.00
V3		TOTAL			75	75	100.00
	Unmapped tests	hmac_directed	3.740s	124.609us	1	1	100.00
		TOTAL			1060	1061	99.91

Failure Buckets

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:

  • Test hmac_wipe_secret has 1 failures.

    • 14.hmac_wipe_secret.61873273449105658398628573386441492633872942044039717764666390040637722316108
      Line 23171, in log /nightly/runs/scratch/master/hmac-sim-vcs/14.hmac_wipe_secret/latest/run.log

        UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Job returned non-zero exit code has 1 failures:

  • Test hmac has 1 failures.

    • cov_report
      Log /nightly/runs/scratch/master/hmac-sim-vcs/cov_report/cov_report.log

        Grading tests: .
      
        Error-[URG-GLF] Test load failed
          You specified the '-grade' option to URG, but grading failed: Could not load
          exclude file /nightly/runs/opentitan/hw/ip/hmac/dv/cov/hmac_cov_excl.el.
          The test may have been corrupted. Please try regenerating it. If the problem
          still persists, please contact vcs_support@synopsys.com.
      
      
        make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:241: cov_report] Error 1