27fc640f8d| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | host_smoke | i2c_host_smoke | 1.352m | 2.190ms | 50 | 50 | 100.00 |
| V1 | target_smoke | i2c_target_smoke | 41.660s | 2.784ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | i2c_csr_hw_reset | 2.680s | 111.645us | 5 | 5 | 100.00 |
| V1 | csr_rw | i2c_csr_rw | 2.720s | 46.525us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | i2c_csr_bit_bash | 4.360s | 116.426us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | i2c_csr_aliasing | 3.530s | 94.711us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | i2c_csr_mem_rw_with_rand_reset | 3.030s | 124.876us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | i2c_csr_rw | 2.720s | 46.525us | 20 | 20 | 100.00 |
| i2c_csr_aliasing | 3.530s | 94.711us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 155 | 155 | 100.00 | |||
| V2 | host_error_intr | i2c_host_error_intr | 11.980s | 2.994ms | 50 | 50 | 100.00 |
| V2 | host_stress_all | i2c_host_stress_all | 30.996m | 23.778ms | 13 | 50 | 26.00 |
| V2 | host_maxperf | i2c_host_perf | 43.641m | 28.887ms | 49 | 50 | 98.00 |
| V2 | host_override | i2c_host_override | 2.310s | 90.737us | 50 | 50 | 100.00 |
| V2 | host_fifo_watermark | i2c_host_fifo_watermark | 4.644m | 4.764ms | 50 | 50 | 100.00 |
| V2 | host_fifo_overflow | i2c_host_fifo_overflow | 2.377m | 5.596ms | 50 | 50 | 100.00 |
| V2 | host_fifo_reset | i2c_host_fifo_reset_fmt | 2.770s | 315.550us | 50 | 50 | 100.00 |
| i2c_host_fifo_fmt_empty | 25.790s | 1.038ms | 50 | 50 | 100.00 | ||
| i2c_host_fifo_reset_rx | 13.660s | 1.379ms | 50 | 50 | 100.00 | ||
| V2 | host_fifo_full | i2c_host_fifo_full | 2.968m | 3.644ms | 50 | 50 | 100.00 |
| V2 | host_timeout | i2c_host_stretch_timeout | 45.950s | 2.186ms | 50 | 50 | 100.00 |
| V2 | i2c_host_mode_toggle | i2c_host_mode_toggle | 6.680s | 557.992us | 15 | 50 | 30.00 |
| V2 | target_glitch | i2c_target_glitch | 9.510s | 14.589ms | 2 | 2 | 100.00 |
| V2 | target_stress_all | i2c_target_stress_all | 17.557m | 51.094ms | 50 | 50 | 100.00 |
| V2 | target_maxperf | i2c_target_perf | 10.320s | 6.183ms | 50 | 50 | 100.00 |
| V2 | target_fifo_empty | i2c_target_stress_rd | 1.113m | 3.909ms | 50 | 50 | 100.00 |
| i2c_target_intr_smoke | 10.020s | 5.195ms | 50 | 50 | 100.00 | ||
| V2 | target_fifo_reset | i2c_target_fifo_reset_acq | 3.520s | 917.904us | 50 | 50 | 100.00 |
| i2c_target_fifo_reset_tx | 3.730s | 3.366ms | 50 | 50 | 100.00 | ||
| V2 | target_fifo_full | i2c_target_stress_wr | 23.017m | 64.058ms | 50 | 50 | 100.00 |
| i2c_target_stress_rd | 1.113m | 3.909ms | 50 | 50 | 100.00 | ||
| i2c_target_intr_stress_wr | 5.041m | 21.315ms | 50 | 50 | 100.00 | ||
| V2 | target_timeout | i2c_target_timeout | 10.620s | 1.402ms | 50 | 50 | 100.00 |
| V2 | target_clock_stretch | i2c_target_stretch | 1.954m | 2.846ms | 45 | 50 | 90.00 |
| V2 | bad_address | i2c_target_bad_addr | 9.320s | 4.898ms | 50 | 50 | 100.00 |
| V2 | target_mode_glitch | i2c_target_hrst | 37.910s | 10.062ms | 24 | 50 | 48.00 |
| V2 | target_fifo_watermark | i2c_target_fifo_watermarks_acq | 5.600s | 2.721ms | 50 | 50 | 100.00 |
| i2c_target_fifo_watermarks_tx | 3.500s | 921.904us | 49 | 50 | 98.00 | ||
| V2 | host_mode_config_perf | i2c_host_perf | 43.641m | 28.887ms | 49 | 50 | 98.00 |
| i2c_host_perf_precise | 14.884m | 24.280ms | 50 | 50 | 100.00 | ||
| V2 | host_mode_clock_stretching | i2c_host_stretch_timeout | 45.950s | 2.186ms | 50 | 50 | 100.00 |
| V2 | target_mode_tx_stretch_ctrl | i2c_target_tx_stretch_ctrl | 28.190s | 1.787ms | 50 | 50 | 100.00 |
| V2 | target_mode_nack_generation | i2c_target_nack_acqfull | 5.600s | 2.077ms | 50 | 50 | 100.00 |
| i2c_target_nack_acqfull_addr | 5.140s | 493.600us | 50 | 50 | 100.00 | ||
| i2c_target_nack_txstretch | 3.290s | 281.652us | 36 | 50 | 72.00 | ||
| V2 | host_mode_halt_on_nak | i2c_host_may_nack | 29.540s | 1.122ms | 50 | 50 | 100.00 |
| V2 | target_mode_smbus_maxlen | i2c_target_smbus_maxlen | 4.740s | 1.162ms | 50 | 50 | 100.00 |
| V2 | alert_test | i2c_alert_test | 2.200s | 25.528us | 50 | 50 | 100.00 |
| V2 | intr_test | i2c_intr_test | 2.900s | 38.417us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | i2c_tl_errors | 3.890s | 2.239ms | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | i2c_tl_errors | 3.890s | 2.239ms | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | i2c_csr_hw_reset | 2.680s | 111.645us | 5 | 5 | 100.00 |
| i2c_csr_rw | 2.720s | 46.525us | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 3.530s | 94.711us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 3.120s | 55.597us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | i2c_csr_hw_reset | 2.680s | 111.645us | 5 | 5 | 100.00 |
| i2c_csr_rw | 2.720s | 46.525us | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 3.530s | 94.711us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 3.120s | 55.597us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 1673 | 1792 | 93.36 | |||
| V2S | tl_intg_err | i2c_tl_intg_err | 3.810s | 443.455us | 20 | 20 | 100.00 |
| i2c_sec_cm | 2.450s | 36.661us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | i2c_tl_intg_err | 3.810s | 443.455us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | host_stress_all_with_rand_reset | i2c_host_stress_all_with_rand_reset | 39.670s | 1.008ms | 0 | 10 | 0.00 |
| V3 | target_error_intr | i2c_target_unexp_stop | 4.450s | 707.064us | 0 | 50 | 0.00 |
| V3 | target_stress_all_with_rand_reset | i2c_target_stress_all_with_rand_reset | 1.461m | 3.146ms | 0 | 10 | 0.00 |
| V3 | TOTAL | 0 | 70 | 0.00 | |||
| TOTAL | 1853 | 2042 | 90.74 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 88.01 | 97.32 | 89.74 | 74.17 | 72.02 | 94.25 | 98.51 | 90.06 |
UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 49 failures:
0.i2c_host_stress_all.82139103063440069770252327751044122905501218927053115698988994838841988964912
Line 277, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 58815112768 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @16985732
1.i2c_host_stress_all.46916673801723507649633920311355782571590559590682989529636469901688699084876
Line 298, in log /nightly/runs/scratch/master/i2c-sim-vcs/1.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 144840395759 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @4563148
... and 25 more failures.
4.i2c_host_mode_toggle.70252896954355119675648959285756413670239590992151945774959742938378708100359
Line 80, in log /nightly/runs/scratch/master/i2c-sim-vcs/4.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 359516796 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @33033
5.i2c_host_mode_toggle.34398456957866996382326579782473763585663015849084062395774848582972156763665
Line 80, in log /nightly/runs/scratch/master/i2c-sim-vcs/5.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 77394901 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @65671
... and 20 more failures.
UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 27 failures:
2.i2c_target_unexp_stop.80216227536375701300345430906195389064545203655022345703092001479714691434478
Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/2.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 413260428 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 140 [0x8c])
UVM_INFO @ 413260428 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.i2c_target_unexp_stop.68803658407835474315585353651692452462077505343626730678994762087189060372413
Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/4.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 1230790626 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 233 [0xe9])
UVM_INFO @ 1230790626 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 25 more failures.
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! has 26 failures:
1.i2c_target_hrst.83089827777137324834493924495821971622804204285265763541898667154823250214812
Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/1.i2c_target_hrst/latest/run.log
UVM_FATAL @ 10017203877 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
UVM_INFO @ 10017203877 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.i2c_target_hrst.30063357120149585064513037640055374276857840087682978814236417522841696837227
Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/3.i2c_target_hrst/latest/run.log
UVM_FATAL @ 10112425894 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
UVM_INFO @ 10112425894 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 24 more failures.
UVM_ERROR (cip_base_vseq.sv:890) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 19 failures:
0.i2c_host_stress_all_with_rand_reset.84247217416355031551925479508643673037882730683196423687903796116333569637163
Line 114, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 704057314 ps: (cip_base_vseq.sv:890) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 704057314 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_host_stress_all_with_rand_reset.93565617968403950223162951534890508029076043922652886293910142684251111307451
Line 91, in log /nightly/runs/scratch/master/i2c-sim-vcs/1.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 492537854 ps: (cip_base_vseq.sv:890) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 492537854 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 8 more failures.
0.i2c_target_stress_all_with_rand_reset.64580698197521301299766836864674614380532841530215782128653695510167941610029
Line 141, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 4809760848 ps: (cip_base_vseq.sv:890) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 4809760848 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_target_stress_all_with_rand_reset.37638541090878292298352914137678612369181289108027497073457886394266312650905
Line 87, in log /nightly/runs/scratch/master/i2c-sim-vcs/1.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 865685569 ps: (cip_base_vseq.sv:890) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 865685569 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 7 more failures.
UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [*] vs * [*]) has 15 failures:
0.i2c_target_unexp_stop.50482589167863954599397461562390822240194166228640060465280046741949661685766
Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 122339927 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
UVM_INFO @ 122339927 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_target_unexp_stop.107240476147163329617776656620208786175811092044162887986954780336873295858251
Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/1.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 179105488 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
UVM_INFO @ 179105488 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 13 more failures.
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.target_nack_count reset value: * has 14 failures:
1.i2c_target_nack_txstretch.84595301107732949140075392060413911927762832086735190326522582061713482536394
Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/1.i2c_target_nack_txstretch/latest/run.log
UVM_ERROR @ 181184790 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
UVM_INFO @ 181184790 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
6.i2c_target_nack_txstretch.34217243603736846820770071953084618591715196682659420592666477448608453173492
Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/6.i2c_target_nack_txstretch/latest/run.log
UVM_ERROR @ 172664632 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
UVM_INFO @ 172664632 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 12 more failures.
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))' has 8 failures:
14.i2c_target_unexp_stop.82685842733162227851324899812452485815280239251294673134112168841747241530038
Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/14.i2c_target_unexp_stop/latest/run.log
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
UVM_ERROR @ 88343843 ps: (i2c_fifos.sv:318) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
UVM_INFO @ 88343843 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
16.i2c_target_unexp_stop.68504044018842549909992405096277202932382316265049206560342465609116596709976
Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/16.i2c_target_unexp_stop/latest/run.log
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
UVM_ERROR @ 707064013 ps: (i2c_fifos.sv:318) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
UVM_INFO @ 707064013 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 6 more failures.
UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpRead has 7 failures:
3.i2c_host_mode_toggle.97349106007281396575645508861960944531351274073166179472616554484196726847716
Line 82, in log /nightly/runs/scratch/master/i2c-sim-vcs/3.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 56421125 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
--> EXP:
---------------------------------------------------
Name Type Size Value
---------------------------------------------------
16.i2c_host_mode_toggle.59705087572887510285651754647102705850230297058228872567833430627535436037195
Line 82, in log /nightly/runs/scratch/master/i2c-sim-vcs/16.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 344668677 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
--> EXP:
---------------------------------------------------
Name Type Size Value
---------------------------------------------------
... and 5 more failures.
Job timed out after * minutes has 6 failures:
2.i2c_host_stress_all.40006613866263667006170826996867436968047253138682534977635830088683448982741
Log /nightly/runs/scratch/master/i2c-sim-vcs/2.i2c_host_stress_all/latest/run.log
Job timed out after 60 minutes
9.i2c_host_stress_all.92080259442070774230607347053869897008282726157558384273426601070730499795506
Log /nightly/runs/scratch/master/i2c-sim-vcs/9.i2c_host_stress_all/latest/run.log
Job timed out after 60 minutes
... and 3 more failures.
49.i2c_host_perf.41681191092949315043121566677505498117744294703900722407825561359834630531201
Log /nightly/runs/scratch/master/i2c-sim-vcs/49.i2c_host_perf/latest/run.log
Job timed out after 60 minutes
UVM_FATAL (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred! has 5 failures:
0.i2c_target_stretch.74021132277461198782921463138789192913096765788489281552070618823338188182993
Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_stretch/latest/run.log
UVM_FATAL @ 10008571402 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
UVM_INFO @ 10008571402 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_target_stretch.3812286194135437743519453416958335514003410616813532269489843586732390044366
Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/1.i2c_target_stretch/latest/run.log
UVM_FATAL @ 10001745430 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
UVM_INFO @ 10001745430 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
Error-[NOA] Null object access has 3 failures:
1.i2c_host_mode_toggle.106621771493168147834270106560508141077138120544111098901642666979514288342056
Line 81, in log /nightly/runs/scratch/master/i2c-sim-vcs/1.i2c_host_mode_toggle/latest/run.log
Error-[NOA] Null object access
../src/lowrisc_dv_i2c_env_0.1/i2c_reference_model.sv, 584
The object at dereference depth 0 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
23.i2c_host_mode_toggle.1487657848498934263806732516914305306006235608741707286980764827313135018485
Line 81, in log /nightly/runs/scratch/master/i2c-sim-vcs/23.i2c_host_mode_toggle/latest/run.log
Error-[NOA] Null object access
../src/lowrisc_dv_i2c_env_0.1/i2c_reference_model.sv, 584
The object at dereference depth 0 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
... and 1 more failures.
UVM_ERROR (i2c_scoreboard.sv:717) [scoreboard] controller_mode_wr_obs_fifo item uncompared: has 3 failures:
6.i2c_host_stress_all.89210910202346668728507108146726496393575551994358919174992871089809888880417
Line 290, in log /nightly/runs/scratch/master/i2c-sim-vcs/6.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 7091510371 ps: (i2c_scoreboard.sv:717) [uvm_test_top.env.scoreboard] controller_mode_wr_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @4161808
27.i2c_host_stress_all.7465500944465198267225468693163860495873655987644776450009092114330752502460
Line 180, in log /nightly/runs/scratch/master/i2c-sim-vcs/27.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 54499248520 ps: (i2c_scoreboard.sv:717) [uvm_test_top.env.scoreboard] controller_mode_wr_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @4552770
... and 1 more failures.
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) has 3 failures:
11.i2c_host_mode_toggle.45117164825941048852720368892970200573560793333583100256871360905251811528069
Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/11.i2c_host_mode_toggle/latest/run.log
UVM_FATAL @ 90036827 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=0x44ed3e14, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
UVM_INFO @ 90036827 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
31.i2c_host_mode_toggle.109565580001493704259617666188484972959126962325347399684358563920108102470008
Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/31.i2c_host_mode_toggle/latest/run.log
UVM_FATAL @ 51683081 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=0x13310f94, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
UVM_INFO @ 51683081 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR (cip_base_vseq.sv:794) [i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
7.i2c_target_stress_all_with_rand_reset.11260951179877584189691287147400765494420118228742843850471837080910641492484
Line 92, in log /nightly/runs/scratch/master/i2c-sim-vcs/7.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 862430949 ps: (cip_base_vseq.sv:794) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 862430949 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
14.i2c_host_stress_all.20380082541809996861442317176303250209481784817866404221380102891525246647620
Line 102, in log /nightly/runs/scratch/master/i2c-sim-vcs/14.i2c_host_stress_all/latest/run.log
UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpWrite has 1 failures:
43.i2c_host_stress_all.10624193828168175034498950354585572072985207568720026327322444370513450185600
Line 157, in log /nightly/runs/scratch/master/i2c-sim-vcs/43.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 53520957451 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpWrite
--> EXP:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
Error-[CNST-CIF] Constraints inconsistency failure has 1 failures:
46.i2c_target_fifo_watermarks_tx.104537885842923932829124649381618640379638021116249662703006161743743284720780
Line 115, in log /nightly/runs/scratch/master/i2c-sim-vcs/46.i2c_target_fifo_watermarks_tx/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 845
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.