KEYMGR Simulation Results

Sunday March 23 2025 00:10:17 UTC

GitHub Revision: 27fc640f8d

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke keymgr_smoke 28.180s 4.691ms 50 50 100.00
V1 random keymgr_random 48.820s 3.545ms 48 50 96.00
V1 csr_hw_reset keymgr_csr_hw_reset 2.430s 115.248us 5 5 100.00
V1 csr_rw keymgr_csr_rw 2.310s 205.435us 18 20 90.00
V1 csr_bit_bash keymgr_csr_bit_bash 12.450s 1.353ms 4 5 80.00
V1 csr_aliasing keymgr_csr_aliasing 7.540s 131.043us 5 5 100.00
V1 csr_mem_rw_with_rand_reset keymgr_csr_mem_rw_with_rand_reset 2.880s 81.827us 18 20 90.00
V1 regwen_csr_and_corresponding_lockable_csr keymgr_csr_rw 2.310s 205.435us 18 20 90.00
keymgr_csr_aliasing 7.540s 131.043us 5 5 100.00
V1 TOTAL 148 155 95.48
V2 cfgen_during_op keymgr_cfg_regwen 1.405m 1.958ms 47 50 94.00
V2 sideload keymgr_sideload 28.230s 2.863ms 48 50 96.00
keymgr_sideload_kmac 35.290s 5.005ms 50 50 100.00
keymgr_sideload_aes 28.870s 10.689ms 48 50 96.00
keymgr_sideload_otbn 31.390s 3.885ms 49 50 98.00
V2 direct_to_disabled_state keymgr_direct_to_disabled 9.150s 405.095us 50 50 100.00
V2 lc_disable keymgr_lc_disable 7.610s 307.645us 48 50 96.00
V2 kmac_error_response keymgr_kmac_rsp_err 8.790s 1.599ms 29 50 58.00
V2 invalid_sw_input keymgr_sw_invalid_input 40.310s 2.274ms 49 50 98.00
V2 invalid_hw_input keymgr_hwsw_invalid_input 44.310s 9.191ms 49 50 98.00
V2 sync_async_fault_cross keymgr_sync_async_fault_cross 22.430s 1.229ms 44 50 88.00
V2 stress_all keymgr_stress_all 9.584m 81.491ms 46 50 92.00
V2 intr_test keymgr_intr_test 2.310s 15.059us 50 50 100.00
V2 alert_test keymgr_alert_test 4.030s 21.212us 50 50 100.00
V2 tl_d_oob_addr_access keymgr_tl_errors 5.100s 1.925ms 20 20 100.00
V2 tl_d_illegal_access keymgr_tl_errors 5.100s 1.925ms 20 20 100.00
V2 tl_d_outstanding_access keymgr_csr_hw_reset 2.430s 115.248us 5 5 100.00
keymgr_csr_rw 2.310s 205.435us 18 20 90.00
keymgr_csr_aliasing 7.540s 131.043us 5 5 100.00
keymgr_same_csr_outstanding 3.810s 90.474us 16 20 80.00
V2 tl_d_partial_access keymgr_csr_hw_reset 2.430s 115.248us 5 5 100.00
keymgr_csr_rw 2.310s 205.435us 18 20 90.00
keymgr_csr_aliasing 7.540s 131.043us 5 5 100.00
keymgr_same_csr_outstanding 3.810s 90.474us 16 20 80.00
V2 TOTAL 693 740 93.65
V2S sec_cm_additional_check keymgr_sec_cm 14.390s 568.226us 5 5 100.00
V2S tl_intg_err keymgr_sec_cm 14.390s 568.226us 5 5 100.00
keymgr_tl_intg_err 7.150s 257.666us 15 20 75.00
V2S shadow_reg_update_error keymgr_shadow_reg_errors 4.800s 229.518us 4 20 20.00
V2S shadow_reg_read_clear_staged_value keymgr_shadow_reg_errors 4.800s 229.518us 4 20 20.00
V2S shadow_reg_storage_error keymgr_shadow_reg_errors 4.800s 229.518us 4 20 20.00
V2S shadowed_reset_glitch keymgr_shadow_reg_errors 4.800s 229.518us 4 20 20.00
V2S shadow_reg_update_error_with_csr_rw keymgr_shadow_reg_errors_with_csr_rw 8.130s 286.813us 3 20 15.00
V2S prim_count_check keymgr_sec_cm 14.390s 568.226us 5 5 100.00
V2S prim_fsm_check keymgr_sec_cm 14.390s 568.226us 5 5 100.00
V2S sec_cm_bus_integrity keymgr_tl_intg_err 7.150s 257.666us 15 20 75.00
V2S sec_cm_config_shadow keymgr_shadow_reg_errors 4.800s 229.518us 4 20 20.00
V2S sec_cm_op_config_regwen keymgr_cfg_regwen 1.405m 1.958ms 47 50 94.00
V2S sec_cm_reseed_config_regwen keymgr_random 48.820s 3.545ms 48 50 96.00
keymgr_csr_rw 2.310s 205.435us 18 20 90.00
V2S sec_cm_sw_binding_config_regwen keymgr_random 48.820s 3.545ms 48 50 96.00
keymgr_csr_rw 2.310s 205.435us 18 20 90.00
V2S sec_cm_max_key_ver_config_regwen keymgr_random 48.820s 3.545ms 48 50 96.00
keymgr_csr_rw 2.310s 205.435us 18 20 90.00
V2S sec_cm_lc_ctrl_intersig_mubi keymgr_lc_disable 7.610s 307.645us 48 50 96.00
V2S sec_cm_constants_consistency keymgr_hwsw_invalid_input 44.310s 9.191ms 49 50 98.00
V2S sec_cm_intersig_consistency keymgr_hwsw_invalid_input 44.310s 9.191ms 49 50 98.00
V2S sec_cm_hw_key_sw_noaccess keymgr_random 48.820s 3.545ms 48 50 96.00
V2S sec_cm_output_keys_ctrl_redun keymgr_sideload_protect 15.220s 3.361ms 50 50 100.00
V2S sec_cm_ctrl_fsm_sparse keymgr_sec_cm 14.390s 568.226us 5 5 100.00
V2S sec_cm_data_fsm_sparse keymgr_sec_cm 14.390s 568.226us 5 5 100.00
V2S sec_cm_ctrl_fsm_local_esc keymgr_sec_cm 14.390s 568.226us 5 5 100.00
V2S sec_cm_ctrl_fsm_consistency keymgr_custom_cm 21.050s 833.394us 36 50 72.00
V2S sec_cm_ctrl_fsm_global_esc keymgr_lc_disable 7.610s 307.645us 48 50 96.00
V2S sec_cm_ctrl_ctr_redun keymgr_sec_cm 14.390s 568.226us 5 5 100.00
V2S sec_cm_kmac_if_fsm_sparse keymgr_sec_cm 14.390s 568.226us 5 5 100.00
V2S sec_cm_kmac_if_ctr_redun keymgr_sec_cm 14.390s 568.226us 5 5 100.00
V2S sec_cm_kmac_if_cmd_ctrl_consistency keymgr_custom_cm 21.050s 833.394us 36 50 72.00
V2S sec_cm_kmac_if_done_ctrl_consistency keymgr_custom_cm 21.050s 833.394us 36 50 72.00
V2S sec_cm_reseed_ctr_redun keymgr_sec_cm 14.390s 568.226us 5 5 100.00
V2S sec_cm_side_load_sel_ctrl_consistency keymgr_custom_cm 21.050s 833.394us 36 50 72.00
V2S sec_cm_sideload_ctrl_fsm_sparse keymgr_sec_cm 14.390s 568.226us 5 5 100.00
V2S sec_cm_ctrl_key_integrity keymgr_custom_cm 21.050s 833.394us 36 50 72.00
V2S TOTAL 113 165 68.48
V3 stress_all_with_rand_reset keymgr_stress_all_with_rand_reset 21.620s 1.565ms 33 50 66.00
V3 TOTAL 33 50 66.00
TOTAL 987 1110 88.92

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.78 99.10 98.15 98.34 100.00 99.01 98.61 91.23

Failure Buckets