KMAC/MASKED Simulation Results

Sunday March 23 2025 00:10:17 UTC

GitHub Revision: `27fc640f8d`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.461m	4.215ms	49	50	98.00
V1	csr_hw_reset	kmac_csr_hw_reset	2.690s	223.038us	5	5	100.00
V1	csr_rw	kmac_csr_rw	2.800s	59.079us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	17.450s	1.261ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	10.160s	435.181us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	4.280s	335.698us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	2.800s	59.079us	20	20	100.00
		kmac_csr_aliasing	10.160s	435.181us	5	5	100.00
V1	mem_walk	kmac_mem_walk	2.150s	12.295us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	2.960s	43.252us	5	5	100.00
V1		TOTAL			114	115	99.13
V2	long_msg_and_output	kmac_long_msg_and_output	1.016h	181.067ms	50	50	100.00
V2	burst_write	kmac_burst_write	22.858m	137.643ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	32.414m	382.758ms	5	5	100.00
		kmac_test_vectors_sha3_256	31.765m	92.267ms	5	5	100.00
		kmac_test_vectors_sha3_384	29.603m	113.725ms	5	5	100.00
		kmac_test_vectors_sha3_512	17.901m	32.460ms	5	5	100.00
		kmac_test_vectors_shake_128	32.148m	20.708ms	5	5	100.00
		kmac_test_vectors_shake_256	34.924m	86.601ms	5	5	100.00
		kmac_test_vectors_kmac	4.470s	64.391us	5	5	100.00
		kmac_test_vectors_kmac_xof	4.650s	229.412us	5	5	100.00
V2	sideload	kmac_sideload	8.185m	18.810ms	50	50	100.00
V2	app	kmac_app	6.471m	55.932ms	50	50	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	6.792m	49.790ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	6.242m	128.779ms	50	50	100.00
V2	error	kmac_error	8.547m	200.000ms	48	50	96.00
V2	key_error	kmac_key_error	20.180s	22.317ms	50	50	100.00
V2	sideload_invalid	kmac_sideload_invalid	10.540s	1.237ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	52.300s	17.251ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	23.730s	1.965ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	57.380s	10.346ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	50.660s	3.597ms	50	50	100.00
V2	stress_all	kmac_stress_all	46.614m	374.328ms	49	50	98.00
V2	intr_test	kmac_intr_test	2.450s	20.703us	50	50	100.00
V2	alert_test	kmac_alert_test	2.430s	27.467us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	6.130s	175.057us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	6.130s	175.057us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	2.690s	223.038us	5	5	100.00
		kmac_csr_rw	2.800s	59.079us	20	20	100.00
		kmac_csr_aliasing	10.160s	435.181us	5	5	100.00
		kmac_same_csr_outstanding	4.480s	439.835us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	2.690s	223.038us	5	5	100.00
		kmac_csr_rw	2.800s	59.079us	20	20	100.00
		kmac_csr_aliasing	10.160s	435.181us	5	5	100.00
		kmac_same_csr_outstanding	4.480s	439.835us	20	20	100.00
V2		TOTAL			737	740	99.59
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	3.170s	454.521us	4	20	20.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	3.170s	454.521us	4	20	20.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	3.170s	454.521us	4	20	20.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	3.170s	454.521us	4	20	20.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	4.020s	239.923us	4	20	20.00
V2S	tl_intg_err	kmac_sec_cm	2.146m	84.051ms	5	5	100.00
		kmac_tl_intg_err	6.560s	752.186us	16	20	80.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	6.560s	752.186us	16	20	80.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	50.660s	3.597ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.461m	4.215ms	49	50	98.00
V2S	sec_cm_key_sideload	kmac_sideload	8.185m	18.810ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	3.170s	454.521us	4	20	20.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	2.146m	84.051ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	2.146m	84.051ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	2.146m	84.051ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.461m	4.215ms	49	50	98.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	50.660s	3.597ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	2.146m	84.051ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	6.362m	15.033ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.461m	4.215ms	49	50	98.00
V2S		TOTAL			39	75	52.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	3.326m	23.770ms	5	10	50.00
V3		TOTAL			5	10	50.00
		TOTAL			895	940	95.21

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.32	99.18	94.40	99.89	79.58	97.09	99.36	97.72

Failure Buckets

UVM_FATAL (alert_receiver_driver.sv:145) [driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q has 27 failures:

Test kmac_shadow_reg_errors_with_csr_rw has 11 failures.

0.kmac_shadow_reg_errors_with_csr_rw.104911158434600229558966939421212614413817895696628040922148091713480926448967
Line 76, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/0.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

  UVM_FATAL @  46237815 ps: (alert_receiver_driver.sv:145) [uvm_test_top.env.m_alert_agent_fatal_fault_err.driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q
  UVM_INFO @  46237815 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.kmac_shadow_reg_errors_with_csr_rw.34993937053531143373049987134428615236128659801439787228313091756030683291257
Line 75, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/3.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

  UVM_FATAL @  81876845 ps: (alert_receiver_driver.sv:145) [uvm_test_top.env.m_alert_agent_fatal_fault_err.driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q
  UVM_INFO @  81876845 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 9 more failures.

Test kmac_shadow_reg_errors has 16 failures.

1.kmac_shadow_reg_errors.67448452416749938305318796336279670314014312430963743485106402116568121257945
Line 75, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/1.kmac_shadow_reg_errors/latest/run.log

  UVM_FATAL @  92416243 ps: (alert_receiver_driver.sv:145) [uvm_test_top.env.m_alert_agent_fatal_fault_err.driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q
  UVM_INFO @  92416243 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.kmac_shadow_reg_errors.55989381743902329628150018279925150888934766069903445411917533673771335994120
Line 75, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/2.kmac_shadow_reg_errors/latest/run.log

  UVM_FATAL @  10176992 ps: (alert_receiver_driver.sv:145) [uvm_test_top.env.m_alert_agent_fatal_fault_err.driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q
  UVM_INFO @  10176992 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 14 more failures.

Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 8 failures:

Test kmac_shadow_reg_errors_with_csr_rw has 4 failures.

7.kmac_shadow_reg_errors_with_csr_rw.86974923940895567330797055066854427969696280969819561792098068822558899914607
Line 76, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/7.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[41] & 'hffffffff)))'
  UVM_ERROR @  23644817 ps: (kmac_csr_assert_fpv.sv:502) [ASSERT FAILED] prefix_2_rd_A
  UVM_INFO @  23644817 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

8.kmac_shadow_reg_errors_with_csr_rw.10918748851307757012894961081826402118173548918587037319969473097455866442430
Line 76, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/8.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[43] & 'hffffffff)))'
  UVM_ERROR @  39996242 ps: (kmac_csr_assert_fpv.sv:512) [ASSERT FAILED] prefix_4_rd_A
  UVM_INFO @  39996242 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

Test kmac_tl_intg_err has 4 failures.

7.kmac_tl_intg_err.6358986966441415208379201970199395062454020743307704810505162211413568986176
Line 79, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/7.kmac_tl_intg_err/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[45] & 'hffffffff)))'
  UVM_ERROR @  10391182 ps: (kmac_csr_assert_fpv.sv:522) [ASSERT FAILED] prefix_6_rd_A
  UVM_INFO @  10391182 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

8.kmac_tl_intg_err.36779636328987584572428570298609799425343138766198399918613349130899590080131
Line 82, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/8.kmac_tl_intg_err/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[40] & 'hffffffff)))'
  UVM_ERROR @  11951604 ps: (kmac_csr_assert_fpv.sv:497) [ASSERT FAILED] prefix_1_rd_A
  UVM_INFO @  11951604 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

UVM_ERROR (kmac_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 5 failures:
- Test kmac_stress_all_with_rand_reset has 5 failures.
  - 1.kmac_stress_all_with_rand_reset.37597261035525010460190905526744590801185500463323734137638352954437992350686
    Line 111, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2726049878 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483704 [0x80000038]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 2726049878 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 4.kmac_stress_all_with_rand_reset.22852852139617828264726328454516696050836728061547550295959081108512001901571
    Line 132, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/4.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 6646507814 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483704 [0x80000038]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 6646507814 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 3 more failures.
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: * has 2 failures:
- Test kmac_smoke has 1 failures.
  - 15.kmac_smoke.1433097674289735854722388702826897258920815992830481627429946214944809874564
    Line 72, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/15.kmac_smoke/latest/run.log
```
  UVM_ERROR @  56239788 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  56239788 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_stress_all has 1 failures.
  - 33.kmac_stress_all.35278667271855068895653793809820812401274818212367849278803727999788675292725
    Line 74, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/33.kmac_stress_all/latest/run.log
```
  UVM_ERROR @ 171950887 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @ 171950887 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:969) [kmac_common_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == * (* [*] vs * [*]) fatal error fatal_fault_err does not trigger! has 1 failures:
- Test kmac_shadow_reg_errors_with_csr_rw has 1 failures.
  - 18.kmac_shadow_reg_errors_with_csr_rw.85165343301476079752370196215564072017983018161719946990276364268805529340111
    Line 75, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/18.kmac_shadow_reg_errors_with_csr_rw/latest/run.log
```
  UVM_ERROR @  69803997 ps: (cip_base_vseq.sv:969) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_fault_err does not trigger!
  UVM_INFO @  69803997 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '(rand_valid_o || $past(seed_done))' has 1 failures:
- Test kmac_error has 1 failures.
  - 25.kmac_error.27837681737687417520786848488970517988755319913241534826379792086206252695866
    Line 73, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/25.kmac_error/latest/run.log
```
      Offending '(rand_valid_o || $past(seed_done))'
  UVM_ERROR @ 164411790 ps: (kmac_entropy.sv:457) [ASSERT FAILED] ConsumeNotAssertWhenNotValid_M
  UVM_INFO @ 164411790 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test kmac_error has 1 failures.
  - 39.kmac_error.50042627113540367507800541273223508530157703738806099963880837166380652966186
    Line 233, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/39.kmac_error/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```